[PATCH v3 0/8] RISC-V: Implement support for big endian targets

[PATCH v3 0/8] RISC-V: Implement support for big endian targets

[Marcus Comstedt]

This is an updated patch series for big endian RISC-V support.
Changes since v2:

 * gas now defaults to big endian when the triplet is riscvNNbe*-*-*.

 * TARGET_BYTES_BIG_ENDIAN is now defined by tc-risc.h only if it is
   not already defined by config.h.

 * Modified riscv_is_insn_reloc to never shift a 64-bit value 64 bits,
   as this is undefined behaviour in ISO C.

 * Fixed byteorder of alignment nop:s.

 * Updated the gas and ld testsuites to handle big endian

All gas and ld testsuite fails are fixed.  What remains is

  XPASS: ld-elf/compressed1d

which might be unrelated (I haven't checked if it also XPASSes for
little endian).

gdb has 114 testsuite failures, which might be as expected since I
haven't actually done any work on gdb (yet)...


  // Marcus

[PATCH v3 1/8] RISC-V: Support assembly and disassembly in big endian mode

[Marcus Comstedt]

bfd/
	* config.bfd: Add riscv_elf32_be_vec and riscv_elf64_be_vec.
	* configure.ac: Likewise.
	* configure: Regenerate.
	* elfnn-riscv.c: (riscv_elf_object_p): Recognize elf32-bigriscv
	as 32-bit mach.
	(TARGET_BIG_SYM, TARGET_BIG_NAME): Add them.
	* targets.c: Add riscv_elf32_be_vec and riscv_elf64_be_vec.

gas/
	* config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv
	and elf32-bigriscv.
	(install_insn): Always write instructions as little endian.
	(md_number_to_chars): Write data in target endianness.
	(options): Add OPTION_BIG_ENDIAN and OPTION_LITTLE_ENDIAN.
	(md_longopts): Likewise.
	(md_parse_option): Likewise.
	* config/tc-riscv.h: Only define TARGET_BYTES_BIG_ENDIAN if not
	already defined.
---
 bfd/config.bfd        |  4 ++--
 bfd/configure         |  2 ++
 bfd/configure.ac      |  2 ++
 bfd/elfnn-riscv.c     |  5 ++++-
 bfd/targets.c         |  4 ++++
 gas/config/tc-riscv.c | 24 +++++++++++++++++++++---
 gas/config/tc-riscv.h |  2 ++
 7 files changed, 37 insertions(+), 6 deletions(-)

diff --git a/bfd/config.bfd b/bfd/config.bfd
index fdc6dbe3dd..2ae8b1a4cc 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -1160,12 +1160,12 @@ case "${targ}" in
 #ifdef BFD64
   riscv-*-* | riscv32*-*-*)
     targ_defvec=riscv_elf32_vec
-    targ_selvecs="riscv_elf32_vec riscv_elf64_vec"
+    targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
     want64=true
     ;;
   riscv64*-*-*)
     targ_defvec=riscv_elf64_vec
-    targ_selvecs="riscv_elf32_vec riscv_elf64_vec"
+    targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
     want64=true
     ;;
 #endif
diff --git a/bfd/configure b/bfd/configure
index 5d84aed069..1460bbdfba 100755
--- a/bfd/configure
+++ b/bfd/configure
@@ -14919,6 +14919,8 @@ do
     pru_elf32_vec)		 tb="$tb elf32-pru.lo elf32.lo $elf" ;;
     riscv_elf32_vec)		 tb="$tb elf32-riscv.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf" ;;
     riscv_elf64_vec)		 tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf"; target_size=64 ;;
+    riscv_elf32_be_vec)		 tb="$tb elf32-riscv.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf" ;;
+    riscv_elf64_be_vec)		 tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf"; target_size=64 ;;
     rl78_elf32_vec)		 tb="$tb elf32-rl78.lo elf32.lo $elf" ;;
     rs6000_xcoff64_vec)		 tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
     rs6000_xcoff64_aix_vec)	 tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
diff --git a/bfd/configure.ac b/bfd/configure.ac
index 5ec4d4f0b4..4813e661aa 100644
--- a/bfd/configure.ac
+++ b/bfd/configure.ac
@@ -625,6 +625,8 @@ do
     pru_elf32_vec)		 tb="$tb elf32-pru.lo elf32.lo $elf" ;;
     riscv_elf32_vec)		 tb="$tb elf32-riscv.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf" ;;
     riscv_elf64_vec)		 tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf"; target_size=64 ;;
+    riscv_elf32_be_vec)		 tb="$tb elf32-riscv.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf" ;;
+    riscv_elf64_be_vec)		 tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf"; target_size=64 ;;
     rl78_elf32_vec)		 tb="$tb elf32-rl78.lo elf32.lo $elf" ;;
     rs6000_xcoff64_vec)		 tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
     rs6000_xcoff64_aix_vec)	 tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 20944c8109..618fe9319f 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -4943,7 +4943,8 @@ static bfd_boolean
 riscv_elf_object_p (bfd *abfd)
 {
   /* There are only two mach types in RISCV currently.  */
-  if (strcmp (abfd->xvec->name, "elf32-littleriscv") == 0)
+  if (strcmp (abfd->xvec->name, "elf32-littleriscv") == 0 ||
+      strcmp (abfd->xvec->name, "elf32-bigriscv") == 0)
     bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv32);
   else
     bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv64);
@@ -4962,6 +4963,8 @@ riscv_elf_obj_attrs_arg_type (int tag)
 
 #define TARGET_LITTLE_SYM		riscv_elfNN_vec
 #define TARGET_LITTLE_NAME		"elfNN-littleriscv"
+#define TARGET_BIG_SYM			riscv_elfNN_be_vec
+#define TARGET_BIG_NAME			"elfNN-bigriscv"
 
 #define elf_backend_reloc_type_class	     riscv_reloc_type_class
 
diff --git a/bfd/targets.c b/bfd/targets.c
index 8ae5c489fc..8fa8f693fb 100644
--- a/bfd/targets.c
+++ b/bfd/targets.c
@@ -843,6 +843,8 @@ extern const bfd_target powerpc_xcoff_vec;
 extern const bfd_target pru_elf32_vec;
 extern const bfd_target riscv_elf32_vec;
 extern const bfd_target riscv_elf64_vec;
+extern const bfd_target riscv_elf32_be_vec;
+extern const bfd_target riscv_elf64_be_vec;
 extern const bfd_target rl78_elf32_vec;
 extern const bfd_target rs6000_xcoff64_vec;
 extern const bfd_target rs6000_xcoff64_aix_vec;
@@ -1237,6 +1239,8 @@ static const bfd_target * const _bfd_target_vector[] =
 #ifdef BFD64
 	&riscv_elf32_vec,
 	&riscv_elf64_vec,
+	&riscv_elf32_be_vec,
+	&riscv_elf64_be_vec,
 #endif
 	&rl78_elf32_vec,
 
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index ca7e52a169..622eb48448 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -445,7 +445,10 @@ static char *expr_end;
 const char *
 riscv_target_format (void)
 {
-  return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
+  if (target_big_endian)
+    return xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv";
+  else
+    return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
 }
 
 /* Return the length of instruction INSN.  */
@@ -474,7 +477,7 @@ static void
 install_insn (const struct riscv_cl_insn *insn)
 {
   char *f = insn->frag->fr_literal + insn->where;
-  md_number_to_chars (f, insn->insn_opcode, insn_length (insn));
+  number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn));
 }
 
 /* Move INSN to offset WHERE in FRAG.  Adjust the fixups accordingly
@@ -2662,7 +2665,10 @@ md_atof (int type, char *litP, int *sizeP)
 void
 md_number_to_chars (char *buf, valueT val, int n)
 {
-  number_to_chars_littleendian (buf, val, n);
+  if (target_big_endian)
+    number_to_chars_bigendian (buf, val, n);
+  else
+    number_to_chars_littleendian (buf, val, n);
 }
 
 const char *md_shortopts = "O::g::G:";
@@ -2681,6 +2687,8 @@ enum options
   OPTION_NO_CSR_CHECK,
   OPTION_MISA_SPEC,
   OPTION_MPRIV_SPEC,
+  OPTION_BIG_ENDIAN,
+  OPTION_LITTLE_ENDIAN,
   OPTION_END_OF_ENUM
 };
 
@@ -2699,6 +2707,8 @@ struct option md_longopts[] =
   {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
   {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
   {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
+  {"mbig-endian", no_argument, NULL, OPTION_BIG_ENDIAN},
+  {"mlittle-endian", no_argument, NULL, OPTION_LITTLE_ENDIAN},
 
   {NULL, no_argument, NULL, 0}
 };
@@ -2777,6 +2787,14 @@ md_parse_option (int c, const char *arg)
     case OPTION_MPRIV_SPEC:
       return riscv_set_default_priv_spec (arg);
 
+    case OPTION_BIG_ENDIAN:
+      target_big_endian = 1;
+      break;
+
+    case OPTION_LITTLE_ENDIAN:
+      target_big_endian = 0;
+      break;
+
     default:
       return 0;
     }
diff --git a/gas/config/tc-riscv.h b/gas/config/tc-riscv.h
index 43d751ad0d..fb0e743cc2 100644
--- a/gas/config/tc-riscv.h
+++ b/gas/config/tc-riscv.h
@@ -28,7 +28,9 @@
 struct frag;
 struct expressionS;
 
+#ifndef TARGET_BYTES_BIG_ENDIAN
 #define TARGET_BYTES_BIG_ENDIAN 0
+#endif
 
 #define TARGET_ARCH bfd_arch_riscv
 
-- 
2.26.2

[PATCH v3 2/8] RISC-V: Fix relocations in big endian mode

[Marcus Comstedt]

bfd/
	* elfnn-riscv.c: (riscv_get_insn, riscv_put_insn): Add them.
	(riscv_is_insn_reloc): Add it.
	(perform_relocation): Use either target endian or fixed little
	endian memory access functions depending on whether the relocation
	is against data or an instruction.
	(riscv_zero_pcrel_hi_reloc, riscv_elf_relocate_section),
	(riscv_elf_finish_dynamic_symbol, riscv_elf_finish_dynamic_sections),
	(_bfd_riscv_relax_call, _bfd_riscv_relax_lui, _bfd_riscv_relax_align),
	(_bfd_riscv_relax_pc): Use fixed little endian memory access
	functions for accesing instructions.
---
 bfd/elfnn-riscv.c | 101 +++++++++++++++++++++++++++++++---------------
 1 file changed, 69 insertions(+), 32 deletions(-)

diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 618fe9319f..5b1c68f23c 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -33,6 +33,13 @@
 #include "opcode/riscv.h"
 #include "objalloc.h"
 
+#ifdef HAVE_LIMITS_H
+#include <limits.h>
+#endif
+#ifndef CHAR_BIT
+#define CHAR_BIT 8
+#endif
+
 /* Internal relocations used exclusively by the relaxation pass.  */
 #define R_RISCV_DELETE (R_RISCV_max + 1)
 
@@ -126,6 +133,18 @@ struct riscv_elf_link_hash_table
 };
 
 
+/* Instruction access functions. */
+#define riscv_get_insn(bits, ptr)		\
+  ((bits) == 16 ? bfd_getl16 (ptr)		\
+   : (bits) == 32 ? bfd_getl32 (ptr)		\
+   : (bits) == 64 ? bfd_getl64 (ptr)		\
+   : (abort (), (bfd_vma) - 1))
+#define riscv_put_insn(bits, val, ptr)		\
+  ((bits) == 16 ? bfd_putl16 (val, ptr)		\
+   : (bits) == 32 ? bfd_putl32 (val, ptr)	\
+   : (bits) == 64 ? bfd_putl64 (val, ptr)	\
+   : (abort (), (void) 0))
+
 /* Get the RISC-V ELF linker hash table from a link_info structure.  */
 #define riscv_elf_hash_table(p) \
   ((is_elf_hash_table ((p)->hash)					\
@@ -152,6 +171,18 @@ riscv_elf_append_rela (bfd *abfd, asection *s, Elf_Internal_Rela *rel)
   bed->s->swap_reloca_out (abfd, rel, loc);
 }
 
+/* Return true if a relocation is modifying an instruction. */
+
+static bfd_boolean
+riscv_is_insn_reloc (const reloc_howto_type *howto)
+{
+  /* Heuristic: A multibyte destination with a nontrivial mask
+     is an instruction */
+  return howto->bitsize > 8 && howto->dst_mask != 0 &&
+    ~(howto->dst_mask | (howto->bitsize < sizeof(bfd_vma) * CHAR_BIT?
+			 (MINUS_ONE << howto->bitsize) : (bfd_vma)0)) != 0;
+}
+
 /* PLT/GOT stuff.  */
 
 #define PLT_HEADER_INSNS 8
@@ -1636,10 +1667,10 @@ perform_relocation (const reloc_howto_type *howto,
 	  /* Linker relaxation can convert an address equal to or greater than
 	     0x800 to slightly below 0x800.  C.LUI does not accept zero as a
 	     valid immediate.  We can fix this by converting it to a C.LI.  */
-	  bfd_vma insn = bfd_get (howto->bitsize, input_bfd,
-				  contents + rel->r_offset);
+	  bfd_vma insn = riscv_get_insn (howto->bitsize,
+					 contents + rel->r_offset);
 	  insn = (insn & ~MATCH_C_LUI) | MATCH_C_LI;
-	  bfd_put (howto->bitsize, input_bfd, insn, contents + rel->r_offset);
+	  riscv_put_insn (howto->bitsize, insn, contents + rel->r_offset);
 	  value = ENCODE_RVC_IMM (0);
 	}
       else if (!VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (value)))
@@ -1675,9 +1706,16 @@ perform_relocation (const reloc_howto_type *howto,
       return bfd_reloc_notsupported;
     }
 
-  bfd_vma word = bfd_get (howto->bitsize, input_bfd, contents + rel->r_offset);
+  bfd_vma word;
+  if (riscv_is_insn_reloc (howto))
+    word = riscv_get_insn (howto->bitsize, contents + rel->r_offset);
+  else
+    word = bfd_get (howto->bitsize, input_bfd, contents + rel->r_offset);
   word = (word & ~howto->dst_mask) | (value & howto->dst_mask);
-  bfd_put (howto->bitsize, input_bfd, word, contents + rel->r_offset);
+  if (riscv_is_insn_reloc (howto))
+    riscv_put_insn (howto->bitsize, word, contents + rel->r_offset);
+  else
+    bfd_put (howto->bitsize, input_bfd, word, contents + rel->r_offset);
 
   return bfd_reloc_ok;
 }
@@ -1755,7 +1793,7 @@ riscv_zero_pcrel_hi_reloc (Elf_Internal_Rela *rel,
 			   bfd_vma addr,
 			   bfd_byte *contents,
 			   const reloc_howto_type *howto,
-			   bfd *input_bfd)
+			   bfd *input_bfd ATTRIBUTE_UNUSED)
 {
   /* We may need to reference low addreses in PC-relative modes even when the
    * PC is far away from these addresses.  For example, undefweak references
@@ -1781,9 +1819,9 @@ riscv_zero_pcrel_hi_reloc (Elf_Internal_Rela *rel,
 
   rel->r_info = ELFNN_R_INFO(addr, R_RISCV_HI20);
 
-  bfd_vma insn = bfd_get(howto->bitsize, input_bfd, contents + rel->r_offset);
+  bfd_vma insn = riscv_get_insn(howto->bitsize, contents + rel->r_offset);
   insn = (insn & ~MASK_AUIPC) | MATCH_LUI;
-  bfd_put(howto->bitsize, input_bfd, insn, contents + rel->r_offset);
+  riscv_put_insn(howto->bitsize, insn, contents + rel->r_offset);
   return TRUE;
 }
 
@@ -2371,10 +2409,9 @@ riscv_elf_relocate_section (bfd *output_bfd,
 	      && (!bfd_link_pic (info) || h->plt.offset == MINUS_ONE))
 	    {
 	      /* We can use x0 as the base register.  */
-	      bfd_vma insn = bfd_get_32 (input_bfd,
-					 contents + rel->r_offset + 4);
+	      bfd_vma insn = bfd_getl32 (contents + rel->r_offset + 4);
 	      insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
-	      bfd_put_32 (input_bfd, insn, contents + rel->r_offset + 4);
+	      bfd_putl32 (insn, contents + rel->r_offset + 4);
 	      /* Set the relocation value so that we get 0 after the pc
 		 relative adjustment.  */
 	      relocation = sec_addr (input_section) + rel->r_offset;
@@ -2407,10 +2444,10 @@ riscv_elf_relocate_section (bfd *output_bfd,
 	  if (VALID_ITYPE_IMM (relocation + rel->r_addend))
 	    {
 	      /* We can use tp as the base register.  */
-	      bfd_vma insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
+	      bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
 	      insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
 	      insn |= X_TP << OP_SH_RS1;
-	      bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
+	      bfd_putl32 (insn, contents + rel->r_offset);
 	    }
 	  else
 	    r = bfd_reloc_overflow;
@@ -2424,14 +2461,14 @@ riscv_elf_relocate_section (bfd *output_bfd,
 	    if (x0_base || VALID_ITYPE_IMM (relocation + rel->r_addend - gp))
 	      {
 		/* We can use x0 or gp as the base register.  */
-		bfd_vma insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
+		bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
 		insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
 		if (!x0_base)
 		  {
 		    rel->r_addend -= gp;
 		    insn |= X_GP << OP_SH_RS1;
 		  }
-		bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
+		bfd_putl32 (insn, contents + rel->r_offset);
 	      }
 	    else
 	      r = bfd_reloc_overflow;
@@ -2855,7 +2892,7 @@ riscv_elf_finish_dynamic_symbol (bfd *output_bfd,
 	return FALSE;
 
       for (i = 0; i < PLT_ENTRY_INSNS; i++)
-	bfd_put_32 (output_bfd, plt_entry[i], loc + 4*i);
+	bfd_putl32 (plt_entry[i], loc + 4*i);
 
       /* Fill in the initial value of the .got.plt entry.  */
       loc = gotplt->contents + (got_address - sec_addr (gotplt));
@@ -3152,7 +3189,7 @@ riscv_elf_finish_dynamic_sections (bfd *output_bfd,
 	    return ret;
 
 	  for (i = 0; i < PLT_HEADER_INSNS; i++)
-	    bfd_put_32 (output_bfd, plt_header[i], splt->contents + 4*i);
+	    bfd_putl32 (plt_header[i], splt->contents + 4*i);
 
 	  elf_section_data (splt->output_section)->this_hdr.sh_entsize
 	    = PLT_ENTRY_SIZE;
@@ -4142,8 +4179,8 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
   /* Shorten the function call.  */
   BFD_ASSERT (rel->r_offset + 8 <= sec->size);
 
-  auipc = bfd_get_32 (abfd, contents + rel->r_offset);
-  jalr = bfd_get_32 (abfd, contents + rel->r_offset + 4);
+  auipc = bfd_getl32 (contents + rel->r_offset);
+  jalr = bfd_getl32 (contents + rel->r_offset + 4);
   rd = (jalr >> OP_SH_RD) & OP_MASK_RD;
   rvc = rvc && VALID_RVC_J_IMM (foff);
 
@@ -4173,7 +4210,7 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
   /* Replace the R_RISCV_CALL reloc.  */
   rel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel->r_info), r_type);
   /* Replace the AUIPC.  */
-  bfd_put (8 * len, abfd, auipc, contents + rel->r_offset);
+  riscv_put_insn (8 * len, auipc, contents + rel->r_offset);
 
   /* Delete unnecessary JALR.  */
   *again = TRUE;
@@ -4247,9 +4284,9 @@ _bfd_riscv_relax_lui (bfd *abfd,
 	  if (undefined_weak)
 	    {
 	      /* Change the RS1 to zero.  */
-	      bfd_vma insn = bfd_get_32 (abfd, contents + rel->r_offset);
+	      bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
 	      insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
-	      bfd_put_32 (abfd, insn, contents + rel->r_offset);
+	      bfd_putl32 (insn, contents + rel->r_offset);
 	    }
 	  else
 	    rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
@@ -4259,9 +4296,9 @@ _bfd_riscv_relax_lui (bfd *abfd,
 	  if (undefined_weak)
 	    {
 	      /* Change the RS1 to zero.  */
-	      bfd_vma insn = bfd_get_32 (abfd, contents + rel->r_offset);
+	      bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
 	      insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
-	      bfd_put_32 (abfd, insn, contents + rel->r_offset);
+	      bfd_putl32 (insn, contents + rel->r_offset);
 	    }
 	  else
 	    rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
@@ -4292,13 +4329,13 @@ _bfd_riscv_relax_lui (bfd *abfd,
 			       : ELF_MAXPAGESIZE)))
     {
       /* Replace LUI with C.LUI if legal (i.e., rd != x0 and rd != x2/sp).  */
-      bfd_vma lui = bfd_get_32 (abfd, contents + rel->r_offset);
+      bfd_vma lui = bfd_getl32 (contents + rel->r_offset);
       unsigned rd = ((unsigned)lui >> OP_SH_RD) & OP_MASK_RD;
       if (rd == 0 || rd == X_SP)
 	return TRUE;
 
       lui = (lui & (OP_MASK_RD << OP_SH_RD)) | MATCH_C_LUI;
-      bfd_put_32 (abfd, lui, contents + rel->r_offset);
+      bfd_putl32 (lui, contents + rel->r_offset);
 
       /* Replace the R_RISCV_HI20 reloc.  */
       rel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel->r_info), R_RISCV_RVC_LUI);
@@ -4400,11 +4437,11 @@ _bfd_riscv_relax_align (bfd *abfd, asection *sec,
 
   /* Write as many RISC-V NOPs as we need.  */
   for (pos = 0; pos < (nop_bytes & -4); pos += 4)
-    bfd_put_32 (abfd, RISCV_NOP, contents + rel->r_offset + pos);
+    bfd_putl32 (RISCV_NOP, contents + rel->r_offset + pos);
 
   /* Write a final RVC NOP if need be.  */
   if (nop_bytes % 4 != 0)
-    bfd_put_16 (abfd, RVC_NOP, contents + rel->r_offset + pos);
+    bfd_putl16 (RVC_NOP, contents + rel->r_offset + pos);
 
   /* Delete the excess bytes.  */
   return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + nop_bytes,
@@ -4511,9 +4548,9 @@ _bfd_riscv_relax_pc  (bfd *abfd ATTRIBUTE_UNUSED,
 	    {
 	      /* Change the RS1 to zero, and then modify the relocation
 		 type to R_RISCV_LO12_I.  */
-	      bfd_vma insn = bfd_get_32 (abfd, contents + rel->r_offset);
+	      bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
 	      insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
-	      bfd_put_32 (abfd, insn, contents + rel->r_offset);
+	      bfd_putl32 (insn, contents + rel->r_offset);
 	      rel->r_info = ELFNN_R_INFO (sym, R_RISCV_LO12_I);
 	      rel->r_addend = hi_reloc.hi_addend;
 	    }
@@ -4529,9 +4566,9 @@ _bfd_riscv_relax_pc  (bfd *abfd ATTRIBUTE_UNUSED,
 	    {
 	      /* Change the RS1 to zero, and then modify the relocation
 		 type to R_RISCV_LO12_S.  */
-	      bfd_vma insn = bfd_get_32 (abfd, contents + rel->r_offset);
+	      bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
 	      insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
-	      bfd_put_32 (abfd, insn, contents + rel->r_offset);
+	      bfd_putl32 (insn, contents + rel->r_offset);
 	      rel->r_info = ELFNN_R_INFO (sym, R_RISCV_LO12_S);
 	      rel->r_addend = hi_reloc.hi_addend;
 	    }
-- 
2.26.2

[PATCH v3 3/8] RISC-V: Add big endian linker scripts

[Marcus Comstedt]

ld/
	* Makefile.am: (eelf32briscv.c, eelf32briscv_ilp32f.c),
	(eelf32briscv_ilp32.c): Add them.
	* Makefile.in: Regenerate.
	* emulparams/elf32briscv.sh: Add it.
	* emulparams/elf32briscv_ilp32.sh: Likewise.
	* emulparams/elf32briscv_ilp32f.sh: Likewise.
	* emulparams/elf64briscv.sh: Likewise.
	* emulparams/elf64briscv_lp64.sh: Likewise.
	* emulparams/elf64briscv_lp64f.sh: Likewise.
---
 ld/Makefile.am                      | 12 ++++++++++++
 ld/Makefile.in                      | 19 +++++++++++++++++++
 ld/emulparams/elf32briscv.sh        |  2 ++
 ld/emulparams/elf32briscv_ilp32.sh  |  2 ++
 ld/emulparams/elf32briscv_ilp32f.sh |  2 ++
 ld/emulparams/elf64briscv.sh        |  2 ++
 ld/emulparams/elf64briscv_lp64.sh   |  2 ++
 ld/emulparams/elf64briscv_lp64f.sh  |  2 ++
 8 files changed, 43 insertions(+)
 create mode 100644 ld/emulparams/elf32briscv.sh
 create mode 100644 ld/emulparams/elf32briscv_ilp32.sh
 create mode 100644 ld/emulparams/elf32briscv_ilp32f.sh
 create mode 100644 ld/emulparams/elf64briscv.sh
 create mode 100644 ld/emulparams/elf64briscv_lp64.sh
 create mode 100644 ld/emulparams/elf64briscv_lp64f.sh

diff --git a/ld/Makefile.am b/ld/Makefile.am
index 73144e730a..b5245f5b76 100644
--- a/ld/Makefile.am
+++ b/ld/Makefile.am
@@ -266,6 +266,9 @@ ALL_EMULATION_SOURCES = \
 	eelf32lriscv.c \
 	eelf32lriscv_ilp32f.c \
 	eelf32lriscv_ilp32.c \
+	eelf32briscv.c \
+	eelf32briscv_ilp32f.c \
+	eelf32briscv_ilp32.c \
 	eelf32rl78.c \
 	eelf32rx.c \
 	eelf32rx_linux.c \
@@ -435,6 +438,9 @@ ALL_64_EMULATION_SOURCES = \
 	eelf64lriscv.c \
 	eelf64lriscv_lp64f.c \
 	eelf64lriscv_lp64.c \
+	eelf64briscv.c \
+	eelf64briscv_lp64f.c \
+	eelf64briscv_lp64.c \
 	eelf64ltsmip.c \
 	eelf64ltsmip_fbsd.c \
 	eelf64mmix.c \
@@ -751,6 +757,9 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv_ilp32f.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv_ilp32.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv_ilp32f.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv_ilp32.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rl78.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rx.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rx_linux.Pc@am__quote@
@@ -916,6 +925,9 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64f.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv_lp64f.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv_lp64.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip_fbsd.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64mmix.Pc@am__quote@
diff --git a/ld/Makefile.in b/ld/Makefile.in
index 178ae49009..8d8cfb33a7 100644
--- a/ld/Makefile.in
+++ b/ld/Makefile.in
@@ -521,6 +521,7 @@ pdfdir = @pdfdir@
 prefix = @prefix@
 program_transform_name = @program_transform_name@
 psdir = @psdir@
+runstatedir = @runstatedir@
 sbindir = @sbindir@
 sharedstatedir = @sharedstatedir@
 srcdir = @srcdir@
@@ -755,6 +756,9 @@ ALL_EMULATION_SOURCES = \
 	eelf32lriscv.c \
 	eelf32lriscv_ilp32f.c \
 	eelf32lriscv_ilp32.c \
+	eelf32briscv.c \
+	eelf32briscv_ilp32f.c \
+	eelf32briscv_ilp32.c \
 	eelf32rl78.c \
 	eelf32rx.c \
 	eelf32rx_linux.c \
@@ -923,6 +927,9 @@ ALL_64_EMULATION_SOURCES = \
 	eelf64lriscv.c \
 	eelf64lriscv_lp64f.c \
 	eelf64lriscv_lp64.c \
+	eelf64briscv.c \
+	eelf64briscv_lp64f.c \
+	eelf64briscv_lp64.c \
 	eelf64ltsmip.c \
 	eelf64ltsmip_fbsd.c \
 	eelf64mmix.c \
@@ -1318,6 +1325,9 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bfinfd.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bmip.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bmipn32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv_ilp32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv_ilp32f.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bsmip.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32btsmip.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32btsmip_fbsd.Po@am__quote@
@@ -1403,6 +1413,9 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_nbsd.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bmip.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bpf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv_lp64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv_lp64f.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip_fbsd.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Po@am__quote@
@@ -2403,6 +2416,9 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv_ilp32f.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv_ilp32.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv_ilp32f.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv_ilp32.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rl78.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rx.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rx_linux.Pc@am__quote@
@@ -2568,6 +2584,9 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64f.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv_lp64f.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv_lp64.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip_fbsd.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64mmix.Pc@am__quote@
diff --git a/ld/emulparams/elf32briscv.sh b/ld/emulparams/elf32briscv.sh
new file mode 100644
index 0000000000..bad02bd5cf
--- /dev/null
+++ b/ld/emulparams/elf32briscv.sh
@@ -0,0 +1,2 @@
+source_sh ${srcdir}/emulparams/elf32lriscv.sh
+OUTPUT_FORMAT="elf32-bigriscv"
diff --git a/ld/emulparams/elf32briscv_ilp32.sh b/ld/emulparams/elf32briscv_ilp32.sh
new file mode 100644
index 0000000000..c150108d3a
--- /dev/null
+++ b/ld/emulparams/elf32briscv_ilp32.sh
@@ -0,0 +1,2 @@
+source_sh ${srcdir}/emulparams/elf32lriscv_ilp32.sh
+OUTPUT_FORMAT="elf32-bigriscv"
diff --git a/ld/emulparams/elf32briscv_ilp32f.sh b/ld/emulparams/elf32briscv_ilp32f.sh
new file mode 100644
index 0000000000..52117e6b0c
--- /dev/null
+++ b/ld/emulparams/elf32briscv_ilp32f.sh
@@ -0,0 +1,2 @@
+source_sh ${srcdir}/emulparams/elf32lriscv_ilp32f.sh
+OUTPUT_FORMAT="elf32-bigriscv"
diff --git a/ld/emulparams/elf64briscv.sh b/ld/emulparams/elf64briscv.sh
new file mode 100644
index 0000000000..86a429f10f
--- /dev/null
+++ b/ld/emulparams/elf64briscv.sh
@@ -0,0 +1,2 @@
+source_sh ${srcdir}/emulparams/elf64lriscv.sh
+OUTPUT_FORMAT="elf64-bigriscv"
diff --git a/ld/emulparams/elf64briscv_lp64.sh b/ld/emulparams/elf64briscv_lp64.sh
new file mode 100644
index 0000000000..b00717c31a
--- /dev/null
+++ b/ld/emulparams/elf64briscv_lp64.sh
@@ -0,0 +1,2 @@
+source_sh ${srcdir}/emulparams/elf64lriscv_lp64.sh
+OUTPUT_FORMAT="elf64-bigriscv"
diff --git a/ld/emulparams/elf64briscv_lp64f.sh b/ld/emulparams/elf64briscv_lp64f.sh
new file mode 100644
index 0000000000..a54a3f41c6
--- /dev/null
+++ b/ld/emulparams/elf64briscv_lp64f.sh
@@ -0,0 +1,2 @@
+source_sh ${srcdir}/emulparams/elf64lriscv_lp64f.sh
+OUTPUT_FORMAT="elf64-bigriscv"
-- 
2.26.2

[PATCH v3 4/8] RISC-V: Recognize riscvNNbe* as target

[Marcus Comstedt]

bfd/
	* config.bfd (riscvbe-*-*, riscv32be*-*-*),
	(riscv64be*-*-*): Add target.

gas/
	* configure.tgt: (riscv64be*, riscv32be*, riscvbe*): Add them.
	(riscv*-*-*): Remove little endian override.

ld/
	* configure.tgt: Add riscvbe-*-*, riscv32be*-*-*, riscv64be*-*-*,
	riscv32be*-*-linux*, and riscv64be*-*-linux*.
---
 bfd/config.bfd    | 10 ++++++++++
 config.sub        |  2 +-
 gas/configure.tgt |  4 +++-
 ld/configure.tgt  | 25 +++++++++++++++++++++----
 4 files changed, 35 insertions(+), 6 deletions(-)

diff --git a/bfd/config.bfd b/bfd/config.bfd
index 2ae8b1a4cc..f792bd01df 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -1158,11 +1158,21 @@ case "${targ}" in
     ;;
 
 #ifdef BFD64
+  riscvbe-*-* | riscv32be*-*-*)
+    targ_defvec=riscv_elf32_be_vec
+    targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
+    want64=true
+    ;;
   riscv-*-* | riscv32*-*-*)
     targ_defvec=riscv_elf32_vec
     targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
     want64=true
     ;;
+  riscv64be*-*-*)
+    targ_defvec=riscv_elf64_be_vec
+    targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
+    want64=true
+    ;;
   riscv64*-*-*)
     targ_defvec=riscv_elf64_vec
     targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
diff --git a/config.sub b/config.sub
index f02d43ad50..7bb0fa6b83 100755
--- a/config.sub
+++ b/config.sub
@@ -1227,7 +1227,7 @@ case $cpu-$vendor in
 			| powerpc | powerpc64 | powerpc64le | powerpcle | powerpcspe \
 			| pru \
 			| pyramid \
-			| riscv | riscv32 | riscv64 \
+			| riscv | riscv32 | riscv64 | riscvbe | riscv32be | riscv64be \
 			| rl78 | romp | rs6000 | rx \
 			| score \
 			| sh | shl \
diff --git a/gas/configure.tgt b/gas/configure.tgt
index cd60f21a74..91eb648513 100644
--- a/gas/configure.tgt
+++ b/gas/configure.tgt
@@ -89,7 +89,9 @@ case ${cpu} in
   pj*)			cpu_type=pj endian=big ;;
   powerpc*le*)		cpu_type=ppc endian=little ;;
   powerpc*)		cpu_type=ppc endian=big ;;
+  riscv64be*)		cpu_type=riscv endian=big arch=riscv64 ;;
   riscv64*)		cpu_type=riscv endian=little arch=riscv64 ;;
+  riscv32be*|riscvbe*)	cpu_type=riscv endian=big arch=riscv32 ;;
   riscv32* | riscv*)	cpu_type=riscv endian=little arch=riscv32 ;;
   rs6000*)		cpu_type=ppc ;;
   rl78*)		cpu_type=rl78 ;;
@@ -357,7 +359,7 @@ case ${generic_target} in
 
   pru-*-*)				fmt=elf ;;
 
-  riscv*-*-*)				fmt=elf endian=little ;;
+  riscv*-*-*)				fmt=elf ;;
 
   rx-*-linux*)				fmt=elf em=linux ;;
 
diff --git a/ld/configure.tgt b/ld/configure.tgt
index 70359301b5..1a5cd476c4 100644
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
@@ -738,21 +738,38 @@ powerpc-*-windiss*)	targ_emul=elf32ppcwindiss
 			;;
 pru*-*-*)		targ_emul=pruelf
 			;;
+riscv32be*-*-linux*)	targ_emul=elf32briscv
+			targ_extra_emuls="elf32briscv_ilp32f elf32briscv_ilp32 elf64briscv elf64briscv_lp64f elf64briscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64"
+			targ_extra_libpath=$targ_extra_emuls
+			;;
 riscv32*-*-linux*)	targ_emul=elf32lriscv
-			targ_extra_emuls="elf32lriscv_ilp32f elf32lriscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64"
+			targ_extra_emuls="elf32lriscv_ilp32f elf32lriscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64 elf32briscv elf32briscv_ilp32f elf32briscv_ilp32 elf64briscv elf64briscv_lp64f elf64briscv_lp64"
+			targ_extra_libpath=$targ_extra_emuls
+			;;
+riscvbe-*-* | riscv32be*-*-*)
+			targ_emul=elf32briscv
+			targ_extra_emuls="elf64briscv elf32lriscv elf64lriscv"
 			targ_extra_libpath=$targ_extra_emuls
 			;;
 riscv-*-* | riscv32*-*-*)
 			targ_emul=elf32lriscv
-			targ_extra_emuls="elf64lriscv"
+			targ_extra_emuls="elf64lriscv elf32briscv elf64briscv"
+			targ_extra_libpath=$targ_extra_emuls
+			;;
+riscv64be*-*-linux*)	targ_emul=elf64briscv
+			targ_extra_emuls="elf64briscv_lp64f elf64briscv_lp64 elf32briscv elf32briscv_ilp32f elf32briscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32"
 			targ_extra_libpath=$targ_extra_emuls
 			;;
 riscv64*-*-linux*)	targ_emul=elf64lriscv
-			targ_extra_emuls="elf64lriscv_lp64f elf64lriscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32"
+			targ_extra_emuls="elf64lriscv_lp64f elf64lriscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32 elf64briscv elf64briscv_lp64f elf64briscv_lp64 elf32briscv elf32briscv_ilp32f elf32briscv_ilp32"
+			targ_extra_libpath=$targ_extra_emuls
+			;;
+riscv64be*-*-*)		targ_emul=elf64briscv
+			targ_extra_emuls="elf32briscv elf64lriscv elf32lriscv"
 			targ_extra_libpath=$targ_extra_emuls
 			;;
 riscv64*-*-*)		targ_emul=elf64lriscv
-			targ_extra_emuls="elf32lriscv"
+			targ_extra_emuls="elf32lriscv elf64briscv elf32briscv"
 			targ_extra_libpath=$targ_extra_emuls
 			;;
 rs6000-*-aix[5-9]*)	targ_emul=aix5rs6
-- 
2.26.2

[PATCH v3 5/8] RISC-V: Fix branch frag conversion on big endian

[Marcus Comstedt]

gas/
	config/tc-riscv.c: (md_convert_frag_branch): Use fixed little
	endian memory access functions for accesing instructions.
---
 gas/config/tc-riscv.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 622eb48448..4ede91847f 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -3486,14 +3486,14 @@ md_convert_frag_branch (fragS *fragp)
       insn = bfd_getl32 (buf);
       insn ^= MATCH_BEQ ^ MATCH_BNE;
       insn |= ENCODE_SBTYPE_IMM (8);
-      md_number_to_chars ((char *) buf, insn, 4);
+      bfd_putl32 (insn, buf);
       buf += 4;
 
     jump:
       /* Jump to the target.  */
       fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
 			  4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
-      md_number_to_chars ((char *) buf, MATCH_JAL, 4);
+      bfd_putl32 (MATCH_JAL, buf);
       buf += 4;
       break;
 
-- 
2.26.2

[PATCH v3 6/8] RISC-V: Mention -mbig-endian and -mlittle-endian in doc

[Marcus Comstedt]

gas/
	* doc/as.texi: Add -mlittle-endian and -mbig-endian to docs.
	* doc/c-riscv.texi: Likewise.
---
 gas/doc/as.texi      |  1 +
 gas/doc/c-riscv.texi | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 983cec3cbf..2f8142472f 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -536,6 +536,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-fpic}|@b{-fPIC}|@b{-fno-pic}]
    [@b{-march}=@var{ISA}]
    [@b{-mabi}=@var{ABI}]
+   [@b{-mlittle}|@b{-mlittle-endian}|@b{-mbig}|@b{-mbig-endian}]
 @end ifset
 @ifset RL78
 
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index d63b1f3990..481bfbbfbb 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -99,6 +99,16 @@ read-only CSR can not be written by the CSR instructions.
 @cindex @samp{-mno-csr-check} option, RISC-V
 @item -mno-csr-check
 Don't do CSR checking.
+
+@cindex @samp{-mlittle} option, RISC-V
+@cindex @samp{-mlittle-endian} option, RISC-V
+@item -mlittle, -mlittle-endian
+Generate code for a little endian machine.
+
+@cindex @samp{-mbig} option, RISC-V
+@cindex @samp{-mbig-endian} option, RISC-V
+@item -mbig, -mbig-endian
+Generate code for a big endian machine.
 @end table
 @c man end
 
-- 
2.26.2

[PATCH v3 7/8] RISC-V: Fix nop generation on big endian

[Marcus Comstedt]

gas/
	* config/tc-riscv.c: (riscv_make_nops):  Use fixed little
	endian memory access functions for storing instructions.
---
 gas/config/tc-riscv.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 4ede91847f..4c31229864 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -3276,13 +3276,13 @@ riscv_make_nops (char *buf, bfd_vma bytes)
   /* Use at most one 2-byte NOP.  */
   if ((bytes - i) % 4 == 2)
     {
-      md_number_to_chars (buf + i, RVC_NOP, 2);
+      number_to_chars_littleendian (buf + i, RVC_NOP, 2);
       i += 2;
     }
 
   /* Fill the remainder with 4-byte NOPs.  */
   for ( ; i < bytes; i += 4)
-    md_number_to_chars (buf + i, RISCV_NOP, 4);
+    number_to_chars_littleendian (buf + i, RISCV_NOP, 4);
 }
 
 /* Called from md_do_align.  Used to create an alignment frag in a
-- 
2.26.2

[PATCH v3 8/8] RISC-V: Fix testsuite failures

[Marcus Comstedt]

gas/
	* testsuite/gas/riscv/li32.d: Accept bigriscv in addition
	to littleriscv.
	* testsuite/gas/riscv/li64.d: Likewise.
	* testsuite/gas/riscv/lla32.d: Likewise.
	* testsuite/gas/riscv/lla64.d: Likewise.
	* testsuite/gas/riscv/march-ok-g2.d: Likewise.
	* testsuite/gas/riscv/march-ok-g2_p1.d: Likewise.
	* testsuite/gas/riscv/march-ok-g2p0.d: Likewise.
	* testsuite/gas/riscv/march-ok-i2p0.d: Likewise.
	* testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise.
	* testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise.
	* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.

ld/
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: (riscv_choose_ilp32_emul),
	(riscv_choose_lp64_emul): Add them.
	Call riscv_choose_ilp32_emul and riscv_choose_lp64_emul instead
	of hardcoding elf32lriscv and elf64lriscv.
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call
	riscv_choose_ilp32_emul instead of hardcoding elf32lriscv.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise.
	* testsuite/ld-riscv-elf/c-lui-2.d: Likewise.
	* testsuite/ld-riscv-elf/c-lui.d: Likewise.
	* testsuite/ld-riscv-elf/call-relax.d: Likewise.
	* testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise.
	* testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise.
	* testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition
	to littleriscv.
	* testsuite/ld-riscv-elf/weakref64.d: Likewise.
	* testsuite/ld-scripts/empty-address-2a.d: xfail riscv64be.
	* testsuite/ld-scripts/empty-address-2b.d: Likewise.
---
 gas/testsuite/gas/riscv/li32.d                |  2 +-
 gas/testsuite/gas/riscv/li64.d                |  2 +-
 gas/testsuite/gas/riscv/lla32.d               |  2 +-
 gas/testsuite/gas/riscv/lla64.d               |  2 +-
 gas/testsuite/gas/riscv/march-ok-g2.d         |  2 +-
 gas/testsuite/gas/riscv/march-ok-g2_p1.d      |  2 +-
 gas/testsuite/gas/riscv/march-ok-g2p0.d       |  2 +-
 gas/testsuite/gas/riscv/march-ok-i2p0.d       |  2 +-
 .../gas/riscv/march-ok-i2p0m2_a2f2.d          |  2 +-
 .../gas/riscv/march-ok-nse-with-version.d     |  2 +-
 gas/testsuite/gas/riscv/march-ok-two-nse.d    |  2 +-
 .../ld-riscv-elf/attr-merge-arch-01.d         |  2 +-
 .../ld-riscv-elf/attr-merge-arch-02.d         |  2 +-
 .../ld-riscv-elf/attr-merge-arch-03.d         |  2 +-
 .../ld-riscv-elf/attr-merge-arch-failed-01.d  |  2 +-
 .../ld-riscv-elf/attr-merge-arch-failed-02.d  |  2 +-
 ld/testsuite/ld-riscv-elf/c-lui-2.d           |  2 +-
 ld/testsuite/ld-riscv-elf/c-lui.d             |  2 +-
 ld/testsuite/ld-riscv-elf/call-relax.d        |  2 +-
 ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp    | 39 +++++++++++++------
 ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d |  2 +-
 ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d   |  2 +-
 ld/testsuite/ld-riscv-elf/weakref32.d         |  2 +-
 ld/testsuite/ld-riscv-elf/weakref64.d         |  2 +-
 ld/testsuite/ld-scripts/empty-address-2a.d    |  2 +-
 ld/testsuite/ld-scripts/empty-address-2b.d    |  2 +-
 26 files changed, 53 insertions(+), 36 deletions(-)

diff --git a/gas/testsuite/gas/riscv/li32.d b/gas/testsuite/gas/riscv/li32.d
index ff0827dde9..947ea4f754 100644
--- a/gas/testsuite/gas/riscv/li32.d
+++ b/gas/testsuite/gas/riscv/li32.d
@@ -1,7 +1,7 @@
 #as: -march=rv32ic -mabi=ilp32
 #objdump: -dr
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv
 
 
 Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/li64.d b/gas/testsuite/gas/riscv/li64.d
index 54213031cc..498b2e513d 100644
--- a/gas/testsuite/gas/riscv/li64.d
+++ b/gas/testsuite/gas/riscv/li64.d
@@ -1,7 +1,7 @@
 #as: -march=rv64ic -mabi=lp64
 #objdump: -dr
 
-.*:     file format elf64-littleriscv
+.*:     file format elf64-(little|big)riscv
 
 
 Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/lla32.d b/gas/testsuite/gas/riscv/lla32.d
index ab766b4e3b..9d87562906 100644
--- a/gas/testsuite/gas/riscv/lla32.d
+++ b/gas/testsuite/gas/riscv/lla32.d
@@ -1,7 +1,7 @@
 #as: -march=rv32i -mabi=ilp32
 #objdump: -dr
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv
 
 
 Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/lla64.d b/gas/testsuite/gas/riscv/lla64.d
index 7848eecdfb..c3b9581862 100644
--- a/gas/testsuite/gas/riscv/lla64.d
+++ b/gas/testsuite/gas/riscv/lla64.d
@@ -1,7 +1,7 @@
 #as: -march=rv64i -mabi=lp64
 #objdump: -dr
 
-.*:     file format elf64-littleriscv
+.*:     file format elf64-(little|big)riscv
 
 
 Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/march-ok-g2.d b/gas/testsuite/gas/riscv/march-ok-g2.d
index 38541ad6a6..7c92bc8bcb 100644
--- a/gas/testsuite/gas/riscv/march-ok-g2.d
+++ b/gas/testsuite/gas/riscv/march-ok-g2.d
@@ -2,4 +2,4 @@
 #objdump: -dr
 #source: empty.s
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv
diff --git a/gas/testsuite/gas/riscv/march-ok-g2_p1.d b/gas/testsuite/gas/riscv/march-ok-g2_p1.d
index cd9e127e66..da2247c9d9 100644
--- a/gas/testsuite/gas/riscv/march-ok-g2_p1.d
+++ b/gas/testsuite/gas/riscv/march-ok-g2_p1.d
@@ -2,4 +2,4 @@
 #objdump: -dr
 #source: empty.s
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv
diff --git a/gas/testsuite/gas/riscv/march-ok-g2p0.d b/gas/testsuite/gas/riscv/march-ok-g2p0.d
index b439314ccf..a11d55e499 100644
--- a/gas/testsuite/gas/riscv/march-ok-g2p0.d
+++ b/gas/testsuite/gas/riscv/march-ok-g2p0.d
@@ -2,4 +2,4 @@
 #objdump: -dr
 #source: empty.s
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv
diff --git a/gas/testsuite/gas/riscv/march-ok-i2p0.d b/gas/testsuite/gas/riscv/march-ok-i2p0.d
index eb8309c7e2..e413e09f88 100644
--- a/gas/testsuite/gas/riscv/march-ok-i2p0.d
+++ b/gas/testsuite/gas/riscv/march-ok-i2p0.d
@@ -2,4 +2,4 @@
 #objdump: -dr
 #source: empty.s
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv
diff --git a/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d b/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d
index 6658417b0f..11960ba5bf 100644
--- a/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d
+++ b/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d
@@ -2,4 +2,4 @@
 #objdump: -dr
 #source: empty.s
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv
diff --git a/gas/testsuite/gas/riscv/march-ok-nse-with-version.d b/gas/testsuite/gas/riscv/march-ok-nse-with-version.d
index bdca7fb18d..8e2110cef4 100644
--- a/gas/testsuite/gas/riscv/march-ok-nse-with-version.d
+++ b/gas/testsuite/gas/riscv/march-ok-nse-with-version.d
@@ -2,4 +2,4 @@
 #objdump: -dr
 #source: empty.s
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv
diff --git a/gas/testsuite/gas/riscv/march-ok-two-nse.d b/gas/testsuite/gas/riscv/march-ok-two-nse.d
index e78cf9dd09..8cdf316f04 100644
--- a/gas/testsuite/gas/riscv/march-ok-two-nse.d
+++ b/gas/testsuite/gas/riscv/march-ok-two-nse.d
@@ -2,4 +2,4 @@
 #objdump: -dr
 #source: empty.s
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
index 5baaba4c16..c148cdbc4f 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
@@ -1,7 +1,7 @@
 #source: attr-merge-arch-01a.s
 #source: attr-merge-arch-01b.s
 #as:
-#ld: -r -melf32lriscv
+#ld: -r -m[riscv_choose_ilp32_emul]
 #readelf: -A
 
 Attribute Section: riscv
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
index a7d79a1ea2..bc0e0fd138 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
@@ -1,7 +1,7 @@
 #source: attr-merge-arch-02a.s
 #source: attr-merge-arch-02b.s
 #as:
-#ld: -r -melf32lriscv
+#ld: -r -m[riscv_choose_ilp32_emul]
 #readelf: -A
 
 Attribute Section: riscv
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
index d46dee808d..374a043c69 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
@@ -1,7 +1,7 @@
 #source: attr-merge-arch-03a.s
 #source: attr-merge-arch-03b.s
 #as:
-#ld: -r -melf32lriscv
+#ld: -r -m[riscv_choose_ilp32_emul]
 #readelf: -A
 
 Attribute Section: riscv
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d
index 4b312388f7..669a139206 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d
@@ -1,7 +1,7 @@
 #source: attr-merge-arch-failed-01a.s
 #source: attr-merge-arch-failed-01b.s
 #as: -march-attr
-#ld: -r -melf32lriscv
+#ld: -r -m[riscv_choose_ilp32_emul]
 #warning: .*mis-matched ISA version 3.0 for 'a' extension, the output version is 2.0
 #readelf: -A
 
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
index 880ee15473..3f4935df54 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
@@ -3,7 +3,7 @@
 #source: attr-merge-arch-failed-02c.s
 #source: attr-merge-arch-failed-02d.s
 #as: -march-attr
-#ld: -r -melf32lriscv
+#ld: -r -m[riscv_choose_ilp32_emul]
 #warning: .*mis-matched ISA version 3.0 for 'i' extension, the output version is 2.0
 #warning: .*mis-matched ISA version 3.0 for 'm' extension, the output version is 2.0
 #warning: .*mis-matched ISA version 3.0 for 'a' extension, the output version is 2.0
diff --git a/ld/testsuite/ld-riscv-elf/c-lui-2.d b/ld/testsuite/ld-riscv-elf/c-lui-2.d
index 622c0f7a31..d363da10c3 100644
--- a/ld/testsuite/ld-riscv-elf/c-lui-2.d
+++ b/ld/testsuite/ld-riscv-elf/c-lui-2.d
@@ -1,7 +1,7 @@
 #name: c.lui to c.li relaxation
 #source: c-lui-2.s
 #as: -march=rv32ic
-#ld: -melf32lriscv -Tc-lui-2.ld
+#ld: -m[riscv_choose_ilp32_emul] -Tc-lui-2.ld
 #objdump: -d -M no-aliases,numeric
 
 .*:     file format .*
diff --git a/ld/testsuite/ld-riscv-elf/c-lui.d b/ld/testsuite/ld-riscv-elf/c-lui.d
index 382eca88dc..f1cf0b42c3 100644
--- a/ld/testsuite/ld-riscv-elf/c-lui.d
+++ b/ld/testsuite/ld-riscv-elf/c-lui.d
@@ -1,7 +1,7 @@
 #name: lui to c.lui relaxation
 #source: c-lui.s
 #as: -march=rv32ic
-#ld: -melf32lriscv
+#ld: -m[riscv_choose_ilp32_emul]
 #objdump: -d -M no-aliases,numeric
 
 .*:     file format .*
diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d
index 597ff67535..c6022bec26 100644
--- a/ld/testsuite/ld-riscv-elf/call-relax.d
+++ b/ld/testsuite/ld-riscv-elf/call-relax.d
@@ -4,6 +4,6 @@
 #source: call-relax-2.s
 #source: call-relax-3.s
 #as: -march=rv32ic -mno-arch-attr
-#ld: -melf32lriscv
+#ld: -m[riscv_choose_ilp32_emul]
 #objdump: -d
 #pass
diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index 86910e60ec..cb7c2ab9fb 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -19,6 +19,24 @@
 # MA 02110-1301, USA.
 #
 
+proc riscv_choose_ilp32_emul {} {
+    if { [istarget "riscvbe-*"] \
+	 || [istarget "riscv32be-*"] \
+	 || [istarget "riscv64be-*"] } {
+        return "elf32briscv"
+    }
+    return "elf32lriscv"
+}
+
+proc riscv_choose_lp64_emul {} {
+    if { [istarget "riscvbe-*"] \
+	 || [istarget "riscv32be-*"] \
+	 || [istarget "riscv64be-*"] } {
+        return "elf64briscv"
+    }
+    return "elf64lriscv"
+}
+
 # target: rv32 or rv64.
 # output: Which output you want?  (exe, pie, .so)
 proc run_dump_test_ifunc { name target output} {
@@ -42,11 +60,11 @@ proc run_dump_test_ifunc { name target output} {
     switch -- $target {
 	rv32 {
 	    set asflags "$asflags -march=rv32i -mabi=ilp32"
-	    set ldflags "$ldflags -melf32lriscv"
+	    set ldflags "$ldflags -m[riscv_choose_ilp32_emul]"
 	}
 	rv64 {
 	    set asflags "$asflags -march=rv64i -mabi=lp64 -defsym __64_bit__=1"
-	    set ldflags "$ldflags -melf64lriscv"
+	    set ldflags "$ldflags -m[riscv_choose_lp64_emul]"
 	}
     }
 
@@ -89,21 +107,20 @@ if [istarget "riscv*-*-*"] {
     run_dump_test "attr-merge-priv-spec-failed-04"
     run_dump_test "attr-merge-priv-spec-failed-05"
     run_dump_test "attr-merge-priv-spec-failed-06"
-    run_ld_link_tests {
-	{ "Weak reference 32" "-T weakref.ld -melf32lriscv" ""
-	    "-march=rv32i -mabi=ilp32" {weakref32.s}
-	    {{objdump -d weakref32.d}} "weakref32"}
-	{ "Weak reference 64" "-T weakref.ld -melf64lriscv" ""
-	    "-march=rv64i -mabi=lp64" {weakref64.s}
-	    {{objdump -d weakref64.d}} "weakref64"}
-    }
+    run_ld_link_tests [list \
+	[list "Weak reference 32" "-T weakref.ld -m[riscv_choose_ilp32_emul]" "" \
+	    "-march=rv32i -mabi=ilp32" {weakref32.s} \
+	    {{objdump -d weakref32.d}} "weakref32"] \
+	[list "Weak reference 64" "-T weakref.ld -m[riscv_choose_lp64_emul]" "" \
+	    "-march=rv64i -mabi=lp64" {weakref64.s} \
+	    {{objdump -d weakref64.d}} "weakref64"]]
 
     # The following tests require shared library support.
     if ![check_shared_lib_support] {
 	return
     }
 
-    set abis { rv32gc ilp32 elf32lriscv rv64gc lp64 elf64lriscv }
+    set abis { rv32gc ilp32 [riscv_choose_ilp32_emul] rv64gc lp64 [riscv_choose_lp64_emul] }
     foreach { arch abi emul } $abis {
 	# This checks whether our linker scripts handle __global_pointer$
 	# correctly.  It should be defined in executables and PIE, but not
diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d
index 039de102c3..895c6cc581 100644
--- a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d
+++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d
@@ -1,5 +1,5 @@
 #name: %pcrel_lo overflow with an addend
 #source: pcrel-lo-addend-2.s
 #as: -march=rv32ic
-#ld: -melf32lriscv --no-relax
+#ld: -m[riscv_choose_ilp32_emul] --no-relax
 #error: .*dangerous relocation: %pcrel_lo overflow with an addend
diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d
index ad658be844..92d41528a4 100644
--- a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d
+++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d
@@ -1,5 +1,5 @@
 #name: %pcrel_lo section symbol with an addend
 #source: pcrel-lo-addend.s
 #as: -march=rv32ic
-#ld: -melf32lriscv
+#ld: -m[riscv_choose_ilp32_emul]
 #error: .*dangerous relocation: %pcrel_lo section symbol with an addend
diff --git a/ld/testsuite/ld-riscv-elf/weakref32.d b/ld/testsuite/ld-riscv-elf/weakref32.d
index eaeb6dae7e..279481d223 100644
--- a/ld/testsuite/ld-riscv-elf/weakref32.d
+++ b/ld/testsuite/ld-riscv-elf/weakref32.d
@@ -1,5 +1,5 @@
 
-.*:     file format elf32-littleriscv
+.*:     file format elf32-(little|big)riscv
 
 
 Disassembly of section \.text:
diff --git a/ld/testsuite/ld-riscv-elf/weakref64.d b/ld/testsuite/ld-riscv-elf/weakref64.d
index cc718a91a3..c8f4c10339 100644
--- a/ld/testsuite/ld-riscv-elf/weakref64.d
+++ b/ld/testsuite/ld-riscv-elf/weakref64.d
@@ -1,5 +1,5 @@
 
-.*:     file format elf64-littleriscv
+.*:     file format elf64-(little|big)riscv
 
 
 Disassembly of section \.text:
diff --git a/ld/testsuite/ld-scripts/empty-address-2a.d b/ld/testsuite/ld-scripts/empty-address-2a.d
index 3b5a2d68f7..2619c48fc1 100644
--- a/ld/testsuite/ld-scripts/empty-address-2a.d
+++ b/ld/testsuite/ld-scripts/empty-address-2a.d
@@ -1,7 +1,7 @@
 #source: empty-address-2.s
 #ld: -Ttext 0x0000000 -Tdata 0x200 -T empty-address-2a.t
 #nm: -n
-#xfail: frv-*-*linux* riscv64-*-* tic54x-*-*
+#xfail: frv-*-*linux* riscv64-*-* riscv64be-*-* tic54x-*-*
 #...
 0+0 T _start
 #...
diff --git a/ld/testsuite/ld-scripts/empty-address-2b.d b/ld/testsuite/ld-scripts/empty-address-2b.d
index 3b530c94d8..ebe8461bb3 100644
--- a/ld/testsuite/ld-scripts/empty-address-2b.d
+++ b/ld/testsuite/ld-scripts/empty-address-2b.d
@@ -1,7 +1,7 @@
 #source: empty-address-2.s
 #ld: -Ttext 0x0000000 -Tdata 0x200 -T empty-address-2b.t
 #nm: -n
-#xfail: frv-*-*linux* riscv64-*-* tic54x-*-*
+#xfail: frv-*-*linux* riscv64-*-* riscv64be-*-* tic54x-*-*
 #...
 0+0 T _start
 #...
-- 
2.26.2

Re: [PATCH v3 0/8] RISC-V: Implement support for big endian targets

[Nelson Chu]

On Sun, Dec 27, 2020 at 10:53 PM Marcus Comstedt <marcus@mc.pp.se> wrote:
>
>
> This is an updated patch series for big endian RISC-V support.
> Changes since v2:
>
>  * gas now defaults to big endian when the triplet is riscvNNbe*-*-*.
>
>  * TARGET_BYTES_BIG_ENDIAN is now defined by tc-risc.h only if it is
>    not already defined by config.h.
>
>  * Modified riscv_is_insn_reloc to never shift a 64-bit value 64 bits,
>    as this is undefined behaviour in ISO C.
>
>  * Fixed byteorder of alignment nop:s.
>  * Updated the gas and ld testsuites to handle big endian
>
> All gas and ld testsuite fails are fixed.  What remains is

Thanks for updating these.  I get the gp-test fail with your eighth
patch, but they can be fixed by following minor changes,

diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index cb7c2ab..eda42d8 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -120,7 +120,7 @@ if [istarget "riscv*-*-*"] {
        return
     }

-    set abis { rv32gc ilp32 [riscv_choose_ilp32_emul] rv64gc lp64
[riscv_choose_lp64_emul] }
+    set abis { rv32gc ilp32 riscv_choose_ilp32_emul rv64gc lp64
riscv_choose_lp64_emul }
     foreach { arch abi emul } $abis {
        # This checks whether our linker scripts handle __global_pointer$
        # correctly.  It should be defined in executables and PIE, but not
@@ -128,13 +128,13 @@ if [istarget "riscv*-*-*"] {
        set suff64 [string map {ilp32 "" lp64 -64} $abi]
        run_ld_link_tests [list \
                               [list "gp test ($abi shared library)" \
-                                   "-m$emul -shared" "" \
+                                   "-m [$emul] -shared" ""\
                                    "-march=$arch -mabi=$abi -fpic" \
                                    { gp-test.s } \
                                    [list "readelf --syms gp-test-lib.sd"] \
                                    "gp-test-lib-${abi}.so"] \
                               [list "gp test ($abi executable)" \
-                                   "-m$emul" "" \
+                                   "-m [$emul]" "" \
                                    "-march=$arch -mabi=$abi" \
                                    { gp-test.s } \
                                    [list "readelf --syms gp-test.sd"] \

With the above minor changes, I can pass the gcc and binutils
riscv-gnu-toolchain/regressions for little-endian toolchains, so the
series of patches are fine to me for now.  Other stuff can be delayed
until you send the gcc patches in the future.

>   XPASS: ld-elf/compressed1d
>
> which might be unrelated (I haven't checked if it also XPASSes for
> little endian).

We will choose the uncompressed .debug_aranges since the sizes of
compressed and uncompressed are the same in this case
(273a49858fa9c8d73de87167618ef99d70f9731a).  I think the RISC-V
big-endian patches won't break the compress rules, just break the
compressed1d testcase by accident.  Jim already had written an
alternative test compressed1d-alt, so it is accepted to me that we add
the compressed1d to the riscv-gnu-toolcahin/test/allowlist/, and
always check the compressed1d-alt.d instead of it.


As I mentioned above, if these patches won't break the current
little-endian toolchains, and can pass at least the binutils testcases
(big-endian binutils without compiler support), then they are OK to me
at this stage.  However, they look good so far.  Other issues can be
fixed/discussed in the future patches, if you have sent the gcc/gdb
patches.

Thank you very much
Nelson

Re: [PATCH v3 0/8] RISC-V: Implement support for big endian targets

[Marcus Comstedt]

Hi Nelson.

Nelson Chu <nelson.chu@sifive.com> writes:

> -    set abis { rv32gc ilp32 [riscv_choose_ilp32_emul] rv64gc lp64
> [riscv_choose_lp64_emul] }
> +    set abis { rv32gc ilp32 riscv_choose_ilp32_emul rv64gc lp64
> riscv_choose_lp64_emul }
>      foreach { arch abi emul } $abis {
[...]
>                                [list "gp test ($abi shared library)" \
> -                                   "-m$emul -shared" "" \
> +                                   "-m [$emul] -shared" ""\
>                                     "-march=$arch -mabi=$abi -fpic" \

Ok.  What was the issue with the original version?  (It worked for me,
although I only tested riscv64be.)  Is the "istarget" command
dependent on upvars set by run_ld_link_tests?

Thanks


  // Marcus

Re: [PATCH v3 0/8] RISC-V: Implement support for big endian targets

[Marcus Comstedt]

Marcus Comstedt <marcus@mc.pp.se> writes:

> Ok.  What was the issue with the original version?

Ah, I see the problem now.  [] will of course not expand inside {}.
Does this fix work for you?

diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index cb7c2ab9fb..6ddc37a737 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -120,7 +120,7 @@ if [istarget "riscv*-*-*"] {
 	return
     }
 
-    set abis { rv32gc ilp32 [riscv_choose_ilp32_emul] rv64gc lp64 [riscv_choose_lp64_emul] }
+    set abis [list rv32gc ilp32 [riscv_choose_ilp32_emul] rv64gc lp64 [riscv_choose_lp64_emul]]
     foreach { arch abi emul } $abis {
 	# This checks whether our linker scripts handle __global_pointer$
 	# correctly.  It should be defined in executables and PIE, but not



  // Marcus

Re: [PATCH v3 6/8] RISC-V: Mention -mbig-endian and -mlittle-endian in doc

[Jim Wilson]

On Sun, Dec 27, 2020 at 6:54 AM Marcus Comstedt <marcus@mc.pp.se> wrote:

> +   [@b{-mlittle}|@b{-mlittle-endian}|@b{-mbig}|@b{-mbig-endian}]
>

This is documenting 4 new options, but the part 1 patch only adds two new
options, -mlittle-endian and -mbig-endian.  So I think we should not be
documenting the -mbig and -mlittle options as they don't exist.

Jim

Re: [PATCH v3 6/8] RISC-V: Mention -mbig-endian and -mlittle-endian in doc

[Marcus Comstedt]

Jim Wilson <jimw@sifive.com> writes:

> On Sun, Dec 27, 2020 at 6:54 AM Marcus Comstedt <marcus@mc.pp.se> wrote:
>
>> +   [@b{-mlittle}|@b{-mlittle-endian}|@b{-mbig}|@b{-mbig-endian}]
>>
>
> This is documenting 4 new options, but the part 1 patch only adds two new
> options, -mlittle-endian and -mbig-endian.  So I think we should not be
> documenting the -mbig and -mlittle options as they don't exist.

Well, the shorter options do exist in the sense that the longer ones
can be abbreviated.  Documenting the abbreviations would function as
a contract that no options will be added that conflict with the
shorter form.  (But -mb and -ml, while also working, are not
documented, so e.g. -mlong-double could be added without problem.)
If you do not agree, I'll remove the documentation of the
abbreviations.

PPC also documents both -mlittle and -mlittle-endian, although the
option parsing is implemented differently there.


  // Marcus

Re: [PATCH v3 6/8] RISC-V: Mention -mbig-endian and -mlittle-endian in doc

[Jim Wilson]

On Tue, Jan 5, 2021 at 12:02 AM Marcus Comstedt <marcus@mc.pp.se> wrote

> Well, the shorter options do exist in the sense that the longer ones
> can be abbreviated.  Documenting the abbreviations would function as
>

Having two options complicates multilib support, since now anyone who uses
the other option gets the wrong result unless we have MULTILIB_REUSE
definitions to map the one option to the other.  We already have way too
many arch variations to easily manage.  We should not make this worse by
adding option aliases.  I would prefer that we just have one documented
option name for each feature.

I looked at PPC.  In gcc they are using MULTILIB_MATCHES to handle the
multiple endian option names.  The RISC-V multilib-generator doesn't
support MULTILIB_MATCHES currently.  If we wanted to use that, we would
have to extend multilib-generator, and then verify that everything still
works, which isn't a given, considering how complicated the RISC-V
multilibs are.  We have already run into bugs in the gcc multilib support
trying to keep this working.  There would be some risk here, and some
delay, if we were forced to add MULTILIB_MATCHES support to the RISC-V
toolchain.

Also if you look in gcc you will see that the PPC port in the
rs6000/sysv4.opt file has to support both -mlittle-endian and -mlittle as
separate options as the compiler doesn't accept abbreviations like the
assembler does.  And the assembler actually supports a third option -le
which the compiler doesn't support.  I'd say this is a poor example of how
to do big/little endian support in the toolchain.

Jim

Re: [PATCH v3 6/8] RISC-V: Mention -mbig-endian and -mlittle-endian in doc

[Jim Wilson]

On Tue, Jan 5, 2021 at 10:12 AM Jim Wilson <jimw@sifive.com> wrote:

> On Tue, Jan 5, 2021 at 12:02 AM Marcus Comstedt <marcus@mc.pp.se> wrote
>
>> Well, the shorter options do exist in the sense that the longer ones
>> can be abbreviated.  Documenting the abbreviations would function as
>
>
I'd like to add that I think getting the patch in is more important about
debating the option docs.  We can always fix the option docs later.  The
sooner the patch get in, the more time I have to do testing.

Jim

Re: [PATCH v3 6/8] RISC-V: Mention -mbig-endian and -mlittle-endian in doc

[Marcus Comstedt]

Jim Wilson <jimw@sifive.com> writes:

> I looked at PPC.  In gcc they are using MULTILIB_MATCHES to handle the
> multiple endian option names.  The RISC-V multilib-generator doesn't
> support MULTILIB_MATCHES currently.  If we wanted to use that, we would
> have to extend multilib-generator, [...]

Ok, fair enough.  I'll remove the documentation for the
abbreviations.  (They can still be used of course, as any option
defined in md_longopts can be abbreviated as long as the abbreviation
is unambiguous.)


  // Marcus