* [integration 3/4] RISC-V/rvv: Changed assembler mnemonic for unordered floating-point reductions.
2021-06-21 6:26 [integration 0/4] RISC-V/rvv: Update rvv from v01.0 to v1.0 except zve feature Nelson Chu
2021-06-21 6:27 ` [integration 1/4] RISC-V/rvv: Added assembly pseudoinstructions, vfabs.v Nelson Chu
2021-06-21 6:27 ` [integration 2/4] RISC-V/rvv: Changed assembler mnemonic for mask loads/stores Nelson Chu
@ 2021-06-21 6:27 ` Nelson Chu
2021-06-21 6:27 ` [integration 4/4] RISC-V/rvv: Removed Zvamo from standard v, and then changed version to 1.0 Nelson Chu
3 siblings, 0 replies; 5+ messages in thread
From: Nelson Chu @ 2021-06-21 6:27 UTC (permalink / raw)
To: binutils, jimw, andrew, palmer, nelson.chu
Changed from vfredsum and vfwredsum to vfredusum and vfwredusum respectively.
Older names kept as aliases.
gas/
* testsuite/gas/riscv/extended/vector-insns.d: Updated.
* testsuite/gas/riscv/extended/vector-insns.s: Likewise.
include/
* opcode/riscv-opc-extended.h: Updated.
opcodes/
* riscv-opc.c (riscv_draft_opcodes): Added vfredusum.vs and vfwredusum.vs.
Marked the old vfredusum.vs and vfwredsum.vs as their aliases.
---
gas/testsuite/gas/riscv/extended/vector-insns.d | 12 ++++++++----
gas/testsuite/gas/riscv/extended/vector-insns.s | 12 ++++++++----
include/opcode/riscv-opc-extended.h | 8 ++++----
opcodes/riscv-opc.c | 6 ++++--
4 files changed, 24 insertions(+), 14 deletions(-)
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.d b/gas/testsuite/gas/riscv/extended/vector-insns.d
index 6d77f936291..c8c01c9d49d 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns.d
+++ b/gas/testsuite/gas/riscv/extended/vector-insns.d
@@ -1869,17 +1869,21 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+c0860257[ ]+vwredsumu.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+c4860257[ ]+vwredsum.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+0e861257[ ]+vfredosum.vs[ ]+v4,v8,v12
-[ ]+[0-9a-f]+:[ ]+06861257[ ]+vfredsum.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+06861257[ ]+vfredusum.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+06861257[ ]+vfredusum.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+1e861257[ ]+vfredmax.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+16861257[ ]+vfredmin.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+0c861257[ ]+vfredosum.vs[ ]+v4,v8,v12,v0.t
-[ ]+[0-9a-f]+:[ ]+04861257[ ]+vfredsum.vs[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+04861257[ ]+vfredusum.vs[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+04861257[ ]+vfredusum.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+1c861257[ ]+vfredmax.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+14861257[ ]+vfredmin.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+ce861257[ ]+vfwredosum.vs[ ]+v4,v8,v12
-[ ]+[0-9a-f]+:[ ]+c6861257[ ]+vfwredsum.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+c6861257[ ]+vfwredusum.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+c6861257[ ]+vfwredusum.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+cc861257[ ]+vfwredosum.vs[ ]+v4,v8,v12,v0.t
-[ ]+[0-9a-f]+:[ ]+c4861257[ ]+vfwredsum.vs[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+c4861257[ ]+vfwredusum.vs[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+c4861257[ ]+vfwredusum.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+66842257[ ]+vmmv.m[ ]+v4,v8
[ ]+[0-9a-f]+:[ ]+66842257[ ]+vmmv.m[ ]+v4,v8
[ ]+[0-9a-f]+:[ ]+6e422257[ ]+vmclr.m[ ]+v4
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.s b/gas/testsuite/gas/riscv/extended/vector-insns.s
index 3e45b9d963b..bace7abbf01 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns.s
+++ b/gas/testsuite/gas/riscv/extended/vector-insns.s
@@ -2096,18 +2096,22 @@
vwredsum.vs v4, v8, v12, v0.t
vfredosum.vs v4, v8, v12
- vfredsum.vs v4, v8, v12
+ vfredusum.vs v4, v8, v12
+ vfredsum.vs v4, v8, v12 # Alias of vfredusum.vs.
vfredmax.vs v4, v8, v12
vfredmin.vs v4, v8, v12
vfredosum.vs v4, v8, v12, v0.t
- vfredsum.vs v4, v8, v12, v0.t
+ vfredusum.vs v4, v8, v12, v0.t
+ vfredsum.vs v4, v8, v12, v0.t # Alias of vfredusum.vs.
vfredmax.vs v4, v8, v12, v0.t
vfredmin.vs v4, v8, v12, v0.t
vfwredosum.vs v4, v8, v12
- vfwredsum.vs v4, v8, v12
+ vfwredusum.vs v4, v8, v12
+ vfwredsum.vs v4, v8, v12 # Alias of vfwredusum.vs.
vfwredosum.vs v4, v8, v12, v0.t
- vfwredsum.vs v4, v8, v12, v0.t
+ vfwredusum.vs v4, v8, v12, v0.t
+ vfwredsum.vs v4, v8, v12, v0.t # Alias of vfwredusum.vs.
# Aliases
vmcpy.m v4, v8
diff --git a/include/opcode/riscv-opc-extended.h b/include/opcode/riscv-opc-extended.h
index 9d509b318b2..907313a5a72 100644
--- a/include/opcode/riscv-opc-extended.h
+++ b/include/opcode/riscv-opc-extended.h
@@ -1359,16 +1359,16 @@
#define MASK_VWREDSUMVS 0xfc00707f
#define MATCH_VFREDOSUMVS 0x0c001057
#define MASK_VFREDOSUMVS 0xfc00707f
-#define MATCH_VFREDSUMVS 0x04001057
-#define MASK_VFREDSUMVS 0xfc00707f
+#define MATCH_VFREDUSUMVS 0x04001057
+#define MASK_VFREDUSUMVS 0xfc00707f
#define MATCH_VFREDMAXVS 0x1c001057
#define MASK_VFREDMAXVS 0xfc00707f
#define MATCH_VFREDMINVS 0x14001057
#define MASK_VFREDMINVS 0xfc00707f
#define MATCH_VFWREDOSUMVS 0xcc001057
#define MASK_VFWREDOSUMVS 0xfc00707f
-#define MATCH_VFWREDSUMVS 0xc4001057
-#define MASK_VFWREDSUMVS 0xfc00707f
+#define MATCH_VFWREDUSUMVS 0xc4001057
+#define MASK_VFWREDUSUMVS 0xfc00707f
#define MATCH_VMANDMM 0x66002057
#define MASK_VMANDMM 0xfe00707f
#define MATCH_VMNANDMM 0x76002057
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 98736072388..be5d49ee33e 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2153,12 +2153,14 @@ const struct riscv_opcode riscv_draft_opcodes[] =
{"vwredsum.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0},
{"vfredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0},
-{"vfredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDSUMVS, MASK_VFREDSUMVS, match_opcode, 0},
+{"vfredusum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDUSUMVS, MASK_VFREDUSUMVS, match_opcode, 0},
+{"vfredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDUSUMVS, MASK_VFREDUSUMVS, match_opcode, INSN_ALIAS},
{"vfredmax.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0},
{"vfredmin.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
{"vfwredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
-{"vfwredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDSUMVS, MASK_VFWREDSUMVS, match_opcode, 0},
+{"vfwredusum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, 0},
+{"vfwredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, INSN_ALIAS},
{"vmmv.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
{"vmcpy.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
--
2.30.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* [integration 4/4] RISC-V/rvv: Removed Zvamo from standard v, and then changed version to 1.0.
2021-06-21 6:26 [integration 0/4] RISC-V/rvv: Update rvv from v01.0 to v1.0 except zve feature Nelson Chu
` (2 preceding siblings ...)
2021-06-21 6:27 ` [integration 3/4] RISC-V/rvv: Changed assembler mnemonic for unordered floating-point reductions Nelson Chu
@ 2021-06-21 6:27 ` Nelson Chu
3 siblings, 0 replies; 5+ messages in thread
From: Nelson Chu @ 2021-06-21 6:27 UTC (permalink / raw)
To: binutils, jimw, andrew, palmer, nelson.chu
gas/
* config/tc-riscv.c (extended_ext_version_table): Changed versions to 1.0.
(riscv_extended_subset_supports): Changed INSN_CLASS_V_OR_ZVAMO to
INSN_CLASS_ZVAMO.
* testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d: Changed
-march from rv32iav to rv32ia_zvamo.
* testsuite/gas/riscv/extended/vector-insns.d: Changed -march from
rv32iafv to rv32iafv_zvamo.
include/
* opcode/riscv.h (riscv_extended_insn_class): Changed
INSN_CLASS_V_OR_ZVAMO to INSN_CLASS_ZVAMO.
opcodes/
* riscv-opc.c (riscv_draft_opcodes): Changed
INSN_CLASS_V_OR_ZVAMO to INSN_CLASS_ZVAMO.
---
gas/config/tc-riscv.c | 12 ++-
.../riscv/extended/vector-insns-fail-zvamo.d | 2 +-
.../gas/riscv/extended/vector-insns.d | 2 +-
include/opcode/riscv.h | 2 +-
opcodes/riscv-opc.c | 78 +++++++++----------
5 files changed, 47 insertions(+), 49 deletions(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 826d3fc1cc6..8389ec89287 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -164,9 +164,9 @@ static const struct riscv_ext_version ext_version_table[] =
/* Default versions for extended extensions. */
static const struct riscv_ext_version extended_ext_version_table[] =
{
- {"v", ISA_SPEC_CLASS_DRAFT, 0, 10},
- {"zvamo", ISA_SPEC_CLASS_DRAFT, 0, 10},
- {"zvlsseg", ISA_SPEC_CLASS_DRAFT, 0, 10},
+ {"v", ISA_SPEC_CLASS_DRAFT, 1, 0},
+ {"zvamo", ISA_SPEC_CLASS_DRAFT, 1, 0},
+ {"zvlsseg", ISA_SPEC_CLASS_DRAFT, 1, 0},
{"zfh", ISA_SPEC_CLASS_DRAFT, 0, 1},
/* Terminate the list. */
@@ -346,13 +346,11 @@ riscv_extended_subset_supports (int insn_class)
case INSN_CLASS_V: return riscv_subset_supports ("v");
case INSN_CLASS_V_AND_F:
return riscv_subset_supports ("v") && riscv_subset_supports ("f");
- case INSN_CLASS_V_OR_ZVAMO:
- return (riscv_subset_supports ("a")
- && (riscv_subset_supports ("v")
- || riscv_subset_supports ("zvamo")));
case INSN_CLASS_V_OR_ZVLSSEG:
return (riscv_subset_supports ("v")
|| riscv_subset_supports ("zvlsseg"));
+ case INSN_CLASS_ZVAMO:
+ return riscv_subset_supports ("a") && riscv_subset_supports ("zvamo");
case INSN_CLASS_ZFH:
return riscv_subset_supports ("zfh");
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d
index 5749449bd03..8a6de14600c 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d
@@ -1,3 +1,3 @@
-#as: -march=rv32iav -mcheck-constraints
+#as: -march=rv32ia_zvamo -mcheck-constraints
#source: vector-insns-fail-zvamo.s
#error_output: vector-insns-fail-zvamo.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.d b/gas/testsuite/gas/riscv/extended/vector-insns.d
index c8c01c9d49d..2f231b6aaa8 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns.d
+++ b/gas/testsuite/gas/riscv/extended/vector-insns.d
@@ -1,4 +1,4 @@
-#as: -march=rv32iafv
+#as: -march=rv32iafv_zvamo
#objdump: -dr
.*:[ ]+file format .*
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 1f6051e1c09..dca5d59f878 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -490,8 +490,8 @@ enum riscv_extended_insn_class
/* Draft */
INSN_CLASS_V = INSN_CLASS_EXTENDED,
INSN_CLASS_V_AND_F,
- INSN_CLASS_V_OR_ZVAMO,
INSN_CLASS_V_OR_ZVLSSEG,
+ INSN_CLASS_ZVAMO,
INSN_CLASS_ZFH,
INSN_CLASS_D_AND_ZFH,
INSN_CLASS_Q_AND_ZFH,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index be5d49ee33e..049743cc43b 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1768,45 +1768,45 @@ const struct riscv_opcode riscv_draft_opcodes[] =
{"vs4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_vls_nf_rv, INSN_DREF },
{"vs8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_vls_nf_rv, INSN_DREF },
-{"vamoaddei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_vd_neq_vm, INSN_DREF},
-{"vamoswapei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_vd_neq_vm, INSN_DREF},
-{"vamoxorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_vd_neq_vm, INSN_DREF},
-{"vamoandei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_vd_neq_vm, INSN_DREF},
-{"vamoorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_vd_neq_vm, INSN_DREF},
-{"vamominei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_vd_neq_vm, INSN_DREF},
-{"vamominuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_vd_neq_vm, INSN_DREF},
-
-{"vamoaddei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_vd_neq_vm, INSN_DREF},
-{"vamoswapei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_vd_neq_vm, INSN_DREF},
-{"vamoxorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_vd_neq_vm, INSN_DREF},
-{"vamoandei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_vd_neq_vm, INSN_DREF},
-{"vamoorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_vd_neq_vm, INSN_DREF},
-{"vamominei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_vd_neq_vm, INSN_DREF},
-{"vamominuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_vd_neq_vm, INSN_DREF},
-
-{"vamoaddei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_vd_neq_vm, INSN_DREF},
-{"vamoswapei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_vd_neq_vm, INSN_DREF},
-{"vamoxorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_vd_neq_vm, INSN_DREF},
-{"vamoandei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_vd_neq_vm, INSN_DREF},
-{"vamoorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_vd_neq_vm, INSN_DREF},
-{"vamominei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_vd_neq_vm, INSN_DREF},
-{"vamominuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_vd_neq_vm, INSN_DREF},
-
-{"vamoaddei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_vd_neq_vm, INSN_DREF},
-{"vamoswapei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_vd_neq_vm, INSN_DREF},
-{"vamoxorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_vd_neq_vm, INSN_DREF},
-{"vamoandei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_vd_neq_vm, INSN_DREF},
-{"vamoorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_vd_neq_vm, INSN_DREF},
-{"vamominei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_vd_neq_vm, INSN_DREF},
-{"vamominuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_vd_neq_vm, INSN_DREF},
+{"vamoaddei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_vd_neq_vm, INSN_DREF},
+{"vamoswapei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_vd_neq_vm, INSN_DREF},
+{"vamoxorei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_vd_neq_vm, INSN_DREF},
+{"vamoandei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_vd_neq_vm, INSN_DREF},
+{"vamoorei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_vd_neq_vm, INSN_DREF},
+{"vamominei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_vd_neq_vm, INSN_DREF},
+{"vamominuei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxuei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_vd_neq_vm, INSN_DREF},
+
+{"vamoaddei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_vd_neq_vm, INSN_DREF},
+{"vamoswapei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_vd_neq_vm, INSN_DREF},
+{"vamoxorei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_vd_neq_vm, INSN_DREF},
+{"vamoandei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_vd_neq_vm, INSN_DREF},
+{"vamoorei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_vd_neq_vm, INSN_DREF},
+{"vamominei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_vd_neq_vm, INSN_DREF},
+{"vamominuei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxuei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_vd_neq_vm, INSN_DREF},
+
+{"vamoaddei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_vd_neq_vm, INSN_DREF},
+{"vamoswapei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_vd_neq_vm, INSN_DREF},
+{"vamoxorei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_vd_neq_vm, INSN_DREF},
+{"vamoandei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_vd_neq_vm, INSN_DREF},
+{"vamoorei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_vd_neq_vm, INSN_DREF},
+{"vamominei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_vd_neq_vm, INSN_DREF},
+{"vamominuei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxuei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_vd_neq_vm, INSN_DREF},
+
+{"vamoaddei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_vd_neq_vm, INSN_DREF},
+{"vamoswapei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_vd_neq_vm, INSN_DREF},
+{"vamoxorei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_vd_neq_vm, INSN_DREF},
+{"vamoandei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_vd_neq_vm, INSN_DREF},
+{"vamoorei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_vd_neq_vm, INSN_DREF},
+{"vamominei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_vd_neq_vm, INSN_DREF},
+{"vamominuei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxuei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_vd_neq_vm, INSN_DREF},
{"vneg.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_vd_neq_vm, INSN_ALIAS },
--
2.30.2
^ permalink raw reply [flat|nested] 5+ messages in thread