From: Nelson Chu <nelson.chu@sifive.com>
To: binutils@sourceware.org, jimw@sifive.com, andrew@sifive.com,
palmer@dabbelt.com, nelson.chu@sifive.com
Subject: [integration 4/4] RISC-V/rvv: Removed Zvamo from standard v, and then changed version to 1.0.
Date: Sun, 20 Jun 2021 23:27:03 -0700 [thread overview]
Message-ID: <20210621062703.8369-5-nelson.chu@sifive.com> (raw)
In-Reply-To: <20210621062703.8369-1-nelson.chu@sifive.com>
gas/
* config/tc-riscv.c (extended_ext_version_table): Changed versions to 1.0.
(riscv_extended_subset_supports): Changed INSN_CLASS_V_OR_ZVAMO to
INSN_CLASS_ZVAMO.
* testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d: Changed
-march from rv32iav to rv32ia_zvamo.
* testsuite/gas/riscv/extended/vector-insns.d: Changed -march from
rv32iafv to rv32iafv_zvamo.
include/
* opcode/riscv.h (riscv_extended_insn_class): Changed
INSN_CLASS_V_OR_ZVAMO to INSN_CLASS_ZVAMO.
opcodes/
* riscv-opc.c (riscv_draft_opcodes): Changed
INSN_CLASS_V_OR_ZVAMO to INSN_CLASS_ZVAMO.
---
gas/config/tc-riscv.c | 12 ++-
.../riscv/extended/vector-insns-fail-zvamo.d | 2 +-
.../gas/riscv/extended/vector-insns.d | 2 +-
include/opcode/riscv.h | 2 +-
opcodes/riscv-opc.c | 78 +++++++++----------
5 files changed, 47 insertions(+), 49 deletions(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 826d3fc1cc6..8389ec89287 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -164,9 +164,9 @@ static const struct riscv_ext_version ext_version_table[] =
/* Default versions for extended extensions. */
static const struct riscv_ext_version extended_ext_version_table[] =
{
- {"v", ISA_SPEC_CLASS_DRAFT, 0, 10},
- {"zvamo", ISA_SPEC_CLASS_DRAFT, 0, 10},
- {"zvlsseg", ISA_SPEC_CLASS_DRAFT, 0, 10},
+ {"v", ISA_SPEC_CLASS_DRAFT, 1, 0},
+ {"zvamo", ISA_SPEC_CLASS_DRAFT, 1, 0},
+ {"zvlsseg", ISA_SPEC_CLASS_DRAFT, 1, 0},
{"zfh", ISA_SPEC_CLASS_DRAFT, 0, 1},
/* Terminate the list. */
@@ -346,13 +346,11 @@ riscv_extended_subset_supports (int insn_class)
case INSN_CLASS_V: return riscv_subset_supports ("v");
case INSN_CLASS_V_AND_F:
return riscv_subset_supports ("v") && riscv_subset_supports ("f");
- case INSN_CLASS_V_OR_ZVAMO:
- return (riscv_subset_supports ("a")
- && (riscv_subset_supports ("v")
- || riscv_subset_supports ("zvamo")));
case INSN_CLASS_V_OR_ZVLSSEG:
return (riscv_subset_supports ("v")
|| riscv_subset_supports ("zvlsseg"));
+ case INSN_CLASS_ZVAMO:
+ return riscv_subset_supports ("a") && riscv_subset_supports ("zvamo");
case INSN_CLASS_ZFH:
return riscv_subset_supports ("zfh");
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d
index 5749449bd03..8a6de14600c 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d
@@ -1,3 +1,3 @@
-#as: -march=rv32iav -mcheck-constraints
+#as: -march=rv32ia_zvamo -mcheck-constraints
#source: vector-insns-fail-zvamo.s
#error_output: vector-insns-fail-zvamo.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.d b/gas/testsuite/gas/riscv/extended/vector-insns.d
index c8c01c9d49d..2f231b6aaa8 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns.d
+++ b/gas/testsuite/gas/riscv/extended/vector-insns.d
@@ -1,4 +1,4 @@
-#as: -march=rv32iafv
+#as: -march=rv32iafv_zvamo
#objdump: -dr
.*:[ ]+file format .*
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 1f6051e1c09..dca5d59f878 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -490,8 +490,8 @@ enum riscv_extended_insn_class
/* Draft */
INSN_CLASS_V = INSN_CLASS_EXTENDED,
INSN_CLASS_V_AND_F,
- INSN_CLASS_V_OR_ZVAMO,
INSN_CLASS_V_OR_ZVLSSEG,
+ INSN_CLASS_ZVAMO,
INSN_CLASS_ZFH,
INSN_CLASS_D_AND_ZFH,
INSN_CLASS_Q_AND_ZFH,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index be5d49ee33e..049743cc43b 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1768,45 +1768,45 @@ const struct riscv_opcode riscv_draft_opcodes[] =
{"vs4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_vls_nf_rv, INSN_DREF },
{"vs8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_vls_nf_rv, INSN_DREF },
-{"vamoaddei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_vd_neq_vm, INSN_DREF},
-{"vamoswapei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_vd_neq_vm, INSN_DREF},
-{"vamoxorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_vd_neq_vm, INSN_DREF},
-{"vamoandei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_vd_neq_vm, INSN_DREF},
-{"vamoorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_vd_neq_vm, INSN_DREF},
-{"vamominei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_vd_neq_vm, INSN_DREF},
-{"vamominuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_vd_neq_vm, INSN_DREF},
-
-{"vamoaddei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_vd_neq_vm, INSN_DREF},
-{"vamoswapei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_vd_neq_vm, INSN_DREF},
-{"vamoxorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_vd_neq_vm, INSN_DREF},
-{"vamoandei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_vd_neq_vm, INSN_DREF},
-{"vamoorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_vd_neq_vm, INSN_DREF},
-{"vamominei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_vd_neq_vm, INSN_DREF},
-{"vamominuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_vd_neq_vm, INSN_DREF},
-
-{"vamoaddei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_vd_neq_vm, INSN_DREF},
-{"vamoswapei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_vd_neq_vm, INSN_DREF},
-{"vamoxorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_vd_neq_vm, INSN_DREF},
-{"vamoandei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_vd_neq_vm, INSN_DREF},
-{"vamoorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_vd_neq_vm, INSN_DREF},
-{"vamominei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_vd_neq_vm, INSN_DREF},
-{"vamominuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_vd_neq_vm, INSN_DREF},
-
-{"vamoaddei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_vd_neq_vm, INSN_DREF},
-{"vamoswapei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_vd_neq_vm, INSN_DREF},
-{"vamoxorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_vd_neq_vm, INSN_DREF},
-{"vamoandei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_vd_neq_vm, INSN_DREF},
-{"vamoorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_vd_neq_vm, INSN_DREF},
-{"vamominei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_vd_neq_vm, INSN_DREF},
-{"vamominuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_vd_neq_vm, INSN_DREF},
-{"vamomaxuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_vd_neq_vm, INSN_DREF},
+{"vamoaddei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_vd_neq_vm, INSN_DREF},
+{"vamoswapei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_vd_neq_vm, INSN_DREF},
+{"vamoxorei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_vd_neq_vm, INSN_DREF},
+{"vamoandei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_vd_neq_vm, INSN_DREF},
+{"vamoorei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_vd_neq_vm, INSN_DREF},
+{"vamominei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_vd_neq_vm, INSN_DREF},
+{"vamominuei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxuei8.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_vd_neq_vm, INSN_DREF},
+
+{"vamoaddei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_vd_neq_vm, INSN_DREF},
+{"vamoswapei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_vd_neq_vm, INSN_DREF},
+{"vamoxorei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_vd_neq_vm, INSN_DREF},
+{"vamoandei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_vd_neq_vm, INSN_DREF},
+{"vamoorei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_vd_neq_vm, INSN_DREF},
+{"vamominei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_vd_neq_vm, INSN_DREF},
+{"vamominuei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxuei16.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_vd_neq_vm, INSN_DREF},
+
+{"vamoaddei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_vd_neq_vm, INSN_DREF},
+{"vamoswapei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_vd_neq_vm, INSN_DREF},
+{"vamoxorei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_vd_neq_vm, INSN_DREF},
+{"vamoandei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_vd_neq_vm, INSN_DREF},
+{"vamoorei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_vd_neq_vm, INSN_DREF},
+{"vamominei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_vd_neq_vm, INSN_DREF},
+{"vamominuei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxuei32.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_vd_neq_vm, INSN_DREF},
+
+{"vamoaddei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_vd_neq_vm, INSN_DREF},
+{"vamoswapei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_vd_neq_vm, INSN_DREF},
+{"vamoxorei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_vd_neq_vm, INSN_DREF},
+{"vamoandei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_vd_neq_vm, INSN_DREF},
+{"vamoorei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_vd_neq_vm, INSN_DREF},
+{"vamominei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_vd_neq_vm, INSN_DREF},
+{"vamominuei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_vd_neq_vm, INSN_DREF},
+{"vamomaxuei64.v", 0, INSN_CLASS_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_vd_neq_vm, INSN_DREF},
{"vneg.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_vd_neq_vm, INSN_ALIAS },
--
2.30.2
prev parent reply other threads:[~2021-06-21 6:27 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-21 6:26 [integration 0/4] RISC-V/rvv: Update rvv from v01.0 to v1.0 except zve feature Nelson Chu
2021-06-21 6:27 ` [integration 1/4] RISC-V/rvv: Added assembly pseudoinstructions, vfabs.v Nelson Chu
2021-06-21 6:27 ` [integration 2/4] RISC-V/rvv: Changed assembler mnemonic for mask loads/stores Nelson Chu
2021-06-21 6:27 ` [integration 3/4] RISC-V/rvv: Changed assembler mnemonic for unordered floating-point reductions Nelson Chu
2021-06-21 6:27 ` Nelson Chu [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210621062703.8369-5-nelson.chu@sifive.com \
--to=nelson.chu@sifive.com \
--cc=andrew@sifive.com \
--cc=binutils@sourceware.org \
--cc=jimw@sifive.com \
--cc=palmer@dabbelt.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).