From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by sourceware.org (Postfix) with ESMTPS id 7BA4A3AAB44F for ; Fri, 9 Jul 2021 07:28:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7BA4A3AAB44F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pf1-x42f.google.com with SMTP id a127so7951332pfa.10 for ; Fri, 09 Jul 2021 00:28:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FQTzkMBBOERvqt7zuiymhNNtwKR1oLFlh4w3p0l0oIg=; b=OAv01XteXZSBbpGdhpK0cYEZUCAlrbTFieF9FrIC2AMaMOFMU2usoSKjgzOUYCij0k 5CEb1XO0vozEwJKqub8XgREh37QhQXOtv2RrXfrrMn5EBIEQg9ZmO3vHBNnxUHxUTyo5 A4og+qcYk8KKrzxU1fbnC1MOlf38Tm/Ws3zy4kvIlN3NzUqeuLleSLBGeO0KnjNBalWc 2San/U+DiFc7Cl+1tqvLOvC/Ao211YnJ1+go2u3NsWATlMzyizEjYU/h8tJdTp873+Is YbT/TTxTVFPPwhPUdQa2ssaHnHlGLf3Heovo/6wwma9waDThiUCNGk8UoBilQdh61OoY 1+bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FQTzkMBBOERvqt7zuiymhNNtwKR1oLFlh4w3p0l0oIg=; b=W86K/JBKKPJCPR9EX4Io3n7rakSIQrVzYtvT2GVDO7vBXsM7Ld+r+4bfD91JG7ryJ5 ihn1LOlMdA3d6FZj1/yXKCu8BnyXnjEcV0PTk3WZjv0rOA3vfu84f6+3usH6Ok43c6B+ ibzp7ROKbfVAHRX/qIyYkxFXxPUlhH6DjbHKGAq3x/lthzAvK8eDLCECiNb4hZYqg+O5 Dh3JVELHzS2pBrLkADCWAGUNGOIWLDEF0DvJ0xbp76HMXlneY8bYqbBJrpFTGMbbMyrf 5yDohUoHHTN5bb7YylhX7sCZmS7sFwVH5MHsvUvV5jJ0Iu84quX54/MH0OX4K12rIkt+ I6IA== X-Gm-Message-State: AOAM532HAvC7DTtZC5+vzdwsdKI0nagTx47oSWPRfpUi3NtdgI0YJFFR 3djnBnvcp+Yoe0/TUdk0Tb/uGyq1TvAfAQEt X-Google-Smtp-Source: ABdhPJzfOjlTrY8v4JXvwwSAvj5BRh7g5sm8Fqz3rGApJSCGEAIDG7QaoiKkw3xtpiagMX8PCDLxEQ== X-Received: by 2002:aa7:943b:0:b029:321:809a:f0b with SMTP id y27-20020aa7943b0000b0290321809a0f0bmr22790092pfo.32.1625815712434; Fri, 09 Jul 2021 00:28:32 -0700 (PDT) Received: from gamma00.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id l2sm5130900pfc.157.2021.07.09.00.28.31 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Jul 2021 00:28:31 -0700 (PDT) From: Nelson Chu To: binutils@sourceware.org, gdb-patches@sourceware.org, jimw@sifive.com, andrew.burgess@embecosm.com, kito.cheng@sifive.com, palmer@dabbelt.com, andrew@sifive.com Subject: [PATCH v2 3/3] RISC-V: PR27916, Extend .insn directive to support hardcode encoding. Date: Fri, 9 Jul 2021 00:28:25 -0700 Message-Id: <20210709072825.13709-4-nelson.chu@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709072825.13709-1-nelson.chu@sifive.com> References: <20210709072825.13709-1-nelson.chu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=unavailable autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Jul 2021 07:28:36 -0000 The .insn directive can let users use their own instructions, or some new instruction, which haven't supported in the old binutils. For example, if users want to use sifive cache instruction, they cannot just write "cflush.d1.l1" in the assembly code, they should use ".insn i SYSTEM, 0, x0, x10, -0x40". But the .insn directive may not easy to use for some cases, and not so friendly to users. Therefore, I believe most of the users will use ".word 0xfc050073", to encode the instructions directly, rather than use .insn. But once we have supported the mapping symbols, the .word directives are marked as data, so disassembler won't dump them as instructions as usual. I have discussed this with Kito many times, we all think extend the .insn direcitve to support the hardcode encoding, is the easiest way to resolve the problem. Therefore, there are two more .insn formats are proposed as follows, (original) .insn , , , ... .insn , .insn The is string, and the and are constants. ChangeLog: gas/ pr 27916 * config/tc-riscv.c (riscv_ip_hardcode): Similar to riscv_ip, but assembles an instruction according to the hardcode values of .insn directive. * testsuite/gas/riscv/insn-fail.d: New testcases. * testsuite/gas/riscv/insn-fail.l: Likewise. * testsuite/gas/riscv/insn-fail.s: Likewise. * testsuite/gas/riscv/insn.d: Updated. * testsuite/gas/riscv/insn.s: Likewise. --- gas/config/tc-riscv.c | 57 +++++++++++++++++++++++++++-- gas/testsuite/gas/riscv/insn-fail.d | 3 ++ gas/testsuite/gas/riscv/insn-fail.l | 7 ++++ gas/testsuite/gas/riscv/insn-fail.s | 6 +++ gas/testsuite/gas/riscv/insn.d | 6 +++ gas/testsuite/gas/riscv/insn.s | 7 ++++ 6 files changed, 83 insertions(+), 3 deletions(-) create mode 100644 gas/testsuite/gas/riscv/insn-fail.d create mode 100644 gas/testsuite/gas/riscv/insn-fail.l create mode 100644 gas/testsuite/gas/riscv/insn-fail.s diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 55c49471825..e9be17f56d1 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2922,6 +2922,50 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, return error; } +/* Similar to riscv_ip, but assembles an instruction according to the + hardcode values of .insn directive. */ + +static const char * +riscv_ip_hardcode (char *str, + struct riscv_cl_insn *ip, + expressionS *imm_expr, + const char *error) +{ + struct riscv_opcode *insn; + insn_t values[2] = {0, 0}; + unsigned int num = 0; + + input_line_pointer = str; + do + { + expression (imm_expr); + if (imm_expr->X_op != O_constant) + { + /* The first value isn't constant, so it should be + .insn . Call riscv_ip to parse it. */ + if (num == 0) + return error; + return _("values must be constant"); + } + values[num++] = (insn_t) imm_expr->X_add_number; + } + while (*input_line_pointer++ == ',' && num < 2); + + input_line_pointer--; + if (*input_line_pointer != '\0') + return _("unrecognized values"); + + insn = XNEW (struct riscv_opcode); + insn->match = values[num - 1]; + create_insn (ip, insn); + unsigned int bytes = riscv_insn_length (insn->match); + if (values[num - 1] >> (8 * bytes) != 0 + || (num == 2 && values[0] != bytes)) + return _("value conflicts with instruction length"); + + return NULL; +} + void md_assemble (char *str) { @@ -3914,7 +3958,10 @@ s_riscv_leb128 (int sign) return s_leb128 (sign); } -/* Parse the .insn directive. */ +/* Parse the .insn directive. There are three formats, + Format 1: .insn , , ... + Format 2: .insn , + Format 3: .insn . */ static void s_riscv_insn (int x ATTRIBUTE_UNUSED) @@ -3935,11 +3982,15 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED) const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, insn_type_hash); - if (error) { - as_bad ("%s `%s'", error, str); + char *save_in = input_line_pointer; + error = riscv_ip_hardcode (str, &insn, &imm_expr, error); + input_line_pointer = save_in; } + + if (error) + as_bad ("%s `%s'", error, str); else { gas_assert (insn.insn_mo->pinfo != INSN_MACRO); diff --git a/gas/testsuite/gas/riscv/insn-fail.d b/gas/testsuite/gas/riscv/insn-fail.d new file mode 100644 index 00000000000..3548e85415a --- /dev/null +++ b/gas/testsuite/gas/riscv/insn-fail.d @@ -0,0 +1,3 @@ +#as: +#source: insn-fail.s +#error_output: insn-fail.l diff --git a/gas/testsuite/gas/riscv/insn-fail.l b/gas/testsuite/gas/riscv/insn-fail.l new file mode 100644 index 00000000000..e47d106b39b --- /dev/null +++ b/gas/testsuite/gas/riscv/insn-fail.l @@ -0,0 +1,7 @@ +.*Assembler messages: +.*Error: unrecognized opcode `r,0x00000013' +.*Error: values must be constant `0x4,rs1' +.*Error: unrecognized values `0x4 0x5' +.*Error: unrecognized values `0x4,0x5,0x6' +.*Error: value conflicts with instruction length `0x4,0x0001' +.*Error: value conflicts with instruction length `0x2,0x00000013' diff --git a/gas/testsuite/gas/riscv/insn-fail.s b/gas/testsuite/gas/riscv/insn-fail.s new file mode 100644 index 00000000000..064211d985d --- /dev/null +++ b/gas/testsuite/gas/riscv/insn-fail.s @@ -0,0 +1,6 @@ + .insn r, 0x00000013 + .insn 0x4, rs1 + .insn 0x4 0x5 + .insn 0x4, 0x5, 0x6 + .insn 0x4, 0x0001 + .insn 0x2, 0x00000013 diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d index 8cb3d64b1a5..4edacc63368 100644 --- a/gas/testsuite/gas/riscv/insn.d +++ b/gas/testsuite/gas/riscv/insn.d @@ -69,3 +69,9 @@ Disassembly of section .text: [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 +[^:]+:[ ]+0001[ ]+nop +[^:]+:[ ]+00000013[ ]+nop +[^:]+:[ ]+00000057[ ]+0x57 +[^:]+:[ ]+0001[ ]+nop +[^:]+:[ ]+00000013[ ]+nop +[^:]+:[ ]+00000057[ ]+0x57 diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s index 937ad119ff2..84739056b1a 100644 --- a/gas/testsuite/gas/riscv/insn.s +++ b/gas/testsuite/gas/riscv/insn.s @@ -53,3 +53,10 @@ target: .insn r 0x33, 0, 0, fa0, a1, fa2 .insn r 0x33, 0, 0, a0, fa1, fa2 .insn r 0x33, 0, 0, fa0, fa1, fa2 + + .insn 0x0001 + .insn 0x00000013 + .insn 0x00000057 + .insn 0x2, 0x0001 + .insn 0x4, 0x00000013 + .insn 0x4, 0x00000057 -- 2.30.2