From 3f9648d785b2a710949995ce3b1b84785badcff4 Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Wed, 19 May 2021 09:00:14 +0200 Subject: [PATCH 03/10] PATCH [3/10] arm: add 'aut' instruction for Armv8.1-M pacbti extension gas/ 2021-06-11 Andrea Corallo * config/tc-arm.c (insns): Add 'aut.' (T16_32_TAB): Add '_aut'. * testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Add 'aut' tests. * testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.d: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo * arm-dis.c (thumb32_opcodes): Add 'aut'. --- gas/config/tc-arm.c | 2 ++ gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l | 3 +++ gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s | 3 +++ gas/testsuite/gas/arm/armv8_1-m-pacbti.d | 1 + gas/testsuite/gas/arm/armv8_1-m-pacbti.s | 1 + opcodes/arm-dis.c | 2 ++ 6 files changed, 12 insertions(+) diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index ed870f01aee..b5d23357fc0 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -11450,6 +11450,7 @@ encode_thumb32_addr_mode (int i, bool is_t, bool is_d) X(_ands, 4000, ea100000), \ X(_asr, 1000, fa40f000), \ X(_asrs, 1000, fa50f000), \ + X(_aut, 0000, f3af802d), \ X(_b, e000, f000b000), \ X(_bcond, d000, f0008000), \ X(_bf, 0000, f040e001), \ @@ -26326,6 +26327,7 @@ static const struct asm_opcode insns[] = /* Armv8.1-M Mainline instructions. */ #undef THUMB_VARIANT #define THUMB_VARIANT & arm_ext_v8_1m_main + toU("aut", _aut, 3, (R12, LR, SP), t_pacbti), ToU("bti", f3af800f, 0, (), noargs), toU("pacbti", _pacbti, 3, (R12, LR, SP), t_pacbti), toU("cinc", _cinc, 3, (RRnpcsp, RR_ZR, COND), t_cond), diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l index a812603d88d..317e62f731b 100644 --- a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l +++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l @@ -2,3 +2,6 @@ .*:6: Error: operand must be r12 -- `pacbti r11,lr,sp' .*:7: Error: operand must be LR register -- `pacbti r12,r10,sp' .*:8: Error: operand must be SP register -- `pacbti r12,lr,r10' +.*:9: Error: operand must be r12 -- `aut r11,lr,sp' +.*:10: Error: operand must be LR register -- `aut r12,r10,sp' +.*:11: Error: operand must be SP register -- `aut r12,lr,r10' diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s index 64e71e70c11..c2ad20455c7 100644 --- a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s +++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s @@ -6,3 +6,6 @@ pacbti r11, lr, sp pacbti r12, r10, sp pacbti r12, lr, r10 + aut r11, lr, sp + aut r12, r10, sp + aut r12, lr, r10 diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d index 593ac34ed49..fe11d7eb036 100644 --- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d +++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d @@ -8,4 +8,5 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> f3af 800f bti 0[0-9a-f]+ <[^>]+> f3af 800d pacbti r12, lr, sp +0[0-9a-f]+ <[^>]+> f3af 802d aut r12, lr, sp #... diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s index 39db4542e39..14b0414a59b 100644 --- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s +++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s @@ -4,3 +4,4 @@ .Lstart: bti pacbti r12, lr, sp + aut r12, lr, sp diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 34b0ace58bc..8eeb303630b 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -4654,6 +4654,8 @@ static const struct opcode32 thumb32_opcodes[] = { /* Arm v8.1-M Mainline Pointer Authentication and Branch Target Identification Extension. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf3af802d, 0xffffffff, "aut\tr12, lr, sp"}, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 0xf3af800f, 0xffffffff, "bti"}, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), -- 2.20.1