From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by sourceware.org (Postfix) with ESMTPS id 334AE385AC0A for ; Tue, 5 Oct 2021 12:51:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 334AE385AC0A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pg1-x52a.google.com with SMTP id 75so19684438pga.3 for ; Tue, 05 Oct 2021 05:51:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kW0KufqIJZQs2HEgyDEXm+LvbgiYpSM7I4CJqvEFAaI=; b=X9kEtrRIRXJeok5sFm4IpCvfFMYX7Qcz24S6YtLO9cZJWqWTpDcXjVGRVr2JOXsX45 MVVOHSCRmS43ATdC4vcWh7aktRhKU278Pxj1Fdftw0RWEo1eKc3ropaKNCHDYufclrby OvniDxy+YpgmFs+G2Q1NWVzk7EvbT6SdhfJ7cAEJ49mOSjK5nTNmdGUn1xMCldBMP0/6 Fxk0i7zfBQYbc2WIu3GWzkaHP0VrpA/4IMxCz0NY7ibvaEIcAQ8s0ohdlg3A+YLTn5Np lsyX4HqecK2Qjex/7vEjgeVBVomGZGmCmCoEVztjHTyVo5XDK6Dp5me2A5+3dX7tYEWX R2cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kW0KufqIJZQs2HEgyDEXm+LvbgiYpSM7I4CJqvEFAaI=; b=m4UEntKF1ZRmb2P3C5rEhlyZGd2El97VAqmYZSBBsBWEdMqE+qFQoJimZk6cgeV39p KziIuoJON7R/ULrIcWn+XLhjsNE1WmFviNphxq8mMA7B+lePpRSrTPXqZFxKI8iY+dvg RGtCYMSsEQLVcXKYimxufCFoaExkl9BASc33ZZuZWa8Q+uGGs1p+Fkj4VpwF8FwnEWjf iGyF/q54tMXZ1JpYKcC6av1KOhgisoFxoS6aVwG/ZF5tOrYNxf7PLlTLqBcRq6Q1qkvP SdTJIUdAIcuV0aNtMYMpBPNlkn1iXO6n3e4BSxFuIG8GBTBBM8KlrEp7lRE7hfTBWtv2 bhNw== X-Gm-Message-State: AOAM533+Hgw7rxobThuI2NTDgf/D2hkoyA2iM8YsHNVgTBaIpSctaeEB TSLxTSFQC3WTHLYIqytwDj9Z87AJrPgsmfoL X-Google-Smtp-Source: ABdhPJzU/sa+O6hZVytxEUSEyGBTtw69dkQ6HGcIitmGJQFu2WdNVWAstfwjCvsF76+uXz5o0SapJw== X-Received: by 2002:a63:df49:: with SMTP id h9mr15554124pgj.198.1633438270644; Tue, 05 Oct 2021 05:51:10 -0700 (PDT) Received: from gamma00.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id q21sm16824435pgk.71.2021.10.05.05.51.09 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Oct 2021 05:51:10 -0700 (PDT) From: Nelson Chu To: binutils@sourceware.org, jimw@sifive.com, andrew@sifive.com Subject: [integration v2 1/4] RISC-V/rvv: Added assembly pseudo and changed assembler mnemonics. Date: Tue, 5 Oct 2021 05:51:03 -0700 Message-Id: <20211005125106.18038-2-nelson.chu@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211005125106.18038-1-nelson.chu@sifive.com> References: <20211005125106.18038-1-nelson.chu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Oct 2021 12:51:15 -0000 * Added pseudo instruction, - vfabs.v vd,vs = vfsgnjx.vv vd,vs,vs * Changed assembler mnemonics, and the older names kept as aliases, - Changed from vle1.v to vlm.v, and vse1.v to vsm.v. - Changed from vfredsum and vfwredsum to vfredusum and vfwredusum respectively. - Changed from vpopc.m to vcpop.m, to be consistent with scalar instruction. - Changed from vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm. gas/ * testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l: Updated. * testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-vmsgtvx.d: Likewise. * testsuite/gas/riscv/extended/vector-insns.d: Likewise. * testsuite/gas/riscv/extended/vector-insns.s: Likewise. include/ * opcode/riscv-opc-extended.h: Updated. opcodes/ * riscv-opc.c: Added pseudo vfabs.v, and changed assembler mnemonics. --- .../extended/vector-insns-fail-arith-floatp.l | 1 + .../extended/vector-insns-fail-arith-floatp.s | 2 ++ .../gas/riscv/extended/vector-insns-vmsgtvx.d | 12 +++---- .../gas/riscv/extended/vector-insns.d | 36 ++++++++++++------- .../gas/riscv/extended/vector-insns.s | 32 +++++++++++------ include/opcode/riscv-opc-extended.h | 28 +++++++-------- opcodes/riscv-opc.c | 23 ++++++++---- 7 files changed, 85 insertions(+), 49 deletions(-) diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l index bcc49a09080..9900dbb1e58 100644 --- a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l +++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l @@ -34,6 +34,7 @@ .*Error: illegal operands vd cannot overlap vm `vfmax.vv v0,v4,v8,v0.t' .*Error: illegal operands vd cannot overlap vm `vfmax.vf v0,v4,fa1,v0.t' .*Error: illegal operands vd cannot overlap vm `vfneg.v v0,v4,v0.t' +.*Error: illegal operands vd cannot overlap vm `vfabs.v v0,v4,v0.t' .*Error: illegal operands vd cannot overlap vm `vfsgnj.vv v0,v4,v8,v0.t' .*Error: illegal operands vd cannot overlap vm `vfsgnj.vf v0,v4,fa1,v0.t' .*Error: illegal operands vd cannot overlap vm `vfsgnjn.vv v0,v4,v8,v0.t' diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s index a48b1a3fd33..19ed26a95aa 100644 --- a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s +++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s @@ -120,6 +120,8 @@ vfneg.v v4, v4 # OK vfneg.v v0, v4, v0.t # vd overlap vm + vfabs.v v4, v4 # OK + vfabs.v v0, v4, v0.t # vd overlap vm vfsgnj.vv v4, v4, v8 # OK vfsgnj.vv v8, v4, v8 # OK diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/extended/vector-insns-vmsgtvx.d index 4d33fe7d596..dcc951a3cbf 100644 --- a/gas/testsuite/gas/riscv/extended/vector-insns-vmsgtvx.d +++ b/gas/testsuite/gas/riscv/extended/vector-insns-vmsgtvx.d @@ -12,18 +12,18 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+6cc64457[ ]+vmslt.vx[ ]+v8,v12,a2,v0.t [ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0 [ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t -[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandnot.mm[ ]+v0,v0,v12 +[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandn.mm[ ]+v0,v0,v12 [ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t -[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandnot.mm[ ]+v12,v0,v12 -[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandnot.mm[ ]+v4,v4,v0 +[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandn.mm[ ]+v12,v0,v12 +[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandn.mm[ ]+v4,v4,v0 [ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4 [ ]+[0-9a-f]+:[ ]+6a85c257[ ]+vmsltu.vx[ ]+v4,v8,a1 [ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4 [ ]+[0-9a-f]+:[ ]+68c64457[ ]+vmsltu.vx[ ]+v8,v12,a2,v0.t [ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0 [ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t -[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandnot.mm[ ]+v0,v0,v12 +[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandn.mm[ ]+v0,v0,v12 [ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t -[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandnot.mm[ ]+v12,v0,v12 -[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandnot.mm[ ]+v4,v4,v0 +[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandn.mm[ ]+v12,v0,v12 +[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandn.mm[ ]+v4,v4,v0 [ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4 diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.d b/gas/testsuite/gas/riscv/extended/vector-insns.d index 01770c48bdd..1b665f6cc0d 100644 --- a/gas/testsuite/gas/riscv/extended/vector-insns.d +++ b/gas/testsuite/gas/riscv/extended/vector-insns.d @@ -44,10 +44,14 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+ca95f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,ma [ ]+[0-9a-f]+:[ ]+c695f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,mu [ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu -[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vle1.v[ ]+v4,\(a0\) -[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vle1.v[ ]+v4,\(a0\) -[ ]+[0-9a-f]+:[ ]+02b50227[ ]+vse1.v[ ]+v4,\(a0\) -[ ]+[0-9a-f]+:[ ]+02b50227[ ]+vse1.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02b50227[ ]+vsm.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02b50227[ ]+vsm.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02b50227[ ]+vsm.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02b50227[ ]+vsm.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+02050207[ ]+vle8.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+02050207[ ]+vle8.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+00050207[ ]+vle8.v[ ]+v4,\(a0\),v0.t @@ -1762,6 +1766,8 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+18865257[ ]+vfmax.vf[ ]+v4,v8,fa2,v0.t [ ]+[0-9a-f]+:[ ]+26841257[ ]+vfneg.v[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+24841257[ ]+vfneg.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+2a841257[ ]+vfabs.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+28841257[ ]+vfabs.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+22861257[ ]+vfsgnj.vv[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+22865257[ ]+vfsgnj.vf[ ]+v4,v8,fa2 [ ]+[0-9a-f]+:[ ]+26861257[ ]+vfsgnjn.vv[ ]+v4,v8,v12 @@ -1863,17 +1869,21 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+c0860257[ ]+vwredsumu.vs[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+c4860257[ ]+vwredsum.vs[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+0e861257[ ]+vfredosum.vs[ ]+v4,v8,v12 -[ ]+[0-9a-f]+:[ ]+06861257[ ]+vfredsum.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+06861257[ ]+vfredusum.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+06861257[ ]+vfredusum.vs[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+1e861257[ ]+vfredmax.vs[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+16861257[ ]+vfredmin.vs[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+0c861257[ ]+vfredosum.vs[ ]+v4,v8,v12,v0.t -[ ]+[0-9a-f]+:[ ]+04861257[ ]+vfredsum.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+04861257[ ]+vfredusum.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+04861257[ ]+vfredusum.vs[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+1c861257[ ]+vfredmax.vs[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+14861257[ ]+vfredmin.vs[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+ce861257[ ]+vfwredosum.vs[ ]+v4,v8,v12 -[ ]+[0-9a-f]+:[ ]+c6861257[ ]+vfwredsum.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+c6861257[ ]+vfwredusum.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+c6861257[ ]+vfwredusum.vs[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+cc861257[ ]+vfwredosum.vs[ ]+v4,v8,v12,v0.t -[ ]+[0-9a-f]+:[ ]+c4861257[ ]+vfwredsum.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+c4861257[ ]+vfwredusum.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+c4861257[ ]+vfwredusum.vs[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+66842257[ ]+vmmv.m[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+66842257[ ]+vmmv.m[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+6e422257[ ]+vmclr.m[ ]+v4 @@ -1881,20 +1891,22 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+76842257[ ]+vmnot.m[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+66862257[ ]+vmand.mm[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+76862257[ ]+vmnand.mm[ ]+v4,v8,v12 -[ ]+[0-9a-f]+:[ ]+62862257[ ]+vmandnot.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+62862257[ ]+vmandn.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+62862257[ ]+vmandn.mm[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+6e862257[ ]+vmxor.mm[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+6a862257[ ]+vmor.mm[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+7a862257[ ]+vmnor.mm[ ]+v4,v8,v12 -[ ]+[0-9a-f]+:[ ]+72862257[ ]+vmornot.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+72862257[ ]+vmorn.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+72862257[ ]+vmorn.mm[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+7e862257[ ]+vmxnor.mm[ ]+v4,v8,v12 -[ ]+[0-9a-f]+:[ ]+42c82557[ ]+vpopc.m[ ]+a0,v12 +[ ]+[0-9a-f]+:[ ]+42c82557[ ]+vcpop.m[ ]+a0,v12 [ ]+[0-9a-f]+:[ ]+42c8a557[ ]+vfirst.m[ ]+a0,v12 [ ]+[0-9a-f]+:[ ]+5280a257[ ]+vmsbf.m[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+5281a257[ ]+vmsif.m[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+52812257[ ]+vmsof.m[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+52882257[ ]+viota.m[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+5208a257[ ]+vid.v[ ]+v4 -[ ]+[0-9a-f]+:[ ]+40c82557[ ]+vpopc.m[ ]+a0,v12,v0.t +[ ]+[0-9a-f]+:[ ]+40c82557[ ]+vcpop.m[ ]+a0,v12,v0.t [ ]+[0-9a-f]+:[ ]+40c8a557[ ]+vfirst.m[ ]+a0,v12,v0.t [ ]+[0-9a-f]+:[ ]+5080a257[ ]+vmsbf.m[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+5081a257[ ]+vmsif.m[ ]+v4,v8,v0.t diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.s b/gas/testsuite/gas/riscv/extended/vector-insns.s index 5c78e28e776..0f894a355aa 100644 --- a/gas/testsuite/gas/riscv/extended/vector-insns.s +++ b/gas/testsuite/gas/riscv/extended/vector-insns.s @@ -36,9 +36,13 @@ vsetivli a0, 0xb, e256, m2, ta, mu vsetivli a0, 0xb, e256, m2, tu, mu - vle1.v v4, (a0) + vlm.v v4, (a0) + vlm.v v4, 0(a0) + vle1.v v4, (a0) # Alias of vlm.v vle1.v v4, 0(a0) - vse1.v v4, (a0) + vsm.v v4, (a0) + vsm.v v4, 0(a0) + vse1.v v4, (a0) # Alias of vsm.v vse1.v v4, 0(a0) vle8.v v4, (a0) @@ -1978,6 +1982,8 @@ vfneg.v v4, v8 vfneg.v v4, v8, v0.t + vfabs.v v4, v8 + vfabs.v v4, v8, v0.t vfsgnj.vv v4, v8, v12 vfsgnj.vf v4, v8, fa2 @@ -2090,18 +2096,22 @@ vwredsum.vs v4, v8, v12, v0.t vfredosum.vs v4, v8, v12 - vfredsum.vs v4, v8, v12 + vfredusum.vs v4, v8, v12 + vfredsum.vs v4, v8, v12 # Alias of vfredusum.vs. vfredmax.vs v4, v8, v12 vfredmin.vs v4, v8, v12 vfredosum.vs v4, v8, v12, v0.t - vfredsum.vs v4, v8, v12, v0.t + vfredusum.vs v4, v8, v12, v0.t + vfredsum.vs v4, v8, v12, v0.t # Alias of vfredusum.vs. vfredmax.vs v4, v8, v12, v0.t vfredmin.vs v4, v8, v12, v0.t vfwredosum.vs v4, v8, v12 - vfwredsum.vs v4, v8, v12 + vfwredusum.vs v4, v8, v12 + vfwredsum.vs v4, v8, v12 # Alias of vfwredusum.vs. vfwredosum.vs v4, v8, v12, v0.t - vfwredsum.vs v4, v8, v12, v0.t + vfwredusum.vs v4, v8, v12, v0.t + vfwredsum.vs v4, v8, v12, v0.t # Alias of vfwredusum.vs. # Aliases vmcpy.m v4, v8 @@ -2112,21 +2122,23 @@ vmand.mm v4, v8, v12 vmnand.mm v4, v8, v12 - vmandnot.mm v4, v8, v12 + vmandn.mm v4, v8, v12 + vmandnot.mm v4, v8, v12 # Alias of vmandn.mm. vmxor.mm v4, v8, v12 vmor.mm v4, v8, v12 vmnor.mm v4, v8, v12 - vmornot.mm v4, v8, v12 + vmorn.mm v4, v8, v12 + vmornot.mm v4, v8, v12 # Alias of vmorn.mm. vmxnor.mm v4, v8, v12 - vpopc.m a0, v12 + vcpop.m a0, v12 vfirst.m a0, v12 vmsbf.m v4, v8 vmsif.m v4, v8 vmsof.m v4, v8 viota.m v4, v8 vid.v v4 - vpopc.m a0, v12, v0.t + vcpop.m a0, v12, v0.t vfirst.m a0, v12, v0.t vmsbf.m v4, v8, v0.t vmsif.m v4, v8, v0.t diff --git a/include/opcode/riscv-opc-extended.h b/include/opcode/riscv-opc-extended.h index 3de8809b4c2..de9741f9b39 100644 --- a/include/opcode/riscv-opc-extended.h +++ b/include/opcode/riscv-opc-extended.h @@ -99,10 +99,10 @@ #define MASK_VSETIVLI 0xc000707f #define MATCH_VSETVLI 0x00007057 #define MASK_VSETVLI 0x8000707f -#define MATCH_VLE1V 0x02b00007 -#define MASK_VLE1V 0xfff0707f -#define MATCH_VSE1V 0x02b00027 -#define MASK_VSE1V 0xfff0707f +#define MATCH_VLMV 0x02b00007 +#define MASK_VLMV 0xfff0707f +#define MATCH_VSMV 0x02b00027 +#define MASK_VSMV 0xfff0707f #define MATCH_VLE8V 0x00000007 #define MASK_VLE8V 0xfdf0707f #define MATCH_VLE16V 0x00005007 @@ -1359,34 +1359,34 @@ #define MASK_VWREDSUMVS 0xfc00707f #define MATCH_VFREDOSUMVS 0x0c001057 #define MASK_VFREDOSUMVS 0xfc00707f -#define MATCH_VFREDSUMVS 0x04001057 -#define MASK_VFREDSUMVS 0xfc00707f +#define MATCH_VFREDUSUMVS 0x04001057 +#define MASK_VFREDUSUMVS 0xfc00707f #define MATCH_VFREDMAXVS 0x1c001057 #define MASK_VFREDMAXVS 0xfc00707f #define MATCH_VFREDMINVS 0x14001057 #define MASK_VFREDMINVS 0xfc00707f #define MATCH_VFWREDOSUMVS 0xcc001057 #define MASK_VFWREDOSUMVS 0xfc00707f -#define MATCH_VFWREDSUMVS 0xc4001057 -#define MASK_VFWREDSUMVS 0xfc00707f +#define MATCH_VFWREDUSUMVS 0xc4001057 +#define MASK_VFWREDUSUMVS 0xfc00707f #define MATCH_VMANDMM 0x66002057 #define MASK_VMANDMM 0xfe00707f #define MATCH_VMNANDMM 0x76002057 #define MASK_VMNANDMM 0xfe00707f -#define MATCH_VMANDNOTMM 0x62002057 -#define MASK_VMANDNOTMM 0xfe00707f +#define MATCH_VMANDNMM 0x62002057 +#define MASK_VMANDNMM 0xfe00707f #define MATCH_VMXORMM 0x6e002057 #define MASK_VMXORMM 0xfe00707f #define MATCH_VMORMM 0x6a002057 #define MASK_VMORMM 0xfe00707f #define MATCH_VMNORMM 0x7a002057 #define MASK_VMNORMM 0xfe00707f -#define MATCH_VMORNOTMM 0x72002057 -#define MASK_VMORNOTMM 0xfe00707f +#define MATCH_VMORNMM 0x72002057 +#define MASK_VMORNMM 0xfe00707f #define MATCH_VMXNORMM 0x7e002057 #define MASK_VMXNORMM 0xfe00707f -#define MATCH_VPOPCM 0x40082057 -#define MASK_VPOPCM 0xfc0ff07f +#define MATCH_VCPOPM 0x40082057 +#define MASK_VCPOPM 0xfc0ff07f #define MATCH_VFIRSTM 0x4008a057 #define MASK_VFIRSTM 0xfc0ff07f #define MATCH_VMSBFM 0x5000a057 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 05f94704774..cccc3553c60 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1417,8 +1417,10 @@ const struct riscv_opcode riscv_draft_opcodes[] = {"vsetvli", 0, INSN_CLASS_V, "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0}, {"vsetivli", 0, INSN_CLASS_V, "d,Z,Vb", MATCH_VSETIVLI, MASK_VSETIVLI, match_opcode, 0}, -{"vle1.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VLE1V, MASK_VLE1V, match_opcode, INSN_DREF }, -{"vse1.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VSE1V, MASK_VSE1V, match_opcode, INSN_DREF }, +{"vlm.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VLMV, MASK_VLMV, match_opcode, INSN_DREF }, +{"vsm.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VSMV, MASK_VSMV, match_opcode, INSN_DREF }, +{"vle1.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VLMV, MASK_VLMV, match_opcode, INSN_DREF|INSN_ALIAS }, +{"vse1.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VSMV, MASK_VSMV, match_opcode, INSN_DREF|INSN_ALIAS }, {"vle8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_vd_neq_vm, INSN_DREF }, {"vle16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_vd_neq_vm, INSN_DREF }, @@ -2087,6 +2089,7 @@ const struct riscv_opcode riscv_draft_opcodes[] = {"vfmax.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_vd_neq_vm, 0}, {"vfneg.v", 0, INSN_CLASS_V_AND_F, "Vd,VuVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vs1_eq_vs2_neq_vm, INSN_ALIAS }, +{"vfabs.v", 0, INSN_CLASS_V_AND_F, "Vd,VuVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vs1_eq_vs2_neq_vm, INSN_ALIAS }, {"vfsgnj.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_vd_neq_vm, 0}, {"vfsgnj.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_vd_neq_vm, 0}, @@ -2150,12 +2153,14 @@ const struct riscv_opcode riscv_draft_opcodes[] = {"vwredsum.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0}, {"vfredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0}, -{"vfredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDSUMVS, MASK_VFREDSUMVS, match_opcode, 0}, +{"vfredusum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDUSUMVS, MASK_VFREDUSUMVS, match_opcode, 0}, +{"vfredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDUSUMVS, MASK_VFREDUSUMVS, match_opcode, INSN_ALIAS}, {"vfredmax.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0}, {"vfredmin.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0}, {"vfwredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0}, -{"vfwredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDSUMVS, MASK_VFWREDSUMVS, match_opcode, 0}, +{"vfwredusum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, 0}, +{"vfwredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, INSN_ALIAS}, {"vmmv.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS}, {"vmcpy.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS}, @@ -2165,14 +2170,18 @@ const struct riscv_opcode riscv_draft_opcodes[] = {"vmand.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0}, {"vmnand.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0}, -{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNOTMM, MASK_VMANDNOTMM, match_opcode, 0}, + +{"vmandn.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, 0}, +{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, INSN_ALIAS}, {"vmxor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0}, {"vmor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0}, {"vmnor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0}, -{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNOTMM, MASK_VMORNOTMM, match_opcode, 0}, +{"vmorn.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, 0}, +{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, INSN_ALIAS}, {"vmxnor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0}, -{"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0}, +{"vcpop.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VCPOPM, MASK_VCPOPM, match_opcode, 0}, +{"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VCPOPM, MASK_VCPOPM, match_opcode, INSN_ALIAS}, {"vfirst.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0}, {"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vs2_neq_vm, 0}, {"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vs2_neq_vm, 0}, -- 2.30.2