From: Nelson Chu <nelson.chu@sifive.com>
To: binutils@sourceware.org, jimw@sifive.com, andrew@sifive.com
Subject: [integration v2 4/4] RISC-V/rvv: Added zve* and zvl* extensions, and clarify the imply rules.
Date: Tue, 5 Oct 2021 05:51:06 -0700 [thread overview]
Message-ID: <20211005125106.18038-5-nelson.chu@sifive.com> (raw)
In-Reply-To: <20211005125106.18038-1-nelson.chu@sifive.com>
* Recognized zve* and zvl* extensions.
- zve*: zve64d, zve64f, zve64x, zve32f and zve32x.
- zvl*: zvl32b, zvl64b, zvl128b, zvl256b, zvl512b, zvl1024b, zvl2048b,
zvl4096b, zvl8192b, zvl16384b, zvl32768b and zvl65536b.
* Spec said that v requires f and d, zve64d requires d, zve64f and zve32f
require f. However, according to the issue 723,
[https://github.com/riscv/riscv-v-spec/issues/723]
The general rule is that extension names imply the things they require.
Therefore, the current imply rules should be as follows,
- v imply f and d.
- zve64d imply d.
- zve64f and zve32f imply f.
- zvamo imply a.
Besides, consider the implicit zve and zvl extensions,
- v imply zve64d and zvl128b.
- zve64* imply the corresponding zve32*. For example, zve64f imply zve32f,
and zve64x imply zve32x.
- zve*d imply zve*f and zve*x. For example, zve64d imply zve64f and zve64x.
- zve*f imply zve*x. For example, zve64f imply zve64x.
- zve64* imply zvl64b, and zve32* imply zvl32b.
- The larger zvl* imply all smaller zvl*. For example, zvl128b imply zvl64b,
and zvl32b.
Therefore, "-march=rv64iv -misa-spec=20191213" will be
"rv64i2p0_f2p0_d2p0_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0".
Note: zicsr is the imply extension of f.
* For zve32x, the (segmant) load/store instructions are illegal when EEW is
64. Besides, vsew cannot be set to 64 by vsetvli when zve32* is enabled.
* For zvl*b extensions, we alos need to enable either v or zve* extensions.
Otherwise we should issue errors.
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Added imply rules for v,
zve* and zvl*b extensions.
(riscv_supported_std_z_ext): Added zve* and zvl*b extensions.
(riscv_parse_check_conflicts): The zvl*b extensions cannot be set
without v and zve* extensions.
gas/
* config/tc-riscv.c (riscv_extended_subset_supports): Handle zve*.
(my_getVsetvliExpression): vsew cannot be set to 64 by vsetvli
when zve32* is enabled.
(riscv_ip): The (segmant) loads and stores with EEW 64 cannot be
used when zve32x is enabled.
* testsuite/gas/riscv/extended/march-imply-v.d: New testcase.
* testsuite/gas/riscv/extended/march-imply-zve*.d: Likewise.
* testsuite/gas/riscv/extended/march-imply-zvl*b.d: Likewise.
* testsuite/gas/riscv/extended/vector-insns-fail-zve32x.d: Likewise.
* testsuite/gas/riscv/extended/vector-insns-fail-zve32x.l: Likewise.
* testsuite/gas/riscv/extended/vector-insns-fail-zve32x.s: Likewise.
* testsuite/gas/riscv/extended/vector-insns-fail-zvl.d: Likewise.
* testsuite/gas/riscv/extended/vector-insns-fail-zvl.l: Likewise.
* testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d: Removed
a-ext from -march since it will be added as implicit ext for zvamo.
* testsuite/gas/riscv/extended/vector-insns.d: Likewise.
include/
* opcode/riscv.h: Defined INSN_V_EEW64.
opcodes/
* riscv-opc.c (riscv_draft_opcodes): Added INSN_V_EEW64 for vector
loads and stores when the eew encodings are 64.
---
bfd/elfxx-riscv.c | 66 +++
gas/config/tc-riscv.c | 29 +-
.../gas/riscv/extended/march-imply-v.d | 6 +
.../gas/riscv/extended/march-imply-zve32f.d | 6 +
.../gas/riscv/extended/march-imply-zve32x.d | 6 +
.../gas/riscv/extended/march-imply-zve64d.d | 6 +
.../gas/riscv/extended/march-imply-zve64f.d | 6 +
.../gas/riscv/extended/march-imply-zve64x.d | 6 +
.../gas/riscv/extended/march-imply-zvl1024b.d | 6 +
.../gas/riscv/extended/march-imply-zvl128b.d | 6 +
.../riscv/extended/march-imply-zvl16384b.d | 6 +
.../gas/riscv/extended/march-imply-zvl2048b.d | 6 +
.../gas/riscv/extended/march-imply-zvl256b.d | 6 +
.../riscv/extended/march-imply-zvl32768b.d | 6 +
.../gas/riscv/extended/march-imply-zvl4096b.d | 6 +
.../gas/riscv/extended/march-imply-zvl512b.d | 6 +
.../gas/riscv/extended/march-imply-zvl64b.d | 6 +
.../riscv/extended/march-imply-zvl65536b.d | 6 +
.../gas/riscv/extended/march-imply-zvl8192b.d | 6 +
.../riscv/extended/vector-insns-fail-zvamo.d | 2 +-
.../riscv/extended/vector-insns-fail-zve32x.d | 3 +
.../riscv/extended/vector-insns-fail-zve32x.l | 82 ++++
.../riscv/extended/vector-insns-fail-zve32x.s | 413 ++++++++++++++++++
.../riscv/extended/vector-insns-fail-zvl.d | 3 +
.../riscv/extended/vector-insns-fail-zvl.l | 2 +
.../gas/riscv/extended/vector-insns.d | 2 +-
include/opcode/riscv.h | 2 +
opcodes/riscv-opc.c | 152 +++----
28 files changed, 777 insertions(+), 81 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-v.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zve32f.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zve32x.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zve64d.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zve64f.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zve64x.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zvl1024b.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zvl128b.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zvl16384b.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zvl2048b.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zvl256b.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zvl32768b.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zvl4096b.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zvl512b.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zvl64b.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zvl65536b.d
create mode 100644 gas/testsuite/gas/riscv/extended/march-imply-zvl8192b.d
create mode 100644 gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.d
create mode 100644 gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.l
create mode 100644 gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.s
create mode 100644 gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.d
create mode 100644 gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.l
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 62b92a05f25..f161181bcac 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1073,6 +1073,32 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"g", "zicsr", check_implicit_always},
{"g", "zifencei", check_implicit_always},
{"q", "d", check_implicit_always},
+ {"v", "d", check_implicit_always},
+ {"v", "zve64d", check_implicit_always},
+ {"v", "zvl128b", check_implicit_always},
+ {"zvamo", "a", check_implicit_always},
+ {"zve64d", "d", check_implicit_always},
+ {"zve64d", "zve64f", check_implicit_always},
+ {"zve64f", "zve32f", check_implicit_always},
+ {"zve64f", "zve64x", check_implicit_always},
+ {"zve64f", "zvl64b", check_implicit_always},
+ {"zve32f", "f", check_implicit_always},
+ {"zve32f", "zvl32b", check_implicit_always},
+ {"zve32f", "zve32x", check_implicit_always},
+ {"zve64x", "zve32x", check_implicit_always},
+ {"zve64x", "zvl64b", check_implicit_always},
+ {"zve32x", "zvl32b", check_implicit_always},
+ {"zvl65536b", "zvl32768b", check_implicit_always},
+ {"zvl32768b", "zvl16384b", check_implicit_always},
+ {"zvl16384b", "zvl8192b", check_implicit_always},
+ {"zvl8192b", "zvl4096b", check_implicit_always},
+ {"zvl4096b", "zvl2048b", check_implicit_always},
+ {"zvl2048b", "zvl1024b", check_implicit_always},
+ {"zvl1024b", "zvl512b", check_implicit_always},
+ {"zvl512b", "zvl256b", check_implicit_always},
+ {"zvl256b", "zvl128b", check_implicit_always},
+ {"zvl128b", "zvl64b", check_implicit_always},
+ {"zvl64b", "zvl32b", check_implicit_always},
{"d", "f", check_implicit_always},
{"f", "zicsr", check_implicit_always},
{"zfh", "f", check_implicit_always},
@@ -1148,6 +1174,24 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zba", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 },
{"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 },
{"zvamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zve32x", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zve32f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zve32d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zve64x", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvl256b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvl512b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvl1024b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvl2048b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvl4096b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvl8192b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvl16384b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvl32768b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvl65536b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfh", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, /* draft. */
{NULL, 0, 0, 0, 0}
};
@@ -1841,6 +1885,28 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
(_("rv32e does not support the `f' extension"));
no_conflict = false;
}
+
+ bool support_zve = false;
+ bool support_zvl = false;
+ riscv_subset_t *s = rps->subset_list->head;
+ for (; s != NULL; s = s->next)
+ {
+ if (!support_zve
+ && strncmp (s->name, "zve", 3) == 0)
+ support_zve = true;
+ if (!support_zvl
+ && strncmp (s->name, "zvl", 3) == 0)
+ support_zvl = true;
+ if (support_zve && support_zvl)
+ break;
+ }
+ if (support_zvl && !support_zve)
+ {
+ rps->error_handler
+ (_("zvl*b extensions need to enable either `v' or `zve' extension"));
+ no_conflict = false;
+ }
+
return no_conflict;
}
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index acdb303f4b9..8c0aa1cecde 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -274,11 +274,17 @@ riscv_extended_subset_supports (int insn_class)
{
switch (insn_class)
{
- case INSN_CLASS_V: return riscv_subset_supports ("v");
+ case INSN_CLASS_V:
+ return (riscv_subset_supports ("v")
+ || riscv_subset_supports ("zve64x")
+ || riscv_subset_supports ("zve32x"));
case INSN_CLASS_V_AND_F:
- return riscv_subset_supports ("v") && riscv_subset_supports ("f");
+ return (riscv_subset_supports ("v")
+ || riscv_subset_supports ("zve64d")
+ || riscv_subset_supports ("zve64f")
+ || riscv_subset_supports ("zve32f"));
case INSN_CLASS_ZVAMO:
- return riscv_subset_supports ("a") && riscv_subset_supports ("zvamo");
+ return riscv_subset_supports ("zvamo");
case INSN_CLASS_ZFH:
return riscv_subset_supports ("zfh");
@@ -2450,6 +2456,13 @@ my_getVsetvliExpression (expressionS *ep, char *str)
++str;
if (vsew_found)
as_bad (_("multiple vsew constants"));
+ /* The zve32x is the implicit extension of zve32f, and the zve64x is
+ the implicit extension of zve64f. */
+ else if (riscv_subset_supports ("zve32x")
+ && !riscv_subset_supports ("zve64x")
+ && vsew_value > 2)
+ as_bad (_("illegal vsew %s for zve32x and zve32f"),
+ riscv_vsew[vsew_value]);
vsew_found = true;
}
if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &vlmul_value))
@@ -2859,6 +2872,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
as_warn (_("read-only CSR is written `%s'"), str);
insn_with_csr = false;
}
+
+ /* The (segmant) load and store with EEW 64 cannot be used
+ when zve32x is enabled. */
+ if (ip->insn_mo->pinfo & INSN_V_EEW64
+ && riscv_subset_supports ("zve32x")
+ && !riscv_subset_supports ("zve64x"))
+ {
+ error = _("illegal opcode for zve32x");
+ break;
+ }
}
if (*asarg != '\0')
break;
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-v.d b/gas/testsuite/gas/riscv/extended/march-imply-v.d
new file mode 100644
index 00000000000..4177f0328bc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-v.d
@@ -0,0 +1,6 @@
+#as: -march=rv32iv -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zve32f.d b/gas/testsuite/gas/riscv/extended/march-imply-zve32f.d
new file mode 100644
index 00000000000..17b7a67cc95
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zve32f.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32f -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zve32x.d b/gas/testsuite/gas/riscv/extended/march-imply-zve32x.d
new file mode 100644
index 00000000000..34742e544dc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zve32x.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl32b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zve64d.d b/gas/testsuite/gas/riscv/extended/march-imply-zve64d.d
new file mode 100644
index 00000000000..f5fb6a5fc1c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zve64d.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve64d -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zve64f.d b/gas/testsuite/gas/riscv/extended/march-imply-zve64f.d
new file mode 100644
index 00000000000..2cd7224a29d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zve64f.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve64f -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zve64x.d b/gas/testsuite/gas/riscv/extended/march-imply-zve64x.d
new file mode 100644
index 00000000000..96dea6f58a6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zve64x.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve64x -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl1024b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl1024b.d
new file mode 100644
index 00000000000..4a68a9c9425
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl1024b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl1024b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl128b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl128b.d
new file mode 100644
index 00000000000..ef1ac30b9ba
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl128b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl128b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl16384b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl16384b.d
new file mode 100644
index 00000000000..a05077afbcd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl16384b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl16384b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl2048b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl2048b.d
new file mode 100644
index 00000000000..8c45a9812d2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl2048b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl2048b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl256b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl256b.d
new file mode 100644
index 00000000000..515bfdb0513
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl256b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl256b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl32768b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl32768b.d
new file mode 100644
index 00000000000..a10b11a74e9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl32768b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl32768b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl4096b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl4096b.d
new file mode 100644
index 00000000000..0951b57366f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl4096b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl4096b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl512b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl512b.d
new file mode 100644
index 00000000000..14b439011c7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl512b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl512b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl64b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl64b.d
new file mode 100644
index 00000000000..071bd245a28
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl64b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl64b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl32b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl65536b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl65536b.d
new file mode 100644
index 00000000000..8b1739feb74
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl65536b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl65536b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl8192b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl8192b.d
new file mode 100644
index 00000000000..ddfdc5019d7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl8192b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl8192b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d
index 8a6de14600c..ff06d2377a3 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d
@@ -1,3 +1,3 @@
-#as: -march=rv32ia_zvamo -mcheck-constraints
+#as: -march=rv32i_zvamo -mcheck-constraints
#source: vector-insns-fail-zvamo.s
#error_output: vector-insns-fail-zvamo.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.d
new file mode 100644
index 00000000000..3c60e8026a9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_zvamo_zve32x
+#source: vector-insns-fail-zve32x.s
+#error_output: vector-insns-fail-zve32x.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.l b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.l
new file mode 100644
index 00000000000..13f747c7ccb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.l
@@ -0,0 +1,82 @@
+.*Assembler messages:
+.*Error: illegal vsew e64 for zve32x and zve32f
+.*Error: illegal vsew e128 for zve32x and zve32f
+.*Error: illegal vsew e256 for zve32x and zve32f
+.*Error: illegal vsew e512 for zve32x and zve32f
+.*Error: illegal vsew e1024 for zve32x and zve32f
+.*Error: illegal opcode for zve32x `vle64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vse64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlse64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vsse64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vloxei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vle64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg2e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg2e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg3e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg3e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg4e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg4e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg5e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg5e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg6e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg6e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg7e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg7e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg8e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg8e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlsseg2e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg2e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg3e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg3e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg4e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg4e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg5e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg5e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg6e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg6e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg7e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg7e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg8e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg8e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vloxseg2ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg2ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg3ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg3ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg4ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg4ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg5ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg5ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg6ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg6ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg7ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg7ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg8ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg8ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg2ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg2ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg3ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg3ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg4ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg4ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg5ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg5ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg6ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg6ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg7ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg7ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg8ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg8ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vlseg2e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg3e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg4e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg5e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg6e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg7e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg8e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vl1re64.v v3,\(a0\)'
+.*Error: illegal opcode for zve32x `vl2re64.v v2,\(a0\)'
+.*Error: illegal opcode for zve32x `vl4re64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vl8re64.v v8,\(a0\)'
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.s b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.s
new file mode 100644
index 00000000000..7a0bfe88db8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.s
@@ -0,0 +1,413 @@
+ vsetvl a0, a1, a2
+ vsetvli a0, a1, e8
+ vsetvli a0, a1, e16, m2
+ vsetvli a0, a1, e32, m2, ta
+ vsetvli a0, a1, e64, m2, ta, ma
+ vsetvli a0, a1, e128
+ vsetvli a0, a1, e256, m2
+ vsetvli a0, a1, e512, m2, ta
+ vsetvli a0, a1, e1024, m2, ta, ma
+
+ vlm.v v4, (a0)
+ vle1.v v4, (a0) # Alias of vlm.v
+ vsm.v v4, (a0)
+ vse1.v v4, (a0) # Alias of vsm.v
+
+ vle8.v v4, (a0)
+ vse8.v v4, (a0)
+ vle16.v v4, (a0)
+ vse16.v v4, (a0)
+ vle32.v v4, (a0)
+ vse32.v v4, (a0)
+ vle64.v v4, (a0)
+ vse64.v v4, (a0)
+
+ vlse8.v v4, (a0), a1
+ vsse8.v v4, (a0), a1
+ vlse16.v v4, (a0), a1
+ vsse16.v v4, (a0), a1
+ vlse32.v v4, (a0), a1
+ vsse32.v v4, (a0), a1
+ vlse64.v v4, (a0), a1
+ vsse64.v v4, (a0), a1
+
+ vloxei8.v v4, (a0), v12
+ vsoxei8.v v4, (a0), v12
+ vluxei8.v v4, (a0), v12
+ vsuxei8.v v4, (a0), v12
+ vloxei16.v v4, (a0), v12
+ vsoxei16.v v4, (a0), v12
+ vluxei16.v v4, (a0), v12
+ vsuxei16.v v4, (a0), v12
+ vloxei32.v v4, (a0), v12
+ vsoxei32.v v4, (a0), v12
+ vluxei32.v v4, (a0), v12
+ vsuxei32.v v4, (a0), v12
+ vloxei64.v v4, (a0), v12
+ vsoxei64.v v4, (a0), v12
+ vluxei64.v v4, (a0), v12
+ vsuxei64.v v4, (a0), v12
+
+ vle8ff.v v4, (a0)
+ vle16ff.v v4, (a0)
+ vle32ff.v v4, (a0)
+ vle64ff.v v4, (a0)
+
+ vlseg2e8.v v4, (a0)
+ vsseg2e8.v v4, (a0)
+ vlseg3e8.v v4, (a0)
+ vsseg3e8.v v4, (a0)
+ vlseg4e8.v v4, (a0)
+ vsseg4e8.v v4, (a0)
+ vlseg5e8.v v4, (a0)
+ vsseg5e8.v v4, (a0)
+ vlseg6e8.v v4, (a0)
+ vsseg6e8.v v4, (a0)
+ vlseg7e8.v v4, (a0)
+ vsseg7e8.v v4, (a0)
+ vlseg8e8.v v4, (a0)
+ vsseg8e8.v v4, (a0)
+ vlseg2e16.v v4, (a0)
+ vsseg2e16.v v4, (a0)
+ vlseg3e16.v v4, (a0)
+ vsseg3e16.v v4, (a0)
+ vlseg4e16.v v4, (a0)
+ vsseg4e16.v v4, (a0)
+ vlseg5e16.v v4, (a0)
+ vsseg5e16.v v4, (a0)
+ vlseg6e16.v v4, (a0)
+ vsseg6e16.v v4, (a0)
+ vlseg7e16.v v4, (a0)
+ vsseg7e16.v v4, (a0)
+ vlseg8e16.v v4, (a0)
+ vsseg8e16.v v4, (a0)
+ vlseg2e32.v v4, (a0)
+ vsseg2e32.v v4, (a0)
+ vlseg3e32.v v4, (a0)
+ vsseg3e32.v v4, (a0)
+ vlseg4e32.v v4, (a0)
+ vsseg4e32.v v4, (a0)
+ vlseg5e32.v v4, (a0)
+ vsseg5e32.v v4, (a0)
+ vlseg6e32.v v4, (a0)
+ vsseg6e32.v v4, (a0)
+ vlseg7e32.v v4, (a0)
+ vsseg7e32.v v4, (a0)
+ vlseg8e32.v v4, (a0)
+ vsseg8e32.v v4, (a0)
+ vlseg2e64.v v4, (a0)
+ vsseg2e64.v v4, (a0)
+ vlseg3e64.v v4, (a0)
+ vsseg3e64.v v4, (a0)
+ vlseg4e64.v v4, (a0)
+ vsseg4e64.v v4, (a0)
+ vlseg5e64.v v4, (a0)
+ vsseg5e64.v v4, (a0)
+ vlseg6e64.v v4, (a0)
+ vsseg6e64.v v4, (a0)
+ vlseg7e64.v v4, (a0)
+ vsseg7e64.v v4, (a0)
+ vlseg8e64.v v4, (a0)
+ vsseg8e64.v v4, (a0)
+
+ vlsseg2e8.v v4, (a0), a1
+ vssseg2e8.v v4, (a0), a1
+ vlsseg3e8.v v4, (a0), a1
+ vssseg3e8.v v4, (a0), a1
+ vlsseg4e8.v v4, (a0), a1
+ vssseg4e8.v v4, (a0), a1
+ vlsseg5e8.v v4, (a0), a1
+ vssseg5e8.v v4, (a0), a1
+ vlsseg6e8.v v4, (a0), a1
+ vssseg6e8.v v4, (a0), a1
+ vlsseg7e8.v v4, (a0), a1
+ vssseg7e8.v v4, (a0), a1
+ vlsseg8e8.v v4, (a0), a1
+ vssseg8e8.v v4, (a0), a1
+ vlsseg2e16.v v4, (a0), a1
+ vssseg2e16.v v4, (a0), a1
+ vlsseg3e16.v v4, (a0), a1
+ vssseg3e16.v v4, (a0), a1
+ vlsseg4e16.v v4, (a0), a1
+ vssseg4e16.v v4, (a0), a1
+ vlsseg5e16.v v4, (a0), a1
+ vssseg5e16.v v4, (a0), a1
+ vlsseg6e16.v v4, (a0), a1
+ vssseg6e16.v v4, (a0), a1
+ vlsseg7e16.v v4, (a0), a1
+ vssseg7e16.v v4, (a0), a1
+ vlsseg8e16.v v4, (a0), a1
+ vssseg8e16.v v4, (a0), a1
+ vlsseg2e32.v v4, (a0), a1
+ vssseg2e32.v v4, (a0), a1
+ vlsseg3e32.v v4, (a0), a1
+ vssseg3e32.v v4, (a0), a1
+ vlsseg4e32.v v4, (a0), a1
+ vssseg4e32.v v4, (a0), a1
+ vlsseg5e32.v v4, (a0), a1
+ vssseg5e32.v v4, (a0), a1
+ vlsseg6e32.v v4, (a0), a1
+ vssseg6e32.v v4, (a0), a1
+ vlsseg7e32.v v4, (a0), a1
+ vssseg7e32.v v4, (a0), a1
+ vlsseg8e32.v v4, (a0), a1
+ vssseg8e32.v v4, (a0), a1
+ vlsseg2e64.v v4, (a0), a1
+ vssseg2e64.v v4, (a0), a1
+ vlsseg3e64.v v4, (a0), a1
+ vssseg3e64.v v4, (a0), a1
+ vlsseg4e64.v v4, (a0), a1
+ vssseg4e64.v v4, (a0), a1
+ vlsseg5e64.v v4, (a0), a1
+ vssseg5e64.v v4, (a0), a1
+ vlsseg6e64.v v4, (a0), a1
+ vssseg6e64.v v4, (a0), a1
+ vlsseg7e64.v v4, (a0), a1
+ vssseg7e64.v v4, (a0), a1
+ vlsseg8e64.v v4, (a0), a1
+ vssseg8e64.v v4, (a0), a1
+
+ vloxseg2ei8.v v4, (a0), v12
+ vsoxseg2ei8.v v4, (a0), v12
+ vloxseg3ei8.v v4, (a0), v12
+ vsoxseg3ei8.v v4, (a0), v12
+ vloxseg4ei8.v v4, (a0), v12
+ vsoxseg4ei8.v v4, (a0), v12
+ vloxseg5ei8.v v4, (a0), v12
+ vsoxseg5ei8.v v4, (a0), v12
+ vloxseg6ei8.v v4, (a0), v12
+ vsoxseg6ei8.v v4, (a0), v12
+ vloxseg7ei8.v v4, (a0), v12
+ vsoxseg7ei8.v v4, (a0), v12
+ vloxseg8ei8.v v4, (a0), v12
+ vsoxseg8ei8.v v4, (a0), v12
+ vloxseg2ei16.v v4, (a0), v12
+ vsoxseg2ei16.v v4, (a0), v12
+ vloxseg3ei16.v v4, (a0), v12
+ vsoxseg3ei16.v v4, (a0), v12
+ vloxseg4ei16.v v4, (a0), v12
+ vsoxseg4ei16.v v4, (a0), v12
+ vloxseg5ei16.v v4, (a0), v12
+ vsoxseg5ei16.v v4, (a0), v12
+ vloxseg6ei16.v v4, (a0), v12
+ vsoxseg6ei16.v v4, (a0), v12
+ vloxseg7ei16.v v4, (a0), v12
+ vsoxseg7ei16.v v4, (a0), v12
+ vloxseg8ei16.v v4, (a0), v12
+ vsoxseg8ei16.v v4, (a0), v12
+ vloxseg2ei32.v v4, (a0), v12
+ vsoxseg2ei32.v v4, (a0), v12
+ vloxseg3ei32.v v4, (a0), v12
+ vsoxseg3ei32.v v4, (a0), v12
+ vloxseg4ei32.v v4, (a0), v12
+ vsoxseg4ei32.v v4, (a0), v12
+ vloxseg5ei32.v v4, (a0), v12
+ vsoxseg5ei32.v v4, (a0), v12
+ vloxseg6ei32.v v4, (a0), v12
+ vsoxseg6ei32.v v4, (a0), v12
+ vloxseg7ei32.v v4, (a0), v12
+ vsoxseg7ei32.v v4, (a0), v12
+ vloxseg8ei32.v v4, (a0), v12
+ vsoxseg8ei32.v v4, (a0), v12
+ vloxseg2ei64.v v4, (a0), v12
+ vsoxseg2ei64.v v4, (a0), v12
+ vloxseg3ei64.v v4, (a0), v12
+ vsoxseg3ei64.v v4, (a0), v12
+ vloxseg4ei64.v v4, (a0), v12
+ vsoxseg4ei64.v v4, (a0), v12
+ vloxseg5ei64.v v4, (a0), v12
+ vsoxseg5ei64.v v4, (a0), v12
+ vloxseg6ei64.v v4, (a0), v12
+ vsoxseg6ei64.v v4, (a0), v12
+ vloxseg7ei64.v v4, (a0), v12
+ vsoxseg7ei64.v v4, (a0), v12
+ vloxseg8ei64.v v4, (a0), v12
+ vsoxseg8ei64.v v4, (a0), v12
+
+ vluxseg2ei8.v v4, (a0), v12
+ vsuxseg2ei8.v v4, (a0), v12
+ vluxseg3ei8.v v4, (a0), v12
+ vsuxseg3ei8.v v4, (a0), v12
+ vluxseg4ei8.v v4, (a0), v12
+ vsuxseg4ei8.v v4, (a0), v12
+ vluxseg5ei8.v v4, (a0), v12
+ vsuxseg5ei8.v v4, (a0), v12
+ vluxseg6ei8.v v4, (a0), v12
+ vsuxseg6ei8.v v4, (a0), v12
+ vluxseg7ei8.v v4, (a0), v12
+ vsuxseg7ei8.v v4, (a0), v12
+ vluxseg8ei8.v v4, (a0), v12
+ vsuxseg8ei8.v v4, (a0), v12
+ vluxseg2ei16.v v4, (a0), v12
+ vsuxseg2ei16.v v4, (a0), v12
+ vluxseg3ei16.v v4, (a0), v12
+ vsuxseg3ei16.v v4, (a0), v12
+ vluxseg4ei16.v v4, (a0), v12
+ vsuxseg4ei16.v v4, (a0), v12
+ vluxseg5ei16.v v4, (a0), v12
+ vsuxseg5ei16.v v4, (a0), v12
+ vluxseg6ei16.v v4, (a0), v12
+ vsuxseg6ei16.v v4, (a0), v12
+ vluxseg7ei16.v v4, (a0), v12
+ vsuxseg7ei16.v v4, (a0), v12
+ vluxseg8ei16.v v4, (a0), v12
+ vsuxseg8ei16.v v4, (a0), v12
+ vluxseg2ei32.v v4, (a0), v12
+ vsuxseg2ei32.v v4, (a0), v12
+ vluxseg3ei32.v v4, (a0), v12
+ vsuxseg3ei32.v v4, (a0), v12
+ vluxseg4ei32.v v4, (a0), v12
+ vsuxseg4ei32.v v4, (a0), v12
+ vluxseg5ei32.v v4, (a0), v12
+ vsuxseg5ei32.v v4, (a0), v12
+ vluxseg6ei32.v v4, (a0), v12
+ vsuxseg6ei32.v v4, (a0), v12
+ vluxseg7ei32.v v4, (a0), v12
+ vsuxseg7ei32.v v4, (a0), v12
+ vluxseg8ei32.v v4, (a0), v12
+ vsuxseg8ei32.v v4, (a0), v12
+ vluxseg2ei64.v v4, (a0), v12
+ vsuxseg2ei64.v v4, (a0), v12
+ vluxseg3ei64.v v4, (a0), v12
+ vsuxseg3ei64.v v4, (a0), v12
+ vluxseg4ei64.v v4, (a0), v12
+ vsuxseg4ei64.v v4, (a0), v12
+ vluxseg5ei64.v v4, (a0), v12
+ vsuxseg5ei64.v v4, (a0), v12
+ vluxseg6ei64.v v4, (a0), v12
+ vsuxseg6ei64.v v4, (a0), v12
+ vluxseg7ei64.v v4, (a0), v12
+ vsuxseg7ei64.v v4, (a0), v12
+ vluxseg8ei64.v v4, (a0), v12
+ vsuxseg8ei64.v v4, (a0), v12
+
+ vlseg2e8ff.v v4, (a0)
+ vlseg3e8ff.v v4, (a0)
+ vlseg4e8ff.v v4, (a0)
+ vlseg5e8ff.v v4, (a0)
+ vlseg6e8ff.v v4, (a0)
+ vlseg7e8ff.v v4, (a0)
+ vlseg8e8ff.v v4, (a0)
+ vlseg2e16ff.v v4, (a0)
+ vlseg3e16ff.v v4, (a0)
+ vlseg4e16ff.v v4, (a0)
+ vlseg5e16ff.v v4, (a0)
+ vlseg6e16ff.v v4, (a0)
+ vlseg7e16ff.v v4, (a0)
+ vlseg8e16ff.v v4, (a0)
+ vlseg2e32ff.v v4, (a0)
+ vlseg3e32ff.v v4, (a0)
+ vlseg4e32ff.v v4, (a0)
+ vlseg5e32ff.v v4, (a0)
+ vlseg6e32ff.v v4, (a0)
+ vlseg7e32ff.v v4, (a0)
+ vlseg8e32ff.v v4, (a0)
+ vlseg2e64ff.v v4, (a0)
+ vlseg3e64ff.v v4, (a0)
+ vlseg4e64ff.v v4, (a0)
+ vlseg5e64ff.v v4, (a0)
+ vlseg6e64ff.v v4, (a0)
+ vlseg7e64ff.v v4, (a0)
+ vlseg8e64ff.v v4, (a0)
+
+ vl1r.v v3, (a0)
+ vl1re8.v v3, (a0)
+ vl1re16.v v3, (a0)
+ vl1re32.v v3, (a0)
+ vl1re64.v v3, (a0)
+ vl2r.v v2, (a0)
+ vl2re8.v v2, (a0)
+ vl2re16.v v2, (a0)
+ vl2re32.v v2, (a0)
+ vl2re64.v v2, (a0)
+ vl4r.v v4, (a0)
+ vl4re8.v v4, (a0)
+ vl4re16.v v4, (a0)
+ vl4re32.v v4, (a0)
+ vl4re64.v v4, (a0)
+ vl8r.v v8, (a0)
+ vl8re8.v v8, (a0)
+ vl8re16.v v8, (a0)
+ vl8re32.v v8, (a0)
+ vl8re64.v v8, (a0)
+
+ vs1r.v v3, (a1)
+ vs2r.v v2, (a1)
+ vs4r.v v4, (a1)
+ vs8r.v v8, (a1)
+
+ vamoaddei8.v v4, (a1), v8, v4
+ vamoswapei8.v v4, (a1), v8, v4
+ vamoxorei8.v v4, (a1), v8, v4
+ vamoandei8.v v4, (a1), v8, v4
+ vamoorei8.v v4, (a1), v8, v4
+ vamominei8.v v4, (a1), v8, v4
+ vamomaxei8.v v4, (a1), v8, v4
+ vamominuei8.v v4, (a1), v8, v4
+ vamomaxuei8.v v4, (a1), v8, v4
+ vamoaddei8.v v4, 0(a1), v8, v4
+ vamoswapei8.v v4, 0(a1), v8, v4
+ vamoxorei8.v v4, 0(a1), v8, v4
+ vamoandei8.v v4, 0(a1), v8, v4
+ vamoorei8.v v4, 0(a1), v8, v4
+ vamominei8.v v4, 0(a1), v8, v4
+ vamomaxei8.v v4, 0(a1), v8, v4
+ vamominuei8.v v4, 0(a1), v8, v4
+ vamomaxuei8.v v4, 0(a1), v8, v4
+
+ vamoaddei16.v v4, (a1), v8, v4
+ vamoswapei16.v v4, (a1), v8, v4
+ vamoxorei16.v v4, (a1), v8, v4
+ vamoandei16.v v4, (a1), v8, v4
+ vamoorei16.v v4, (a1), v8, v4
+ vamominei16.v v4, (a1), v8, v4
+ vamomaxei16.v v4, (a1), v8, v4
+ vamominuei16.v v4, (a1), v8, v4
+ vamomaxuei16.v v4, (a1), v8, v4
+ vamoaddei16.v v4, 0(a1), v8, v4
+ vamoswapei16.v v4, 0(a1), v8, v4
+ vamoxorei16.v v4, 0(a1), v8, v4
+ vamoandei16.v v4, 0(a1), v8, v4
+ vamoorei16.v v4, 0(a1), v8, v4
+ vamominei16.v v4, 0(a1), v8, v4
+ vamomaxei16.v v4, 0(a1), v8, v4
+ vamominuei16.v v4, 0(a1), v8, v4
+ vamomaxuei16.v v4, 0(a1), v8, v4
+
+ vamoaddei32.v v4, (a1), v8, v4
+ vamoswapei32.v v4, (a1), v8, v4
+ vamoxorei32.v v4, (a1), v8, v4
+ vamoandei32.v v4, (a1), v8, v4
+ vamoorei32.v v4, (a1), v8, v4
+ vamominei32.v v4, (a1), v8, v4
+ vamomaxei32.v v4, (a1), v8, v4
+ vamominuei32.v v4, (a1), v8, v4
+ vamomaxuei32.v v4, (a1), v8, v4
+ vamoaddei32.v v4, 0(a1), v8, v4
+ vamoswapei32.v v4, 0(a1), v8, v4
+ vamoxorei32.v v4, 0(a1), v8, v4
+ vamoandei32.v v4, 0(a1), v8, v4
+ vamoorei32.v v4, 0(a1), v8, v4
+ vamominei32.v v4, 0(a1), v8, v4
+ vamomaxei32.v v4, 0(a1), v8, v4
+ vamominuei32.v v4, 0(a1), v8, v4
+ vamomaxuei32.v v4, 0(a1), v8, v4
+
+ vamoaddei64.v v4, (a1), v8, v4
+ vamoswapei64.v v4, (a1), v8, v4
+ vamoxorei64.v v4, (a1), v8, v4
+ vamoandei64.v v4, (a1), v8, v4
+ vamoorei64.v v4, (a1), v8, v4
+ vamominei64.v v4, (a1), v8, v4
+ vamomaxei64.v v4, (a1), v8, v4
+ vamominuei64.v v4, (a1), v8, v4
+ vamomaxuei64.v v4, (a1), v8, v4
+ vamoaddei64.v v4, 0(a1), v8, v4
+ vamoswapei64.v v4, 0(a1), v8, v4
+ vamoxorei64.v v4, 0(a1), v8, v4
+ vamoandei64.v v4, 0(a1), v8, v4
+ vamoorei64.v v4, 0(a1), v8, v4
+ vamominei64.v v4, 0(a1), v8, v4
+ vamomaxei64.v v4, 0(a1), v8, v4
+ vamominuei64.v v4, 0(a1), v8, v4
+ vamomaxuei64.v v4, 0(a1), v8, v4
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.d
new file mode 100644
index 00000000000..16884e7e906
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_zvl65536b
+#source: ../empty.s
+#error_output: vector-insns-fail-zvl.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.l b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.l
new file mode 100644
index 00000000000..d820ded1e91
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*Error: zvl\*b extensions need to enable either `v' or `zve' extension
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.d b/gas/testsuite/gas/riscv/extended/vector-insns.d
index 4e0ffff368c..3f9b9a1de02 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns.d
+++ b/gas/testsuite/gas/riscv/extended/vector-insns.d
@@ -1,4 +1,4 @@
-#as: -march=rv32iafv_zvamo
+#as: -march=rv32ifv_zvamo
#objdump: -dr
.*:[ ]+file format .*
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 329bbc95ac9..25ef888bd63 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -445,6 +445,8 @@ extern const struct riscv_opcode riscv_insn_types[];
/* Extended extensions. */
+/* The insn_info fields. */
+#define INSN_V_EEW64 0x10000000
/* RVV IMM encodings. */
#define EXTRACT_RVV_VI_IMM(x) \
(RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 830b1bbf128..278b67326f3 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1321,47 +1321,47 @@ const struct riscv_opcode riscv_draft_opcodes[] =
{"vle8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_vd_neq_vm, INSN_DREF },
{"vle16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_vd_neq_vm, INSN_DREF },
{"vle32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_vd_neq_vm, INSN_DREF },
-{"vle64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_vd_neq_vm, INSN_DREF },
+{"vle64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
{"vse8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_vd_neq_vm, INSN_DREF },
{"vse16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_vd_neq_vm, INSN_DREF },
{"vse32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_vd_neq_vm, INSN_DREF },
-{"vse64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_vd_neq_vm, INSN_DREF },
+{"vse64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
{"vlse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_vd_neq_vm, INSN_DREF },
{"vlse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_vd_neq_vm, INSN_DREF },
{"vlse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_vd_neq_vm, INSN_DREF },
-{"vlse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_vd_neq_vm, INSN_DREF },
+{"vlse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
{"vsse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_vd_neq_vm, INSN_DREF },
{"vsse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_vd_neq_vm, INSN_DREF },
{"vsse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_vd_neq_vm, INSN_DREF },
-{"vsse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_vd_neq_vm, INSN_DREF },
+{"vsse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
{"vloxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI8V, MASK_VLOXEI8V, match_vd_neq_vm, INSN_DREF },
{"vloxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI16V, MASK_VLOXEI16V, match_vd_neq_vm, INSN_DREF },
{"vloxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI32V, MASK_VLOXEI32V, match_vd_neq_vm, INSN_DREF },
-{"vloxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_vd_neq_vm, INSN_DREF },
+{"vloxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
{"vsoxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI8V, MASK_VSOXEI8V, match_vd_neq_vm, INSN_DREF },
{"vsoxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI16V, MASK_VSOXEI16V, match_vd_neq_vm, INSN_DREF },
{"vsoxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_vd_neq_vm, INSN_DREF },
-{"vsoxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_vd_neq_vm, INSN_DREF },
+{"vsoxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
{"vluxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI8V, MASK_VLUXEI8V, match_vd_neq_vm, INSN_DREF },
{"vluxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI16V, MASK_VLUXEI16V, match_vd_neq_vm, INSN_DREF },
{"vluxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI32V, MASK_VLUXEI32V, match_vd_neq_vm, INSN_DREF },
-{"vluxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI64V, MASK_VLUXEI64V, match_vd_neq_vm, INSN_DREF },
+{"vluxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI64V, MASK_VLUXEI64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
{"vsuxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_vd_neq_vm, INSN_DREF },
{"vsuxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_vd_neq_vm, INSN_DREF },
{"vsuxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_vd_neq_vm, INSN_DREF },
-{"vsuxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_vd_neq_vm, INSN_DREF },
+{"vsuxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
{"vle8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_vd_neq_vm, INSN_DREF },
{"vle16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_vd_neq_vm, INSN_DREF },
{"vle32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_vd_neq_vm, INSN_DREF },
-{"vle64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_vd_neq_vm, INSN_DREF },
+{"vle64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
{"vlseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_vd_neq_vm, INSN_DREF },
{"vsseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_vd_neq_vm, INSN_DREF },
@@ -1408,20 +1408,20 @@ const struct riscv_opcode riscv_draft_opcodes[] =
{"vlseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_vd_neq_vm, INSN_DREF },
{"vsseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_vd_neq_vm, INSN_DREF },
-{"vlseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_vd_neq_vm, INSN_DREF },
-{"vsseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_vd_neq_vm, INSN_DREF },
-{"vlseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_vd_neq_vm, INSN_DREF },
-{"vsseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_vd_neq_vm, INSN_DREF },
-{"vlseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_vd_neq_vm, INSN_DREF },
-{"vsseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_vd_neq_vm, INSN_DREF },
-{"vlseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_vd_neq_vm, INSN_DREF },
-{"vsseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_vd_neq_vm, INSN_DREF },
-{"vlseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_vd_neq_vm, INSN_DREF },
-{"vsseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_vd_neq_vm, INSN_DREF },
-{"vlseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_vd_neq_vm, INSN_DREF },
-{"vsseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_vd_neq_vm, INSN_DREF },
-{"vlseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_vd_neq_vm, INSN_DREF },
-{"vsseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_vd_neq_vm, INSN_DREF },
+{"vlseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
{"vlsseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_vd_neq_vm, INSN_DREF },
{"vssseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_vd_neq_vm, INSN_DREF },
@@ -1468,20 +1468,20 @@ const struct riscv_opcode riscv_draft_opcodes[] =
{"vlsseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_vd_neq_vm, INSN_DREF },
{"vssseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_vd_neq_vm, INSN_DREF },
-{"vlsseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_vd_neq_vm, INSN_DREF },
-{"vssseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_vd_neq_vm, INSN_DREF },
-{"vlsseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_vd_neq_vm, INSN_DREF },
-{"vssseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_vd_neq_vm, INSN_DREF },
-{"vlsseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_vd_neq_vm, INSN_DREF },
-{"vssseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_vd_neq_vm, INSN_DREF },
-{"vlsseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_vd_neq_vm, INSN_DREF },
-{"vssseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_vd_neq_vm, INSN_DREF },
-{"vlsseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_vd_neq_vm, INSN_DREF },
-{"vssseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_vd_neq_vm, INSN_DREF },
-{"vlsseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_vd_neq_vm, INSN_DREF },
-{"vssseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_vd_neq_vm, INSN_DREF },
-{"vlsseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_vd_neq_vm, INSN_DREF },
-{"vssseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_vd_neq_vm, INSN_DREF },
+{"vlsseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vssseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlsseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vssseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlsseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vssseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlsseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vssseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlsseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vssseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlsseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vssseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlsseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vssseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
{"vloxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
{"vsoxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
@@ -1528,20 +1528,20 @@ const struct riscv_opcode riscv_draft_opcodes[] =
{"vloxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
{"vsoxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vloxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vsoxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vloxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vsoxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vloxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vsoxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vloxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vsoxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vloxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vsoxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vloxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vsoxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vloxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vsoxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+{"vloxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsoxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vloxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsoxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vloxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsoxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vloxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsoxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vloxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsoxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vloxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsoxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vloxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsoxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
{"vluxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI8V, MASK_VLUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
{"vsuxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI8V, MASK_VSUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
@@ -1588,20 +1588,20 @@ const struct riscv_opcode riscv_draft_opcodes[] =
{"vluxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI32V, MASK_VLUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
{"vsuxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI32V, MASK_VSUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vluxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V, MASK_VLUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vsuxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V, MASK_VSUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vluxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V, MASK_VLUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vsuxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V, MASK_VSUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vluxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V, MASK_VLUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vsuxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V, MASK_VSUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vluxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V, MASK_VLUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vsuxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V, MASK_VSUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vluxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V, MASK_VLUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vsuxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V, MASK_VSUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vluxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V, MASK_VLUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vsuxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V, MASK_VSUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vluxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V, MASK_VLUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
-{"vsuxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V, MASK_VSUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
+{"vluxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V, MASK_VLUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsuxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V, MASK_VSUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vluxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V, MASK_VLUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsuxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V, MASK_VSUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vluxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V, MASK_VLUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsuxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V, MASK_VSUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vluxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V, MASK_VLUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsuxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V, MASK_VSUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vluxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V, MASK_VLUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsuxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V, MASK_VSUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vluxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V, MASK_VLUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsuxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V, MASK_VSUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vluxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V, MASK_VLUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vsuxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V, MASK_VSUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF|INSN_V_EEW64 },
{"vlseg2e8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_vd_neq_vm, INSN_DREF },
{"vlseg3e8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_vd_neq_vm, INSN_DREF },
@@ -1627,37 +1627,37 @@ const struct riscv_opcode riscv_draft_opcodes[] =
{"vlseg7e32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_vd_neq_vm, INSN_DREF },
{"vlseg8e32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_vd_neq_vm, INSN_DREF },
-{"vlseg2e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_vd_neq_vm, INSN_DREF },
-{"vlseg3e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_vd_neq_vm, INSN_DREF },
-{"vlseg4e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_vd_neq_vm, INSN_DREF },
-{"vlseg5e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_vd_neq_vm, INSN_DREF },
-{"vlseg6e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_vd_neq_vm, INSN_DREF },
-{"vlseg7e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_vd_neq_vm, INSN_DREF },
-{"vlseg8e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_vd_neq_vm, INSN_DREF },
+{"vlseg2e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlseg3e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlseg4e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlseg5e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlseg6e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlseg7e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
+{"vlseg8e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_vd_neq_vm, INSN_DREF|INSN_V_EEW64 },
{"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
{"vl1re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF },
{"vl1re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_vls_nf_rv, INSN_DREF },
{"vl1re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_vls_nf_rv, INSN_DREF },
-{"vl1re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_vls_nf_rv, INSN_DREF },
+{"vl1re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_vls_nf_rv, INSN_DREF|INSN_V_EEW64 },
{"vl2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
{"vl2re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF },
{"vl2re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_vls_nf_rv, INSN_DREF },
{"vl2re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_vls_nf_rv, INSN_DREF },
-{"vl2re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_vls_nf_rv, INSN_DREF },
+{"vl2re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_vls_nf_rv, INSN_DREF|INSN_V_EEW64 },
{"vl4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
{"vl4re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF },
{"vl4re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_vls_nf_rv, INSN_DREF },
{"vl4re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_vls_nf_rv, INSN_DREF },
-{"vl4re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_vls_nf_rv, INSN_DREF },
+{"vl4re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_vls_nf_rv, INSN_DREF|INSN_V_EEW64 },
{"vl8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
{"vl8re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF },
{"vl8re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_vls_nf_rv, INSN_DREF },
{"vl8re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_vls_nf_rv, INSN_DREF },
-{"vl8re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_vls_nf_rv, INSN_DREF },
+{"vl8re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_vls_nf_rv, INSN_DREF|INSN_V_EEW64 },
{"vs1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_vls_nf_rv, INSN_DREF },
{"vs2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_vls_nf_rv, INSN_DREF },
--
2.30.2
next prev parent reply other threads:[~2021-10-05 12:51 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-05 12:51 [integration v2 0/4] RISC-V/rvv: Update rvv from v01.0 to v1.0 Nelson Chu
2021-10-05 12:51 ` [integration v2 1/4] RISC-V/rvv: Added assembly pseudo and changed assembler mnemonics Nelson Chu
2021-10-05 12:51 ` [integration v2 2/4] RISC-V/rvv: Update constraints for widening and narrowing instructions Nelson Chu
2021-10-05 12:51 ` [integration v2 3/4] RISC-V/rvv: Separate zvamo from v, and removed the zvlsseg extension name Nelson Chu
2021-10-05 12:51 ` Nelson Chu [this message]
2021-10-25 6:04 ` [integration v2 0/4] RISC-V/rvv: Update rvv from v01.0 to v1.0 Nelson Chu
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