From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: binutils@sourceware.org
Cc: Kito Cheng <kito.cheng@sifive.com>, Jim Wilson <jimw@sifive.com>,
Jan Beulich <jbeulich@suse.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH v3 4/4] RISC-V: Support aliases for Zbs instructions
Date: Wed, 6 Oct 2021 22:26:47 +0200 [thread overview]
Message-ID: <20211006202647.328777-4-philipp.tomsich@vrull.eu> (raw)
In-Reply-To: <20211006202647.328777-1-philipp.tomsich@vrull.eu>
Add aliases for the non-immediate mnemonics of b{set,clr,inv,ext} to
yencode the respective immediate insn b{set,clr,inv,ext}i when the
second source operand is an immediate.
2021-01-11 Philipp Tomsich <philipp.tomsich@vrull.eu>
gas/
* testsuite/gas/riscv/b-ext.d: Add tests.
* testsuite/gas/riscv/b-ext.s: Likewise.
* testsuite/gas/riscv/b-ext-64.d: Likewise.
* testsuite/gas/riscv/b-ext-64.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Add aliases for Zbs.
Suggested-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
(no changes since v2)
Changes in v2:
- Add aliases for the b{set,clr,inv,ext} when called with an immediate
as a second source operand.
gas/testsuite/gas/riscv/b-ext-64.d | 8 ++++++++
gas/testsuite/gas/riscv/b-ext-64.s | 9 +++++++++
gas/testsuite/gas/riscv/b-ext.d | 4 ++++
gas/testsuite/gas/riscv/b-ext.s | 5 +++++
opcodes/riscv-opc.c | 4 ++++
5 files changed, 30 insertions(+)
diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
index 339fa20a367..9b6e6b7ab2a 100644
--- a/gas/testsuite/gas/riscv/b-ext-64.d
+++ b/gas/testsuite/gas/riscv/b-ext-64.d
@@ -62,3 +62,11 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclri[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bseti[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binvi[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bexti[ ]+a0,a1,0x3f
diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
index 8ceb2b4fd1c..57e501e9a41 100644
--- a/gas/testsuite/gas/riscv/b-ext-64.s
+++ b/gas/testsuite/gas/riscv/b-ext-64.s
@@ -53,3 +53,12 @@ target:
bset a0, a1, a2
binv a0, a1, a2
bext a0, a1, a2
+ #aliases
+ bclr a0, a1, 31
+ bset a0, a1, 31
+ binv a0, a1, 31
+ bext a0, a1, 31
+ bclr a0, a1, 63
+ bset a0, a1, 63
+ binv a0, a1, 63
+ bext a0, a1, 63
diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
index 748c218fdd0..c1c5f918a84 100644
--- a/gas/testsuite/gas/riscv/b-ext.d
+++ b/gas/testsuite/gas/riscv/b-ext.d
@@ -45,3 +45,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f
diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
index a13a797f0dc..9de3fc32806 100644
--- a/gas/testsuite/gas/riscv/b-ext.s
+++ b/gas/testsuite/gas/riscv/b-ext.s
@@ -36,3 +36,8 @@ target:
bset a0, a1, a2
binv a0, a1, a2
bext a0, a1, a2
+ #aliases
+ bclr a0, a1, 31
+ bset a0, a1, 31
+ binv a0, a1, 31
+ bext a0, a1, 31
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 1a4c9f0e4fe..b756bae64ab 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -839,9 +839,13 @@ const struct riscv_opcode riscv_opcodes[] =
{"binvi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
{"bexti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
{"bclr", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
+{"bclr", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, INSN_ALIAS },
{"bset", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BSET, MASK_BSET, match_opcode, 0 },
+{"bset", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, INSN_ALIAS },
{"binv", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BINV, MASK_BINV, match_opcode, 0 },
+{"binv", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, INSN_ALIAS },
{"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
+{"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
/* Terminate the list. */
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
--
2.25.1
next prev parent reply other threads:[~2021-10-06 20:27 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-06 20:26 [PATCH v3 1/4] RISC-V: Split Zb[abc] into commented sections Philipp Tomsich
2021-10-06 20:26 ` [PATCH v3 2/4] RISC-V: Update extension version for Zb[abc] to 1.0.0 Philipp Tomsich
2021-10-07 4:02 ` Nelson Chu
2021-10-06 20:26 ` [PATCH v3 3/4] RISC-V: Add support for Zbs instructions Philipp Tomsich
2021-10-07 4:02 ` Nelson Chu
2021-10-07 6:57 ` Jan Beulich
2021-10-07 11:51 ` Delivery delayed:Re: " postmaster
2021-10-06 20:26 ` Philipp Tomsich [this message]
2021-10-07 4:05 ` [PATCH v3 4/4] RISC-V: Support aliases " Nelson Chu
2021-10-07 6:58 ` Jan Beulich
2021-10-07 9:13 ` Nelson Chu
2021-10-27 23:54 ` Vineet Gupta
2021-10-28 2:28 ` Nelson Chu
2021-10-28 3:24 ` Vineet Gupta
2021-10-28 8:08 ` Kito Cheng
2021-10-07 11:06 ` Delivery delayed:Re: " postmaster
2021-10-07 4:01 ` [PATCH v3 1/4] RISC-V: Split Zb[abc] into commented sections Nelson Chu
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