From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by sourceware.org (Postfix) with ESMTPS id 4BD163858430 for ; Fri, 29 Oct 2021 19:29:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4BD163858430 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pj1-x102e.google.com with SMTP id iq11so922992pjb.3 for ; Fri, 29 Oct 2021 12:29:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=TqIis6rCgtAiDDtj54m9vIqsFtSD2VCjlsnsAinJBug=; b=QVIygPwwFri0yeN5OSmrI9E44qGlByoJMQvGW1CYkENOuJCzwTqHfvAIJ+h1SuD8i3 rrCasD+pdTS1gylXcrCFeIf/QPc9vDEWkJmc8lOvdSl09H/wE+8exJGlTpcoNDJkCTPx tzwTzBOifQ1rm+jmPCgCkvgquJkUgo5w/fEMPBSWJnTBPbIsi3BhHgkuN4uJjNoXOe3k +OpxMls/Ihd2MZREBlzlR8MnLKp0yiB7lFf4pl9gufoSh2tCxou2fS8etcGDeaN6wdsB ABTyuVyMtFwLU6GeuVss6fNY8/4MZGGvStZgkMttI3MU8+vwLwCAi1JqdtIaT5ECimYl e6+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=TqIis6rCgtAiDDtj54m9vIqsFtSD2VCjlsnsAinJBug=; b=5fALzkGZ7+MFvD/Gh7pLEJoVTr6Pqx6aLOkQiT5vU8H6GlHwLrWYpoY9crk5LCSzHN jAjDUIUTsIdpu6XnGgIzaR7eO3KhfNO2Drt8k/HbTbTTzm0DMq1uu0wb/N33+943MFMc sFcswJyy8u/DHo5juSLM6BJLQScgAhjDHHAkRPkFD4rYXSX5vZNmsMmY1tAZ2GVP9pFe Tsw644woS05z31zXs4nPESpPNPT0W1Gzz8wADPYDY4oEiFHCN1flWfGTp37LIbfap0XS /Ru0rzAcN77C4IlEWiXGfzO6CxC7+NP8MUDNhqJfzVLNibKl3bMNgvE+WW4uJjam9ZwE 0g/Q== X-Gm-Message-State: AOAM53142noIilJ0wPTOSTLBFoiF2UkR75uYYyYkyzuMyUA+38OLA7Hp rtnjMe/KtVFyGs1ML8ctFehSjA== X-Google-Smtp-Source: ABdhPJwcHpYts2rIHVXPb4XN6/x4kAD0JqS2q5YqAfBXyJJ0nlMfJOhXFa0/t4IhqNxPn2ea2323wA== X-Received: by 2002:a17:902:e892:b0:141:5e96:8bfd with SMTP id w18-20020a170902e89200b001415e968bfdmr11591583plg.82.1635535739463; Fri, 29 Oct 2021 12:28:59 -0700 (PDT) Received: from vineetg-ThinkPad-X1-Carbon-Gen-9.ba.rivosinc.com (c-24-4-73-83.hsd1.ca.comcast.net. [24.4.73.83]) by smtp.gmail.com with ESMTPSA id t1sm7175420pfe.51.2021.10.29.12.28.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Oct 2021 12:28:59 -0700 (PDT) From: Vineet Gupta To: gdb-patches@sourceware.org, binutils@sourceware.org Cc: Nelson Chu , Kito Cheng , Jim Wilson , Mike Frysinger , Vineet Gupta , Dylan Reid Subject: [PATCH] sim: riscv: fix build breakage with rvv changes Date: Fri, 29 Oct 2021 12:28:56 -0700 Message-Id: <20211029192856.3987778-1-vineetg@rivosinc.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Oct 2021 19:29:02 -0000 changes to gas for riscv vector extensions need to be propagated to sim otherwise gdb fails to build on users/riscv/binutils-integration-branch This patch currently applies to that branch. Fixes: 144cceb058e "(RISC-V/rvv: Add rvv v0.10 instructions.)" Reported-by: Dylan Reid Signed-off-by: Vineet Gupta --- sim/riscv/ChangeLog-2021 | 4 ++++ sim/riscv/sim-main.c | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/sim/riscv/ChangeLog-2021 b/sim/riscv/ChangeLog-2021 index e9aa74490f12..9ced6773bdd6 100644 --- a/sim/riscv/ChangeLog-2021 +++ b/sim/riscv/ChangeLog-2021 @@ -1,3 +1,7 @@ +2021-20-28 Vineet Gupta + + * sim-main.c (step_once): Fix match_func call per gas changes. + 2021-07-01 Mike Frysinger * configure: Regenerate. diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 0faf9395ae52..9b4f7c6c5aad 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -956,6 +956,7 @@ void step_once (SIM_CPU *cpu) sim_cia pc = cpu->pc; const struct riscv_opcode *op; int xlen = RISCV_XLEN (cpu); + const char *error = NULL; if (TRACE_ANY_P (cpu)) trace_prefix (sd, cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu), @@ -985,7 +986,7 @@ void step_once (SIM_CPU *cpu) for (; op->name; op++) { /* Does the opcode match? */ - if (! op->match_func (op, iw)) + if (! op->match_func (op, iw, 0, /* check_constraints */ &error)) continue; /* Is this a pseudo-instruction and may we print it as such? */ if (op->pinfo & INSN_ALIAS) -- 2.30.2