* [PATCH 0/4] RISC-V: Support Scalar Cryptography extension
@ 2021-11-02 9:43 jiawei
2021-11-02 9:44 ` [PATCH 1/4] RISC-V: Fix order check when use 'z*' sub-extensions jiawei
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: jiawei @ 2021-11-02 9:43 UTC (permalink / raw)
To: binutils
Cc: kito.cheng, nelson.chu, jimw, mjos, ben.marshall, cmuellner,
palmer, andrew, lazyparser, siyu, jiawei
This patch is support Scalar Cryptography extension(k-ext v1.0.0-rc5) as
binutils part, you can find gcc patches part in https://github.com/WuSiYu/riscv-gcc/tree/trunk-crypto-rebase by siyu@isrc.iscas.ac.cn.
The first patch fix the order check with 'z' begin sub-extension, it set 'zb' before 'zk' as a right case. Some instruction in 'zbkb' and 'zbkc' is both used by Bitmanip and Scalar Cryptography extension, we just redefine the class with them.
Here is the github repo link contain this patch: https://github.com/pz9115/riscv-binutils-gdb/commits/k-ext-rebase, the old version of this work is form https://github.com/riscv-collab/riscv-binutils-gdb/pull/254, Thanks for Nelson Chu and Jim Wilson's review and help.
jiawei (4):
RISC-V: Fix order check when use 'z*' sub-extensions
RISC-V: Minimal support of scalar crypto extension
RISC-V: Scalar crypto instructions and operand set
RISC-V: Scalar crypto instruction and Entropy Source CSR testcases
bfd/elfxx-riscv.c | 29 ++++++-
gas/config/tc-riscv.c | 49 +++++++++++
gas/testsuite/gas/riscv/k-ext-64.d | 47 ++++++++++
gas/testsuite/gas/riscv/k-ext-64.s | 38 ++++++++
gas/testsuite/gas/riscv/k-ext.d | 44 ++++++++++
gas/testsuite/gas/riscv/k-ext.s | 35 ++++++++
.../gas/riscv/priv-reg-version-1p10.d | 1 +
.../gas/riscv/priv-reg-version-1p11.d | 1 +
.../gas/riscv/priv-reg-version-1p9p1.d | 1 +
gas/testsuite/gas/riscv/priv-reg.s | 4 +
include/opcode/riscv-opc.h | 75 ++++++++++++++++
include/opcode/riscv.h | 18 ++++
opcodes/riscv-dis.c | 8 ++
opcodes/riscv-opc.c | 87 +++++++++++++++----
14 files changed, 419 insertions(+), 18 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/k-ext-64.d
create mode 100644 gas/testsuite/gas/riscv/k-ext-64.s
create mode 100644 gas/testsuite/gas/riscv/k-ext.d
create mode 100644 gas/testsuite/gas/riscv/k-ext.s
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/4] RISC-V: Fix order check when use 'z*' sub-extensions
2021-11-02 9:43 [PATCH 0/4] RISC-V: Support Scalar Cryptography extension jiawei
@ 2021-11-02 9:44 ` jiawei
2021-11-02 10:38 ` Nelson Chu
2021-11-02 9:44 ` [PATCH 2/4] RISC-V: Minimal support of scalar crypto extension jiawei
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: jiawei @ 2021-11-02 9:44 UTC (permalink / raw)
To: binutils
Cc: kito.cheng, nelson.chu, jimw, mjos, ben.marshall, cmuellner,
palmer, andrew, lazyparser, siyu, jiawei
---
bfd/elfxx-riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index cdb4fa0996a..0d8fc755b5c 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1333,7 +1333,7 @@ riscv_compare_subsets (const char *subset1, const char *subset2)
order1 = riscv_ext_order[(*++subset1 - 'a')];
order2 = riscv_ext_order[(*++subset2 - 'a')];
if (order1 != order2)
- return order1 - order2;
+ return order2 - order1;
}
return strcasecmp (++subset1, ++subset2);
}
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/4] RISC-V: Minimal support of scalar crypto extension
2021-11-02 9:43 [PATCH 0/4] RISC-V: Support Scalar Cryptography extension jiawei
2021-11-02 9:44 ` [PATCH 1/4] RISC-V: Fix order check when use 'z*' sub-extensions jiawei
@ 2021-11-02 9:44 ` jiawei
2021-11-02 9:44 ` [PATCH 3/4] RISC-V: Scalar crypto instructions and operand set jiawei
2021-11-02 9:44 ` [PATCH 4/4] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases jiawei
3 siblings, 0 replies; 9+ messages in thread
From: jiawei @ 2021-11-02 9:44 UTC (permalink / raw)
To: binutils
Cc: kito.cheng, nelson.chu, jimw, mjos, ben.marshall, cmuellner,
palmer, andrew, lazyparser, siyu, jiawei
---
bfd/elfxx-riscv.c | 27 +++++++++++++++++++++++++++
gas/config/tc-riscv.c | 25 +++++++++++++++++++++++++
include/opcode/riscv.h | 11 +++++++++++
3 files changed, 63 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 0d8fc755b5c..049c26a42eb 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1075,6 +1075,20 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"q", "d", check_implicit_always},
{"d", "f", check_implicit_always},
{"f", "zicsr", check_implicit_always},
+ {"zk", "zkn", check_implicit_always},
+ {"zk", "zkr", check_implicit_always},
+ {"zk", "zkt", check_implicit_always},
+ {"zkn", "zbkb", check_implicit_always},
+ {"zkn", "zbkc", check_implicit_always},
+ {"zkn", "zbkx", check_implicit_always},
+ {"zkn", "zkne", check_implicit_always},
+ {"zkn", "zknd", check_implicit_always},
+ {"zkn", "zknh", check_implicit_always},
+ {"zks", "zbkb", check_implicit_always},
+ {"zks", "zbkc", check_implicit_always},
+ {"zks", "zbkx", check_implicit_always},
+ {"zks", "zksed", check_implicit_always},
+ {"zks", "zksh", check_implicit_always},
{NULL, NULL, NULL}
};
@@ -1146,6 +1160,19 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zbkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zbkc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zbkx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zk", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zknd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zkne", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zknh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zkr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zkt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
};
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index eb626f8e1d5..4e4dff419eb 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -301,6 +301,31 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
return riscv_subset_supports ("zbc");
case INSN_CLASS_ZBS:
return riscv_subset_supports ("zbs");
+ case INSN_CLASS_ZBKB:
+ return riscv_subset_supports ("zbkb");
+ case INSN_CLASS_ZBKC:
+ return riscv_subset_supports ("zbkc");
+ case INSN_CLASS_ZBKX:
+ return riscv_subset_supports ("zbkx");
+ case INSN_CLASS_ZBB_OR_ZBKB:
+ return (riscv_subset_supports ("zbb")
+ || riscv_subset_supports ("zbkb"));
+ case INSN_CLASS_ZBC_OR_ZBKC:
+ return (riscv_subset_supports ("zbc")
+ || riscv_subset_supports ("zbkc"));
+ case INSN_CLASS_ZKND:
+ return riscv_subset_supports ("zknd");
+ case INSN_CLASS_ZKNE:
+ return riscv_subset_supports ("zkne");
+ case INSN_CLASS_ZKNH:
+ return riscv_subset_supports ("zknh");
+ case INSN_CLASS_ZKND_OR_ZKNE:
+ return (riscv_subset_supports ("zknd")
+ || riscv_subset_supports ("zkne"));
+ case INSN_CLASS_ZKSED:
+ return riscv_subset_supports ("zksed");
+ case INSN_CLASS_ZKSH:
+ return riscv_subset_supports ("zksh");
default:
as_fatal ("internal: unreachable");
return false;
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index afcd41ff1dd..f61004bdf95 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -320,6 +320,17 @@ enum riscv_insn_class
INSN_CLASS_ZBB,
INSN_CLASS_ZBC,
INSN_CLASS_ZBS,
+ INSN_CLASS_ZBKB,
+ INSN_CLASS_ZBKC,
+ INSN_CLASS_ZBKX,
+ INSN_CLASS_ZKND,
+ INSN_CLASS_ZKNE,
+ INSN_CLASS_ZKNH,
+ INSN_CLASS_ZKSED,
+ INSN_CLASS_ZKSH,
+ INSN_CLASS_ZBB_OR_ZBKB,
+ INSN_CLASS_ZBC_OR_ZBKC,
+ INSN_CLASS_ZKND_OR_ZKNE,
};
/* This structure holds information for a particular instruction. */
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/4] RISC-V: Scalar crypto instructions and operand set
2021-11-02 9:43 [PATCH 0/4] RISC-V: Support Scalar Cryptography extension jiawei
2021-11-02 9:44 ` [PATCH 1/4] RISC-V: Fix order check when use 'z*' sub-extensions jiawei
2021-11-02 9:44 ` [PATCH 2/4] RISC-V: Minimal support of scalar crypto extension jiawei
@ 2021-11-02 9:44 ` jiawei
2021-11-02 9:44 ` [PATCH 4/4] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases jiawei
3 siblings, 0 replies; 9+ messages in thread
From: jiawei @ 2021-11-02 9:44 UTC (permalink / raw)
To: binutils
Cc: kito.cheng, nelson.chu, jimw, mjos, ben.marshall, cmuellner,
palmer, andrew, lazyparser, siyu, jiawei
---
gas/config/tc-riscv.c | 24 +++++++++++
include/opcode/riscv-opc.h | 75 ++++++++++++++++++++++++++++++++
include/opcode/riscv.h | 7 +++
opcodes/riscv-dis.c | 8 ++++
opcodes/riscv-opc.c | 87 ++++++++++++++++++++++++++++++--------
5 files changed, 184 insertions(+), 17 deletions(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 4e4dff419eb..a81a090ed52 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1183,6 +1183,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'I': break; /* Macro operand, must be constant. */
case 'D': /* RD, floating point. */
case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
+ case 'y': USE_BITS (OP_MASK_BS, OP_SH_BS); break;
+ case 'Y': USE_BITS (OP_MASK_RNUM, OP_SH_RNUM); break;
case 'Z': /* RS1, CSR number. */
case 'S': /* RS1, floating point. */
case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
@@ -2804,6 +2806,28 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
}
break;
+ case 'y': /* bs immediate */
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ if ((unsigned long)imm_expr->X_add_number > 3)
+ as_bad(_("Improper bs immediate (%lu)"),
+ (unsigned long)imm_expr->X_add_number);
+ INSERT_OPERAND(BS, *ip, imm_expr->X_add_number);
+ imm_expr->X_op = O_absent;
+ asarg = expr_end;
+ continue;
+
+ case 'Y': /* rcon immediate */
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ if ((unsigned long)imm_expr->X_add_number > 10)
+ as_bad(_("Improper rnum immediate (%lu)"),
+ (unsigned long)imm_expr->X_add_number);
+ INSERT_OPERAND(RNUM, *ip, imm_expr->X_add_number);
+ imm_expr->X_op = O_absent;
+ asarg = expr_end;
+ continue;
+
case 'z':
if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
|| imm_expr->X_op != O_constant
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 45a207da0cd..16a7cf243a9 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -443,6 +443,8 @@
#define MASK_SEXT_H 0xfff0707f
#define MATCH_PACK 0x8004033
#define MASK_PACK 0xfe00707f
+#define MATCH_PACKH 0x8007033
+#define MASK_PACKH 0xfe00707f
#define MATCH_PACKW 0x800403b
#define MASK_PACKW 0xfe00707f
#define MATCH_ANDN 0x40007033
@@ -461,6 +463,10 @@
#define MASK_GREVI 0xfc00707f
#define MATCH_GORCI 0x28005013
#define MASK_GORCI 0xfc00707f
+#define MATCH_SHFLI 0x8001013
+#define MASK_SHFLI 0xfc00707f
+#define MATCH_UNSHFLI 0x8005013
+#define MASK_UNSHFLI 0xfc00707f
#define MATCH_CLZW 0x6000101b
#define MASK_CLZW 0xfff0707f
#define MATCH_CTZW 0x6010101b
@@ -495,6 +501,10 @@
#define MASK_CLMULH 0xfe00707f
#define MATCH_CLMULR 0xa002033
#define MASK_CLMULR 0xfe00707f
+#define MATCH_XPERM4 0x28002033
+#define MASK_XPERM4 0xfe00707f
+#define MATCH_XPERM8 0x28004033
+#define MASK_XPERM8 0xfe00707f
#define MATCH_BCLRI 0x48001013
#define MASK_BCLRI 0xfc00707f
#define MATCH_BSETI 0x28001013
@@ -637,6 +647,64 @@
#define MASK_C_LDSP 0xe003
#define MATCH_C_SDSP 0xe002
#define MASK_C_SDSP 0xe003
+#define MATCH_SM3P0 0x10801013
+#define MASK_SM3P0 0xfff0707f
+#define MATCH_SM3P1 0x10901013
+#define MASK_SM3P1 0xfff0707f
+#define MATCH_SHA256SUM0 0x10001013
+#define MASK_SHA256SUM0 0xfff0707f
+#define MATCH_SHA256SUM1 0x10101013
+#define MASK_SHA256SUM1 0xfff0707f
+#define MATCH_SHA256SIG0 0x10201013
+#define MASK_SHA256SIG0 0xfff0707f
+#define MATCH_SHA256SIG1 0x10301013
+#define MASK_SHA256SIG1 0xfff0707f
+#define MATCH_SHA512SUM0R 0x50000033
+#define MASK_SHA512SUM0R 0xfe00707f
+#define MATCH_SHA512SUM1R 0x52000033
+#define MASK_SHA512SUM1R 0xfe00707f
+#define MATCH_SHA512SIG0L 0x54000033
+#define MASK_SHA512SIG0L 0xfe00707f
+#define MATCH_SHA512SIG0H 0x5c000033
+#define MASK_SHA512SIG0H 0xfe00707f
+#define MATCH_SHA512SIG1L 0x56000033
+#define MASK_SHA512SIG1L 0xfe00707f
+#define MATCH_SHA512SIG1H 0x5e000033
+#define MASK_SHA512SIG1H 0xfe00707f
+#define MATCH_SM4ED 0x30000033
+#define MASK_SM4ED 0x3e00707f
+#define MATCH_SM4KS 0x34000033
+#define MASK_SM4KS 0x3e00707f
+#define MATCH_AES32ESMI 0x26000033
+#define MASK_AES32ESMI 0x3e00707f
+#define MATCH_AES32ESI 0x22000033
+#define MASK_AES32ESI 0x3e00707f
+#define MATCH_AES32DSMI 0x2e000033
+#define MASK_AES32DSMI 0x3e00707f
+#define MATCH_AES32DSI 0x2a000033
+#define MASK_AES32DSI 0x3e00707f
+#define MATCH_SHA512SUM0 0x10401013
+#define MASK_SHA512SUM0 0xfff0707f
+#define MATCH_SHA512SUM1 0x10501013
+#define MASK_SHA512SUM1 0xfff0707f
+#define MATCH_SHA512SIG0 0x10601013
+#define MASK_SHA512SIG0 0xfff0707f
+#define MATCH_SHA512SIG1 0x10701013
+#define MASK_SHA512SIG1 0xfff0707f
+#define MATCH_AES64KS1I 0x31001013
+#define MASK_AES64KS1I 0xff00707f
+#define MATCH_AES64IM 0x30001013
+#define MASK_AES64IM 0xfff0707f
+#define MATCH_AES64KS2 0x7e000033
+#define MASK_AES64KS2 0xfe00707f
+#define MATCH_AES64ESM 0x36000033
+#define MASK_AES64ESM 0xfe00707f
+#define MATCH_AES64ES 0x32000033
+#define MASK_AES64ES 0xfe00707f
+#define MATCH_AES64DSM 0x3e000033
+#define MASK_AES64DSM 0xfe00707f
+#define MATCH_AES64DS 0x3a000033
+#define MASK_AES64DS 0xfe00707f
/* Privileged CSR addresses. */
#define CSR_USTATUS 0x0
#define CSR_UIE 0x4
@@ -884,6 +952,7 @@
#define CSR_TCONTROL 0x7a5
#define CSR_MCONTEXT 0x7a8
#define CSR_SCONTEXT 0x7aa
+#define CSR_SEED 0x015
#endif /* RISCV_ENCODING_H */
#ifdef DECLARE_INSN
DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
@@ -1118,6 +1187,11 @@ DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
+DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
+DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
+DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
+DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4)
+DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8)
DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
@@ -1436,6 +1510,7 @@ DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_C
DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(seed, CSR_SEED, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
#endif /* DECLARE_CSR */
#ifdef DECLARE_CSR_ALIAS
DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index f61004bdf95..1b5b7cb6ffc 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -261,6 +261,13 @@ static const char * const riscv_pred_succ[16] =
#define OP_MASK_CFUNCT2 0x3
#define OP_SH_CFUNCT2 5
+/* Scalar crypto fields. */
+
+#define OP_SH_BS 30
+#define OP_MASK_BS 3
+#define OP_SH_RNUM 20
+#define OP_MASK_RNUM 0xf
+
/* ABI names for selected x-registers. */
#define X_RA 1
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 1a094404fc5..9ef6e526690 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -362,6 +362,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, "%s", riscv_gpr_names[rd]);
break;
+ case 'y':
+ print (info->stream, "0x%x", (int)EXTRACT_OPERAND (BS, l));
+ break;
+
case 'z':
print (info->stream, "%s", riscv_gpr_names[0]);
break;
@@ -427,6 +431,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
break;
}
+ case 'Y':
+ print (info->stream, "0x%x", (int)EXTRACT_OPERAND (RNUM, l));
+ break;
+
case 'Z':
print (info->stream, "%d", rs1);
break;
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index b756bae64ab..a8f91e30b51 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -84,6 +84,9 @@ const char * const riscv_fpr_names_abi[NFPR] =
#define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
#define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
#define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
+#define MATCH_SHAMT_BREV8_32 (0b00111 << OP_SH_SHAMT)
+#define MATCH_SHAMT_BREV8_64 (0b000111 << OP_SH_SHAMT)
+#define MATCH_SHAMT_ZIP_32 (0b1111 << OP_SH_SHAMT)
#define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
static int
@@ -783,7 +786,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
-/* Zbb instructions */
+/* Zbb or zbkb instructions */
{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
{"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
@@ -798,23 +801,30 @@ const struct riscv_opcode riscv_opcodes[] =
{"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
{"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
-{"andn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
-{"orn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
-{"xnor", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
-{"rol", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
-{"rori", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
-{"ror", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
-{"ror", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
-{"rev8", 32, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
-{"rev8", 64, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
{"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_SHAMT_ORC_B, MASK_GORCI | MASK_SHAMT, match_opcode, 0 },
{"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
{"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
{"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
-{"rolw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
-{"roriw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
-{"rorw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
-{"rorw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
+{"brev8", 32, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
+{"brev8", 64, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
+{"zip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
+{"unzip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
+{"pack", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
+{"packh", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
+{"packw", 64, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
+{"andn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
+{"orn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
+{"xnor", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
+{"rol", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
+{"rori", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
+{"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
+{"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
+{"rev8", 32, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
+{"rev8", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
+{"rolw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
+{"roriw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
+{"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
+{"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
/* Zba instructions */
{"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
@@ -828,9 +838,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
{"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
-/* Zbc instructions */
-{"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
-{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
+/* Zbc or zbkc instructions */
+{"clmul", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
+{"clmulh", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
{"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
/* Zbs instructions */
@@ -847,6 +857,49 @@ const struct riscv_opcode riscv_opcodes[] =
{"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
{"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
+/* Zbkx instructions */
+{"xperm4", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM4, MASK_XPERM4, match_opcode, 0 },
+{"xperm8", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM8, MASK_XPERM8, match_opcode, 0 },
+
+/* Zknd instructions */
+{"aes32dsi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSI, MASK_AES32DSI, match_opcode, 0 },
+{"aes32dsmi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSMI, MASK_AES32DSMI, match_opcode, 0 },
+{"aes64ds", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DS, MASK_AES64DS, match_opcode, 0 },
+{"aes64dsm", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DSM, MASK_AES64DSM, match_opcode, 0 },
+{"aes64im", 64, INSN_CLASS_ZKND, "d,s", MATCH_AES64IM, MASK_AES64IM, match_opcode, 0 },
+{"aes64ks1i", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,Y", MATCH_AES64KS1I, MASK_AES64KS1I, match_opcode, 0 },
+{"aes64ks2", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,t", MATCH_AES64KS2, MASK_AES64KS2, match_opcode, 0 },
+
+/* Zkne instructions */
+{"aes32esi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESI, MASK_AES32ESI, match_opcode, 0 },
+{"aes32esmi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESMI, MASK_AES32ESMI, match_opcode, 0 },
+{"aes64es", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ES, MASK_AES64ES, match_opcode, 0 },
+{"aes64esm", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ESM, MASK_AES64ESM, match_opcode, 0 },
+
+/* Zknh instructions */
+{"sha256sig0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG0, MASK_SHA256SIG0, match_opcode, 0 },
+{"sha256sig1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG1, MASK_SHA256SIG1, match_opcode, 0 },
+{"sha256sum0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM0, MASK_SHA256SUM0, match_opcode, 0 },
+{"sha256sum1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM1, MASK_SHA256SUM1, match_opcode, 0 },
+{"sha512sig0h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0H, MASK_SHA512SIG0H, match_opcode, 0 },
+{"sha512sig0l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0L, MASK_SHA512SIG0L, match_opcode, 0 },
+{"sha512sig1h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1H, MASK_SHA512SIG1H, match_opcode, 0 },
+{"sha512sig1l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1L, MASK_SHA512SIG1L, match_opcode, 0 },
+{"sha512sum0r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM0R, MASK_SHA512SUM0R, match_opcode, 0 },
+{"sha512sum1r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM1R, MASK_SHA512SUM1R, match_opcode, 0 },
+{"sha512sig0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG0, MASK_SHA512SIG0, match_opcode, 0 },
+{"sha512sig1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG1, MASK_SHA512SIG1, match_opcode, 0 },
+{"sha512sum0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM0, MASK_SHA512SUM0, match_opcode, 0 },
+{"sha512sum1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM1, MASK_SHA512SUM1, match_opcode, 0 },
+
+/* Zksed instructions */
+{"sm4ed", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4ED, MASK_SM4ED, match_opcode, 0 },
+{"sm4ks", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4KS, MASK_SM4KS, match_opcode, 0 },
+
+/* Zksh instructions */
+{"sm3p0", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P0, MASK_SM3P0, match_opcode, 0 },
+{"sm3p1", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P1, MASK_SM3P1, match_opcode, 0 },
+
/* Terminate the list. */
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
};
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 4/4] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases
2021-11-02 9:43 [PATCH 0/4] RISC-V: Support Scalar Cryptography extension jiawei
` (2 preceding siblings ...)
2021-11-02 9:44 ` [PATCH 3/4] RISC-V: Scalar crypto instructions and operand set jiawei
@ 2021-11-02 9:44 ` jiawei
2021-11-02 9:54 ` Andreas Schwab
3 siblings, 1 reply; 9+ messages in thread
From: jiawei @ 2021-11-02 9:44 UTC (permalink / raw)
To: binutils
Cc: kito.cheng, nelson.chu, jimw, mjos, ben.marshall, cmuellner,
palmer, andrew, lazyparser, siyu, jiawei
---
gas/testsuite/gas/riscv/k-ext-64.d | 47 +++++++++++++++++++
gas/testsuite/gas/riscv/k-ext-64.s | 38 +++++++++++++++
gas/testsuite/gas/riscv/k-ext.d | 44 +++++++++++++++++
gas/testsuite/gas/riscv/k-ext.s | 35 ++++++++++++++
.../gas/riscv/priv-reg-version-1p10.d | 1 +
.../gas/riscv/priv-reg-version-1p11.d | 1 +
.../gas/riscv/priv-reg-version-1p9p1.d | 1 +
gas/testsuite/gas/riscv/priv-reg.s | 4 ++
8 files changed, 171 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/k-ext-64.d
create mode 100644 gas/testsuite/gas/riscv/k-ext-64.s
create mode 100644 gas/testsuite/gas/riscv/k-ext.d
create mode 100644 gas/testsuite/gas/riscv/k-ext.s
diff --git a/gas/testsuite/gas/riscv/k-ext-64.d b/gas/testsuite/gas/riscv/k-ext-64.d
new file mode 100644
index 00000000000..06f47566ac8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext-64.d
@@ -0,0 +1,47 @@
+#as: -march=rv64i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
+#source: k-ext-64.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
+[ ]+.*:[ ]+.*[ ]+rorw[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rolw[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+roriw[ ]+a0,a1,0x2
+[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+packw[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64ds[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64dsm[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64im[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+aes64ks1i[ ]+a0,a1,0x4
+[ ]+.*:[ ]+.*[ ]+aes64ks2[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64es[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64esm[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sig0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sig1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sum0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sum1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/k-ext-64.s b/gas/testsuite/gas/riscv/k-ext-64.s
new file mode 100644
index 00000000000..302b82ea005
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext-64.s
@@ -0,0 +1,38 @@
+target:
+ ror a0, a1, a2
+ rol a0, a1, a2
+ rori a0, a1, 2
+ rorw a0, a1, a2
+ rolw a0, a1, a2
+ roriw a0, a1, 2
+ andn a0, a1, a2
+ orn a0, a1, a2
+ xnor a0, a1, a2
+ pack a0, a1, a2
+ packh a0, a1, a2
+ packw a0, a1, a2
+ brev8 a0, a0
+ rev8 a0, a0
+ clmul a0, a1, a2
+ clmulh a0, a1, a2
+ xperm4 a0, a1, a2
+ xperm8 a0, a1, a2
+ aes64ds a0, a1, a2
+ aes64dsm a0, a1, a2
+ aes64im a0, a0
+ aes64ks1i a0, a1, 4
+ aes64ks2 a0, a1, a2
+ aes64es a0, a1, a2
+ aes64esm a0, a1, a2
+ sha256sig0 a0, a0
+ sha256sig1 a0, a0
+ sha256sum0 a0, a0
+ sha256sum1 a0, a0
+ sha512sig0 a0, a0
+ sha512sig1 a0, a0
+ sha512sum0 a0, a0
+ sha512sum1 a0, a0
+ sm4ed a0, a1, a2, 2
+ sm4ks a0, a1, a2, 2
+ sm3p0 a0, a0
+ sm3p1 a0, a0
diff --git a/gas/testsuite/gas/riscv/k-ext.d b/gas/testsuite/gas/riscv/k-ext.d
new file mode 100644
index 00000000000..3ba65aadc74
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext.d
@@ -0,0 +1,44 @@
+#as: -march=rv32i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
+#source: k-ext.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
+[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+zip[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+unzip[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes32dsi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+aes32dsmi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+aes32esi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+aes32esmi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sig0h[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sig0l[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sig1h[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sig1l[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sum0r[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sum1r[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/k-ext.s b/gas/testsuite/gas/riscv/k-ext.s
new file mode 100644
index 00000000000..8eb27684710
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext.s
@@ -0,0 +1,35 @@
+target:
+ ror a0, a1, a2
+ rol a0, a1, a2
+ rori a0, a1, 2
+ andn a0, a1, a2
+ orn a0, a1, a2
+ xnor a0, a1, a2
+ pack a0, a1, a2
+ packh a0, a1, a2
+ brev8 a0, a0
+ rev8 a0, a0
+ zip a0, a0
+ unzip a0, a0
+ clmul a0, a1, a2
+ clmulh a0, a1, a2
+ xperm4 a0, a1, a2
+ xperm8 a0, a1, a2
+ aes32dsi a0, a1, a2, 2
+ aes32dsmi a0, a1, a2, 2
+ aes32esi a0, a1, a2, 2
+ aes32esmi a0, a1, a2, 2
+ sha256sig0 a0, a0
+ sha256sig1 a0, a0
+ sha256sum0 a0, a0
+ sha256sum1 a0, a0
+ sha512sig0h a0, a1, a2
+ sha512sig0l a0, a1, a2
+ sha512sig1h a0, a1, a2
+ sha512sig1l a0, a1, a2
+ sha512sum0r a0, a1, a2
+ sha512sum1r a0, a1, a2
+ sm4ed a0, a1, a2, 2
+ sm4ks a0, a1, a2, 2
+ sm3p0 a0, a0
+ sm3p1 a0, a0
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
index 3ad8eebe851..78c683d3dea 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
@@ -265,3 +265,4 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
index 5824bc5e1f6..6c1cc70479b 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
@@ -265,3 +265,4 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
index 569b9587e29..3d2ab74eb35 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
@@ -265,3 +265,4 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed
diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
index c40d28862b7..23245a7301e 100644
--- a/gas/testsuite/gas/riscv/priv-reg.s
+++ b/gas/testsuite/gas/riscv/priv-reg.s
@@ -282,3 +282,7 @@
csr etrigger # 0x7a1, alias to tdata1
csr textra32 # 0x7a3, alias to tdata3
csr textra64 # 0x7a3, alias to tdata3
+
+ # Scalar crypto
+ csr seed # 0x015, Entropy Source
+
\ No newline at end of file
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 4/4] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases
2021-11-02 9:44 ` [PATCH 4/4] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases jiawei
@ 2021-11-02 9:54 ` Andreas Schwab
0 siblings, 0 replies; 9+ messages in thread
From: Andreas Schwab @ 2021-11-02 9:54 UTC (permalink / raw)
To: jiawei; +Cc: binutils, ben.marshall, mjos, siyu, cmuellner, kito.cheng
On Nov 02 2021, jiawei wrote:
> diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
> index c40d28862b7..23245a7301e 100644
> --- a/gas/testsuite/gas/riscv/priv-reg.s
> +++ b/gas/testsuite/gas/riscv/priv-reg.s
> @@ -282,3 +282,7 @@
> csr etrigger # 0x7a1, alias to tdata1
> csr textra32 # 0x7a3, alias to tdata3
> csr textra64 # 0x7a3, alias to tdata3
> +
> + # Scalar crypto
> + csr seed # 0x015, Entropy Source
> +
> \ No newline at end of file
Please remove the trailing spaces.
Andreas.
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] RISC-V: Fix order check when use 'z*' sub-extensions
2021-11-02 9:44 ` [PATCH 1/4] RISC-V: Fix order check when use 'z*' sub-extensions jiawei
@ 2021-11-02 10:38 ` Nelson Chu
2021-11-02 12:23 ` 陈嘉炜
0 siblings, 1 reply; 9+ messages in thread
From: Nelson Chu @ 2021-11-02 10:38 UTC (permalink / raw)
To: jiawei
Cc: Binutils, Kito Cheng, Jim Wilson, mjos, ben.marshall, cmuellner,
Palmer Dabbelt, Andrew Waterman, Wei Wu (吴伟),
siyu
Hi jiawei,
On Tue, Nov 2, 2021 at 5:44 PM jiawei <jiawei@iscas.ac.cn> wrote:
>
> ---
> bfd/elfxx-riscv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index cdb4fa0996a..0d8fc755b5c 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1333,7 +1333,7 @@ riscv_compare_subsets (const char *subset1, const char *subset2)
> order1 = riscv_ext_order[(*++subset1 - 'a')];
> order2 = riscv_ext_order[(*++subset2 - 'a')];
> if (order1 != order2)
> - return order1 - order2;
> + return order2 - order1;
> }
> return strcasecmp (++subset1, ++subset2);
> }
> --
> 2.25.1
>
After I apply this change, I get the unexpected results as follows,
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-linux64-upstream/build-install/bin/riscv64-unknown-linux-gnu-as
-misa-spec=20191213 -march=rv64i_zicsr_zifencei_zbb empty.s -o empty.o
Assembler messages:
Error: rv64i_zicsr_zifencei_zbb: prefixed ISA extension `zbb' is not
in expected order. It must come before `zifencei'
BTW, the expected result is as follows, before applying this patch,
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-linux64-upstream/build-install/bin/riscv64-unknown-linux-gnu-as
-misa-spec=20191213 -march=rv64i_zicsr_zifencei_zbb empty.s -o empty.o
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-linux64-upstream/build-install/bin/riscv64-unknown-linux-gnu-readelf
-A empty.o Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv64i2p1_zicsr2p0_zifencei2p0_zbb1p0"
Could I ask what issues or cases you want to resolve originally, so
that you need to change this?
Thanks
Nelson
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: Re: [PATCH 1/4] RISC-V: Fix order check when use 'z*' sub-extensions
2021-11-02 10:38 ` Nelson Chu
@ 2021-11-02 12:23 ` 陈嘉炜
2021-11-02 14:56 ` Nelson Chu
0 siblings, 1 reply; 9+ messages in thread
From: 陈嘉炜 @ 2021-11-02 12:23 UTC (permalink / raw)
To: Nelson Chu
Cc: Binutils, Kito Cheng, Jim Wilson, mjos, ben.marshall, cmuellner,
Palmer Dabbelt, Andrew Waterman, Wei Wu (吴伟),
siyu
Hi Nelson,
Thank you for the check, if we undo with this patch, here comes another unexpected results same as you mentioned:
riscv64-unknown-elf-as -misa-spec=20191213 -march=rv64i_zbb_zknd empty.s -o empty.o
Assembler messages:
Error: rv64i_zicsr_zifencei_zbb_zknd: prefixed ISA extension `zknd' is not in expected order. It must come before `zbb'
I think that zb* should goes before zk*, so I change the order at first patch to make 'zb' before 'zk'. Sorry for that I missed zicsr， zifencei and don't check it.
What should the right order if we have a string both contain 'zb', 'zk' even 'zp', 'zv' like -march=rv64i_zicsr_zifencei_zbb_zknd?
"Nelson Chu" <nelson.chu@sifive.com>写道：
> Hi jiawei,
>
> On Tue, Nov 2, 2021 at 5:44 PM jiawei <jiawei@iscas.ac.cn> wrote:
> >
> > ---
> > bfd/elfxx-riscv.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> > index cdb4fa0996a..0d8fc755b5c 100644
> > --- a/bfd/elfxx-riscv.c
> > +++ b/bfd/elfxx-riscv.c
> > @@ -1333,7 +1333,7 @@ riscv_compare_subsets (const char *subset1, const char *subset2)
> > order1 = riscv_ext_order[(*++subset1 - 'a')];
> > order2 = riscv_ext_order[(*++subset2 - 'a')];
> > if (order1 != order2)
> > - return order1 - order2;
> > + return order2 - order1;
> > }
> > return strcasecmp (++subset1, ++subset2);
> > }
> > --
> > 2.25.1
> >
>
> After I apply this change, I get the unexpected results as follows,
>
> nelson@LAPTOP-QFSGI1F2:~/test$
> ~/binutils-dev/build-linux64-upstream/build-install/bin/riscv64-unknown-linux-gnu-as
> -misa-spec=20191213 -march=rv64i_zicsr_zifencei_zbb empty.s -o empty.o
> Assembler messages:
> Error: rv64i_zicsr_zifencei_zbb: prefixed ISA extension `zbb' is not
> in expected order. It must come before `zifencei'
>
> BTW, the expected result is as follows, before applying this patch,
>
> nelson@LAPTOP-QFSGI1F2:~/test$
> ~/binutils-dev/build-linux64-upstream/build-install/bin/riscv64-unknown-linux-gnu-as
> -misa-spec=20191213 -march=rv64i_zicsr_zifencei_zbb empty.s -o empty.o
> nelson@LAPTOP-QFSGI1F2:~/test$
> ~/binutils-dev/build-linux64-upstream/build-install/bin/riscv64-unknown-linux-gnu-readelf
> -A empty.o Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: "rv64i2p1_zicsr2p0_zifencei2p0_zbb1p0"
>
> Could I ask what issues or cases you want to resolve originally, so
> that you need to change this?
>
> Thanks
> Nelson
</jiawei@iscas.ac.cn>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: Re: [PATCH 1/4] RISC-V: Fix order check when use 'z*' sub-extensions
2021-11-02 12:23 ` 陈嘉炜
@ 2021-11-02 14:56 ` Nelson Chu
0 siblings, 0 replies; 9+ messages in thread
From: Nelson Chu @ 2021-11-02 14:56 UTC (permalink / raw)
To: 陈嘉炜
Cc: Binutils, Kito Cheng, Jim Wilson, mjos, ben.marshall, cmuellner,
Palmer Dabbelt, Andrew Waterman, Wei Wu (吴伟),
siyu
On Tue, Nov 2, 2021 at 8:23 PM 陈嘉炜 <jiawei@iscas.ac.cn> wrote:
>
> Hi Nelson,
>
> Thank you for the check, if we undo with this patch, here comes another unexpected results same as you mentioned:
>
> riscv64-unknown-elf-as -misa-spec=20191213 -march=rv64i_zbb_zknd empty.s -o empty.o
> Assembler messages:
> Error: rv64i_zicsr_zifencei_zbb_zknd: prefixed ISA extension `zknd' is not in expected order. It must come before `zbb'
>
> I think that zb* should goes before zk*, so I change the order at first patch to make 'zb' before 'zk'. Sorry for that I missed zicsr， zifencei and don't check it.
>
> What should the right order if we have a string both contain 'zb', 'zk' even 'zp', 'zv' like -march=rv64i_zicsr_zifencei_zbb_zknd?
You can add the entry for k in the riscv_supported_std_ext, for example,
@@ -1127,6 +1127,7 @@ static struct riscv_supported_ext
riscv_supported_std_ext[] =
{"c", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"c", ISA_SPEC_CLASS_2P2, 2, 0, 0 },
{"b", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION,
RISCV_UNKNOWN_VERSION, 0 },
+ {"k", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION,
RISCV_UNKNOWN_VERSION, 0 },
{"j", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION,
RISCV_UNKNOWN_VERSION, 0 },
{"t", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION,
RISCV_UNKNOWN_VERSION, 0 },
{"p", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION,
RISCV_UNKNOWN_VERSION, 0 },
The standard extensions must be added in canonical order in the
riscv_supported_std_ext table, since I used to use this table to build
riscv_ext_order. So you could find a proper place to add the entry
for k extension.
> "Nelson Chu" <nelson.chu@sifive.com>写道：
> > Hi jiawei,
> >
> > On Tue, Nov 2, 2021 at 5:44 PM jiawei <jiawei@iscas.ac.cn> wrote:
> > >
> > > ---
> > > bfd/elfxx-riscv.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> > > index cdb4fa0996a..0d8fc755b5c 100644
> > > --- a/bfd/elfxx-riscv.c
> > > +++ b/bfd/elfxx-riscv.c
> > > @@ -1333,7 +1333,7 @@ riscv_compare_subsets (const char *subset1, const char *subset2)
> > > order1 = riscv_ext_order[(*++subset1 - 'a')];
> > > order2 = riscv_ext_order[(*++subset2 - 'a')];
> > > if (order1 != order2)
> > > - return order1 - order2;
> > > + return order2 - order1;
> > > }
> > > return strcasecmp (++subset1, ++subset2);
> > > }
> > > --
> > > 2.25.1
> > >
> >
> > After I apply this change, I get the unexpected results as follows,
> >
> > nelson@LAPTOP-QFSGI1F2:~/test$
> > ~/binutils-dev/build-linux64-upstream/build-install/bin/riscv64-unknown-linux-gnu-as
> > -misa-spec=20191213 -march=rv64i_zicsr_zifencei_zbb empty.s -o empty.o
> > Assembler messages:
> > Error: rv64i_zicsr_zifencei_zbb: prefixed ISA extension `zbb' is not
> > in expected order. It must come before `zifencei'
> >
> > BTW, the expected result is as follows, before applying this patch,
> >
> > nelson@LAPTOP-QFSGI1F2:~/test$
> > ~/binutils-dev/build-linux64-upstream/build-install/bin/riscv64-unknown-linux-gnu-as
> > -misa-spec=20191213 -march=rv64i_zicsr_zifencei_zbb empty.s -o empty.o
> > nelson@LAPTOP-QFSGI1F2:~/test$
> > ~/binutils-dev/build-linux64-upstream/build-install/bin/riscv64-unknown-linux-gnu-readelf
> > -A empty.o Attribute Section: riscv
> > File Attributes
> > Tag_RISCV_arch: "rv64i2p1_zicsr2p0_zifencei2p0_zbb1p0"
> >
> > Could I ask what issues or cases you want to resolve originally, so
> > that you need to change this?
> >
> > Thanks
> > Nelson
> </jiawei@iscas.ac.cn>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-11-03 18:00 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-02 9:43 [PATCH 0/4] RISC-V: Support Scalar Cryptography extension jiawei
2021-11-02 9:44 ` [PATCH 1/4] RISC-V: Fix order check when use 'z*' sub-extensions jiawei
2021-11-02 10:38 ` Nelson Chu
2021-11-02 12:23 ` 陈嘉炜
2021-11-02 14:56 ` Nelson Chu
2021-11-02 9:44 ` [PATCH 2/4] RISC-V: Minimal support of scalar crypto extension jiawei
2021-11-02 9:44 ` [PATCH 3/4] RISC-V: Scalar crypto instructions and operand set jiawei
2021-11-02 9:44 ` [PATCH 4/4] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases jiawei
2021-11-02 9:54 ` Andreas Schwab
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