* [PATCH v3 0/3] RISC-V: Support Scalar Cryptography extension
@ 2021-11-04 5:56 jiawei
2021-11-04 5:56 ` [PATCH v3 1/3] RISC-V: Minimal support of scalar crypto extension jiawei
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: jiawei @ 2021-11-04 5:56 UTC (permalink / raw)
To: binutils
Cc: kito.cheng, nelson.chu, jimw, philipp.tomsich, mjos,
ben.marshall, cmuellner, palmer, andrew, lazyparser, siyu,
schwab, jbeulich, jiawei
This patch is support Scalar Cryptography extension(k-ext v1.0.0-rc5) as
binutils part, you can find gcc patches part in https://github.com/WuSiYu/riscv-gcc/tree/trunk-crypto-rebase by siyu@isrc.iscas.ac.cn.
The first patch fix the order check with 'z' begin sub-extension, it set 'zb' before 'zk' as a right case. Some instruction in 'zbkb' and 'zbkc' is both used by Bitmanip and Scalar Cryptography extension, we just redefine the class with them.
Here is the github repo link contain this patch: https://github.com/pz9115/riscv-binutils-gdb/commits/k-ext-rebase, the old version of this work is form https://github.com/riscv-collab/riscv-binutils-gdb/pull/254, Thanks for Nelson Chu and Jim Wilson's review and help.
Version logs:
v2: Add missing arch "k" in riscv_supported_std_ext[] to make the order check right with "zk" behind "zb" as Neslon Chu's comment.
v3: Remove the trailing spaces as Andreas Schwab's comment. Add commit for each patch and add split testcases into sub-extension tests as Christoph Muellner's comment.
jiawei (3):
RISC-V: Minimal support of scalar crypto extension
RISC-V: Scalar crypto instructions and operand set
RISC-V: Scalar crypto instruction and Entropy Source CSR testcases
bfd/elfxx-riscv.c | 28 ++++++
gas/config/tc-riscv.c | 49 +++++++++++
gas/testsuite/gas/riscv/k-ext-64.d | 47 ++++++++++
gas/testsuite/gas/riscv/k-ext-64.s | 38 ++++++++
gas/testsuite/gas/riscv/k-ext.d | 44 ++++++++++
gas/testsuite/gas/riscv/k-ext.s | 35 ++++++++
.../gas/riscv/priv-reg-version-1p10.d | 1 +
.../gas/riscv/priv-reg-version-1p11.d | 1 +
.../gas/riscv/priv-reg-version-1p9p1.d | 1 +
gas/testsuite/gas/riscv/priv-reg.s | 3 +
gas/testsuite/gas/riscv/zbkb-32.d | 22 +++++
gas/testsuite/gas/riscv/zbkb-32.s | 13 +++
gas/testsuite/gas/riscv/zbkb-64.d | 24 +++++
gas/testsuite/gas/riscv/zbkb-64.s | 15 ++++
gas/testsuite/gas/riscv/zbkc-32.d | 12 +++
gas/testsuite/gas/riscv/zbkc-64.d | 12 +++
gas/testsuite/gas/riscv/zbkc.s | 3 +
gas/testsuite/gas/riscv/zbkx-32.d | 12 +++
gas/testsuite/gas/riscv/zbkx-64.d | 12 +++
gas/testsuite/gas/riscv/zbkx.s | 3 +
gas/testsuite/gas/riscv/zknd-32.d | 12 +++
gas/testsuite/gas/riscv/zknd-32.s | 3 +
gas/testsuite/gas/riscv/zknd-64.d | 15 ++++
gas/testsuite/gas/riscv/zknd-64.s | 6 ++
gas/testsuite/gas/riscv/zkne-32.d | 12 +++
gas/testsuite/gas/riscv/zkne-32.s | 3 +
gas/testsuite/gas/riscv/zkne-64.d | 14 +++
gas/testsuite/gas/riscv/zkne-64.s | 5 ++
gas/testsuite/gas/riscv/zknh-32.d | 20 +++++
gas/testsuite/gas/riscv/zknh-32.s | 11 +++
gas/testsuite/gas/riscv/zknh-64.d | 18 ++++
gas/testsuite/gas/riscv/zknh-64.s | 9 ++
gas/testsuite/gas/riscv/zksed-32.d | 12 +++
gas/testsuite/gas/riscv/zksed-64.d | 12 +++
gas/testsuite/gas/riscv/zksed.s | 3 +
gas/testsuite/gas/riscv/zksh-32.d | 12 +++
gas/testsuite/gas/riscv/zksh-64.d | 12 +++
gas/testsuite/gas/riscv/zksh.s | 3 +
include/opcode/riscv-opc.h | 75 ++++++++++++++++
include/opcode/riscv.h | 18 ++++
opcodes/riscv-dis.c | 8 ++
opcodes/riscv-opc.c | 87 +++++++++++++++----
42 files changed, 728 insertions(+), 17 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/k-ext-64.d
create mode 100644 gas/testsuite/gas/riscv/k-ext-64.s
create mode 100644 gas/testsuite/gas/riscv/k-ext.d
create mode 100644 gas/testsuite/gas/riscv/k-ext.s
create mode 100644 gas/testsuite/gas/riscv/zbkb-32.d
create mode 100644 gas/testsuite/gas/riscv/zbkb-32.s
create mode 100644 gas/testsuite/gas/riscv/zbkb-64.d
create mode 100644 gas/testsuite/gas/riscv/zbkb-64.s
create mode 100644 gas/testsuite/gas/riscv/zbkc-32.d
create mode 100644 gas/testsuite/gas/riscv/zbkc-64.d
create mode 100644 gas/testsuite/gas/riscv/zbkc.s
create mode 100644 gas/testsuite/gas/riscv/zbkx-32.d
create mode 100644 gas/testsuite/gas/riscv/zbkx-64.d
create mode 100644 gas/testsuite/gas/riscv/zbkx.s
create mode 100644 gas/testsuite/gas/riscv/zknd-32.d
create mode 100644 gas/testsuite/gas/riscv/zknd-32.s
create mode 100644 gas/testsuite/gas/riscv/zknd-64.d
create mode 100644 gas/testsuite/gas/riscv/zknd-64.s
create mode 100644 gas/testsuite/gas/riscv/zkne-32.d
create mode 100644 gas/testsuite/gas/riscv/zkne-32.s
create mode 100644 gas/testsuite/gas/riscv/zkne-64.d
create mode 100644 gas/testsuite/gas/riscv/zkne-64.s
create mode 100644 gas/testsuite/gas/riscv/zknh-32.d
create mode 100644 gas/testsuite/gas/riscv/zknh-32.s
create mode 100644 gas/testsuite/gas/riscv/zknh-64.d
create mode 100644 gas/testsuite/gas/riscv/zknh-64.s
create mode 100644 gas/testsuite/gas/riscv/zksed-32.d
create mode 100644 gas/testsuite/gas/riscv/zksed-64.d
create mode 100644 gas/testsuite/gas/riscv/zksed.s
create mode 100644 gas/testsuite/gas/riscv/zksh-32.d
create mode 100644 gas/testsuite/gas/riscv/zksh-64.d
create mode 100644 gas/testsuite/gas/riscv/zksh.s
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 1/3] RISC-V: Minimal support of scalar crypto extension
2021-11-04 5:56 [PATCH v3 0/3] RISC-V: Support Scalar Cryptography extension jiawei
@ 2021-11-04 5:56 ` jiawei
2021-11-10 2:38 ` Nelson Chu
2021-11-04 5:56 ` [PATCH v3 2/3] RISC-V: Scalar crypto instructions and operand set jiawei
2021-11-04 5:56 ` [PATCH v3 3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases jiawei
2 siblings, 1 reply; 7+ messages in thread
From: jiawei @ 2021-11-04 5:56 UTC (permalink / raw)
To: binutils
Cc: kito.cheng, nelson.chu, jimw, philipp.tomsich, mjos,
ben.marshall, cmuellner, palmer, andrew, lazyparser, siyu,
schwab, jbeulich, jiawei
Minimal support of scalar crypto extension, add "k" in riscv_supported_std_ext[] to make the order check right with "zk" behind "zb". "zbk*" is sub-extension for k-ext, so it added behind "zbs" in riscv_supported_std_z_ext[].
---
bfd/elfxx-riscv.c | 28 ++++++++++++++++++++++++++++
gas/config/tc-riscv.c | 25 +++++++++++++++++++++++++
include/opcode/riscv.h | 11 +++++++++++
3 files changed, 64 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index cdb4fa0996a..045b5a68a10 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1075,6 +1075,20 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"q", "d", check_implicit_always},
{"d", "f", check_implicit_always},
{"f", "zicsr", check_implicit_always},
+ {"zk", "zkn", check_implicit_always},
+ {"zk", "zkr", check_implicit_always},
+ {"zk", "zkt", check_implicit_always},
+ {"zkn", "zbkb", check_implicit_always},
+ {"zkn", "zbkc", check_implicit_always},
+ {"zkn", "zbkx", check_implicit_always},
+ {"zkn", "zkne", check_implicit_always},
+ {"zkn", "zknd", check_implicit_always},
+ {"zkn", "zknh", check_implicit_always},
+ {"zks", "zbkb", check_implicit_always},
+ {"zks", "zbkc", check_implicit_always},
+ {"zks", "zbkx", check_implicit_always},
+ {"zks", "zksed", check_implicit_always},
+ {"zks", "zksh", check_implicit_always},
{NULL, NULL, NULL}
};
@@ -1128,6 +1142,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
{"c", ISA_SPEC_CLASS_2P2, 2, 0, 0 },
{"b", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
{"j", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
+ {"k", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
{"t", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
{"p", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
{"v", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
@@ -1146,6 +1161,19 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zbkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zbkc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zbkx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zk", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zknd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zkne", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zknh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zkr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zkt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
};
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index eb626f8e1d5..5e7009b5696 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -301,6 +301,31 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
return riscv_subset_supports ("zbc");
case INSN_CLASS_ZBS:
return riscv_subset_supports ("zbs");
+ case INSN_CLASS_ZBKB:
+ return riscv_subset_supports ("zbkb");
+ case INSN_CLASS_ZBKC:
+ return riscv_subset_supports ("zbkc");
+ case INSN_CLASS_ZBKX:
+ return riscv_subset_supports ("zbkx");
+ case INSN_CLASS_ZBB_OR_ZBKB:
+ return (riscv_subset_supports ("zbb")
+ || riscv_subset_supports ("zbkb"));
+ case INSN_CLASS_ZBC_OR_ZBKC:
+ return (riscv_subset_supports ("zbc")
+ || riscv_subset_supports ("zbkc"));
+ case INSN_CLASS_ZKND:
+ return riscv_subset_supports ("zknd");
+ case INSN_CLASS_ZKNE:
+ return riscv_subset_supports ("zkne");
+ case INSN_CLASS_ZKNH:
+ return riscv_subset_supports ("zknh");
+ case INSN_CLASS_ZKND_OR_ZKNE:
+ return (riscv_subset_supports ("zknd")
+ || riscv_subset_supports ("zkne"));
+ case INSN_CLASS_ZKSED:
+ return riscv_subset_supports ("zksed");
+ case INSN_CLASS_ZKSH:
+ return riscv_subset_supports ("zksh");
default:
as_fatal ("internal: unreachable");
return false;
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index afcd41ff1dd..f61004bdf95 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -320,6 +320,17 @@ enum riscv_insn_class
INSN_CLASS_ZBB,
INSN_CLASS_ZBC,
INSN_CLASS_ZBS,
+ INSN_CLASS_ZBKB,
+ INSN_CLASS_ZBKC,
+ INSN_CLASS_ZBKX,
+ INSN_CLASS_ZKND,
+ INSN_CLASS_ZKNE,
+ INSN_CLASS_ZKNH,
+ INSN_CLASS_ZKSED,
+ INSN_CLASS_ZKSH,
+ INSN_CLASS_ZBB_OR_ZBKB,
+ INSN_CLASS_ZBC_OR_ZBKC,
+ INSN_CLASS_ZKND_OR_ZKNE,
};
/* This structure holds information for a particular instruction. */
--
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 2/3] RISC-V: Scalar crypto instructions and operand set
2021-11-04 5:56 [PATCH v3 0/3] RISC-V: Support Scalar Cryptography extension jiawei
2021-11-04 5:56 ` [PATCH v3 1/3] RISC-V: Minimal support of scalar crypto extension jiawei
@ 2021-11-04 5:56 ` jiawei
2021-11-10 9:26 ` Nelson Chu
2021-11-04 5:56 ` [PATCH v3 3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases jiawei
2 siblings, 1 reply; 7+ messages in thread
From: jiawei @ 2021-11-04 5:56 UTC (permalink / raw)
To: binutils
Cc: kito.cheng, nelson.chu, jimw, philipp.tomsich, mjos,
ben.marshall, cmuellner, palmer, andrew, lazyparser, siyu,
schwab, jbeulich, jiawei
Add instructions in k-ext, some instruction in zbkb, zbkc is reuse from zbb,zbc, we just change the class attribute to make them both support.
The 'aes64ks1i' and 'aes64ks2' instructions are present in both the Zknd and Zkne extensions on rv64.
Add new operand letter 'y' to present 'bs' symbol and 'Y' to present 'rnum' symbolc for zkn instructions.
Add new Entropy Source CSR define 'seed' located at address 0x015.
---
gas/config/tc-riscv.c | 24 +++++++++++
include/opcode/riscv-opc.h | 75 ++++++++++++++++++++++++++++++++
include/opcode/riscv.h | 7 +++
opcodes/riscv-dis.c | 8 ++++
opcodes/riscv-opc.c | 87 ++++++++++++++++++++++++++++++--------
5 files changed, 184 insertions(+), 17 deletions(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 5e7009b5696..2812432b8d6 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1183,6 +1183,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'I': break; /* Macro operand, must be constant. */
case 'D': /* RD, floating point. */
case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
+ case 'y': USE_BITS (OP_MASK_BS, OP_SH_BS); break;
+ case 'Y': USE_BITS (OP_MASK_RNUM, OP_SH_RNUM); break;
case 'Z': /* RS1, CSR number. */
case 'S': /* RS1, floating point. */
case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
@@ -2804,6 +2806,28 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
}
break;
+ case 'y': /* bs immediate */
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ if ((unsigned long)imm_expr->X_add_number > 3)
+ as_bad(_("Improper bs immediate (%lu)"),
+ (unsigned long)imm_expr->X_add_number);
+ INSERT_OPERAND(BS, *ip, imm_expr->X_add_number);
+ imm_expr->X_op = O_absent;
+ asarg = expr_end;
+ continue;
+
+ case 'Y': /* rcon immediate */
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ if ((unsigned long)imm_expr->X_add_number > 10)
+ as_bad(_("Improper rnum immediate (%lu)"),
+ (unsigned long)imm_expr->X_add_number);
+ INSERT_OPERAND(RNUM, *ip, imm_expr->X_add_number);
+ imm_expr->X_op = O_absent;
+ asarg = expr_end;
+ continue;
+
case 'z':
if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
|| imm_expr->X_op != O_constant
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 45a207da0cd..16a7cf243a9 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -443,6 +443,8 @@
#define MASK_SEXT_H 0xfff0707f
#define MATCH_PACK 0x8004033
#define MASK_PACK 0xfe00707f
+#define MATCH_PACKH 0x8007033
+#define MASK_PACKH 0xfe00707f
#define MATCH_PACKW 0x800403b
#define MASK_PACKW 0xfe00707f
#define MATCH_ANDN 0x40007033
@@ -461,6 +463,10 @@
#define MASK_GREVI 0xfc00707f
#define MATCH_GORCI 0x28005013
#define MASK_GORCI 0xfc00707f
+#define MATCH_SHFLI 0x8001013
+#define MASK_SHFLI 0xfc00707f
+#define MATCH_UNSHFLI 0x8005013
+#define MASK_UNSHFLI 0xfc00707f
#define MATCH_CLZW 0x6000101b
#define MASK_CLZW 0xfff0707f
#define MATCH_CTZW 0x6010101b
@@ -495,6 +501,10 @@
#define MASK_CLMULH 0xfe00707f
#define MATCH_CLMULR 0xa002033
#define MASK_CLMULR 0xfe00707f
+#define MATCH_XPERM4 0x28002033
+#define MASK_XPERM4 0xfe00707f
+#define MATCH_XPERM8 0x28004033
+#define MASK_XPERM8 0xfe00707f
#define MATCH_BCLRI 0x48001013
#define MASK_BCLRI 0xfc00707f
#define MATCH_BSETI 0x28001013
@@ -637,6 +647,64 @@
#define MASK_C_LDSP 0xe003
#define MATCH_C_SDSP 0xe002
#define MASK_C_SDSP 0xe003
+#define MATCH_SM3P0 0x10801013
+#define MASK_SM3P0 0xfff0707f
+#define MATCH_SM3P1 0x10901013
+#define MASK_SM3P1 0xfff0707f
+#define MATCH_SHA256SUM0 0x10001013
+#define MASK_SHA256SUM0 0xfff0707f
+#define MATCH_SHA256SUM1 0x10101013
+#define MASK_SHA256SUM1 0xfff0707f
+#define MATCH_SHA256SIG0 0x10201013
+#define MASK_SHA256SIG0 0xfff0707f
+#define MATCH_SHA256SIG1 0x10301013
+#define MASK_SHA256SIG1 0xfff0707f
+#define MATCH_SHA512SUM0R 0x50000033
+#define MASK_SHA512SUM0R 0xfe00707f
+#define MATCH_SHA512SUM1R 0x52000033
+#define MASK_SHA512SUM1R 0xfe00707f
+#define MATCH_SHA512SIG0L 0x54000033
+#define MASK_SHA512SIG0L 0xfe00707f
+#define MATCH_SHA512SIG0H 0x5c000033
+#define MASK_SHA512SIG0H 0xfe00707f
+#define MATCH_SHA512SIG1L 0x56000033
+#define MASK_SHA512SIG1L 0xfe00707f
+#define MATCH_SHA512SIG1H 0x5e000033
+#define MASK_SHA512SIG1H 0xfe00707f
+#define MATCH_SM4ED 0x30000033
+#define MASK_SM4ED 0x3e00707f
+#define MATCH_SM4KS 0x34000033
+#define MASK_SM4KS 0x3e00707f
+#define MATCH_AES32ESMI 0x26000033
+#define MASK_AES32ESMI 0x3e00707f
+#define MATCH_AES32ESI 0x22000033
+#define MASK_AES32ESI 0x3e00707f
+#define MATCH_AES32DSMI 0x2e000033
+#define MASK_AES32DSMI 0x3e00707f
+#define MATCH_AES32DSI 0x2a000033
+#define MASK_AES32DSI 0x3e00707f
+#define MATCH_SHA512SUM0 0x10401013
+#define MASK_SHA512SUM0 0xfff0707f
+#define MATCH_SHA512SUM1 0x10501013
+#define MASK_SHA512SUM1 0xfff0707f
+#define MATCH_SHA512SIG0 0x10601013
+#define MASK_SHA512SIG0 0xfff0707f
+#define MATCH_SHA512SIG1 0x10701013
+#define MASK_SHA512SIG1 0xfff0707f
+#define MATCH_AES64KS1I 0x31001013
+#define MASK_AES64KS1I 0xff00707f
+#define MATCH_AES64IM 0x30001013
+#define MASK_AES64IM 0xfff0707f
+#define MATCH_AES64KS2 0x7e000033
+#define MASK_AES64KS2 0xfe00707f
+#define MATCH_AES64ESM 0x36000033
+#define MASK_AES64ESM 0xfe00707f
+#define MATCH_AES64ES 0x32000033
+#define MASK_AES64ES 0xfe00707f
+#define MATCH_AES64DSM 0x3e000033
+#define MASK_AES64DSM 0xfe00707f
+#define MATCH_AES64DS 0x3a000033
+#define MASK_AES64DS 0xfe00707f
/* Privileged CSR addresses. */
#define CSR_USTATUS 0x0
#define CSR_UIE 0x4
@@ -884,6 +952,7 @@
#define CSR_TCONTROL 0x7a5
#define CSR_MCONTEXT 0x7a8
#define CSR_SCONTEXT 0x7aa
+#define CSR_SEED 0x015
#endif /* RISCV_ENCODING_H */
#ifdef DECLARE_INSN
DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
@@ -1118,6 +1187,11 @@ DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
+DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
+DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
+DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
+DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4)
+DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8)
DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
@@ -1436,6 +1510,7 @@ DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_C
DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(seed, CSR_SEED, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
#endif /* DECLARE_CSR */
#ifdef DECLARE_CSR_ALIAS
DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index f61004bdf95..1b5b7cb6ffc 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -261,6 +261,13 @@ static const char * const riscv_pred_succ[16] =
#define OP_MASK_CFUNCT2 0x3
#define OP_SH_CFUNCT2 5
+/* Scalar crypto fields. */
+
+#define OP_SH_BS 30
+#define OP_MASK_BS 3
+#define OP_SH_RNUM 20
+#define OP_MASK_RNUM 0xf
+
/* ABI names for selected x-registers. */
#define X_RA 1
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 1a094404fc5..9ef6e526690 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -362,6 +362,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, "%s", riscv_gpr_names[rd]);
break;
+ case 'y':
+ print (info->stream, "0x%x", (int)EXTRACT_OPERAND (BS, l));
+ break;
+
case 'z':
print (info->stream, "%s", riscv_gpr_names[0]);
break;
@@ -427,6 +431,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
break;
}
+ case 'Y':
+ print (info->stream, "0x%x", (int)EXTRACT_OPERAND (RNUM, l));
+ break;
+
case 'Z':
print (info->stream, "%d", rs1);
break;
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index b756bae64ab..a8f91e30b51 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -84,6 +84,9 @@ const char * const riscv_fpr_names_abi[NFPR] =
#define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
#define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
#define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
+#define MATCH_SHAMT_BREV8_32 (0b00111 << OP_SH_SHAMT)
+#define MATCH_SHAMT_BREV8_64 (0b000111 << OP_SH_SHAMT)
+#define MATCH_SHAMT_ZIP_32 (0b1111 << OP_SH_SHAMT)
#define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
static int
@@ -783,7 +786,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
-/* Zbb instructions */
+/* Zbb or zbkb instructions */
{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
{"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
@@ -798,23 +801,30 @@ const struct riscv_opcode riscv_opcodes[] =
{"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
{"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
-{"andn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
-{"orn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
-{"xnor", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
-{"rol", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
-{"rori", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
-{"ror", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
-{"ror", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
-{"rev8", 32, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
-{"rev8", 64, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
{"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_SHAMT_ORC_B, MASK_GORCI | MASK_SHAMT, match_opcode, 0 },
{"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
{"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
{"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
-{"rolw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
-{"roriw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
-{"rorw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
-{"rorw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
+{"brev8", 32, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
+{"brev8", 64, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
+{"zip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
+{"unzip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
+{"pack", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
+{"packh", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
+{"packw", 64, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
+{"andn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
+{"orn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
+{"xnor", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
+{"rol", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
+{"rori", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
+{"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
+{"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
+{"rev8", 32, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
+{"rev8", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
+{"rolw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
+{"roriw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
+{"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
+{"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
/* Zba instructions */
{"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
@@ -828,9 +838,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
{"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
-/* Zbc instructions */
-{"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
-{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
+/* Zbc or zbkc instructions */
+{"clmul", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
+{"clmulh", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
{"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
/* Zbs instructions */
@@ -847,6 +857,49 @@ const struct riscv_opcode riscv_opcodes[] =
{"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
{"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
+/* Zbkx instructions */
+{"xperm4", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM4, MASK_XPERM4, match_opcode, 0 },
+{"xperm8", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM8, MASK_XPERM8, match_opcode, 0 },
+
+/* Zknd instructions */
+{"aes32dsi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSI, MASK_AES32DSI, match_opcode, 0 },
+{"aes32dsmi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSMI, MASK_AES32DSMI, match_opcode, 0 },
+{"aes64ds", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DS, MASK_AES64DS, match_opcode, 0 },
+{"aes64dsm", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DSM, MASK_AES64DSM, match_opcode, 0 },
+{"aes64im", 64, INSN_CLASS_ZKND, "d,s", MATCH_AES64IM, MASK_AES64IM, match_opcode, 0 },
+{"aes64ks1i", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,Y", MATCH_AES64KS1I, MASK_AES64KS1I, match_opcode, 0 },
+{"aes64ks2", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,t", MATCH_AES64KS2, MASK_AES64KS2, match_opcode, 0 },
+
+/* Zkne instructions */
+{"aes32esi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESI, MASK_AES32ESI, match_opcode, 0 },
+{"aes32esmi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESMI, MASK_AES32ESMI, match_opcode, 0 },
+{"aes64es", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ES, MASK_AES64ES, match_opcode, 0 },
+{"aes64esm", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ESM, MASK_AES64ESM, match_opcode, 0 },
+
+/* Zknh instructions */
+{"sha256sig0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG0, MASK_SHA256SIG0, match_opcode, 0 },
+{"sha256sig1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG1, MASK_SHA256SIG1, match_opcode, 0 },
+{"sha256sum0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM0, MASK_SHA256SUM0, match_opcode, 0 },
+{"sha256sum1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM1, MASK_SHA256SUM1, match_opcode, 0 },
+{"sha512sig0h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0H, MASK_SHA512SIG0H, match_opcode, 0 },
+{"sha512sig0l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0L, MASK_SHA512SIG0L, match_opcode, 0 },
+{"sha512sig1h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1H, MASK_SHA512SIG1H, match_opcode, 0 },
+{"sha512sig1l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1L, MASK_SHA512SIG1L, match_opcode, 0 },
+{"sha512sum0r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM0R, MASK_SHA512SUM0R, match_opcode, 0 },
+{"sha512sum1r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM1R, MASK_SHA512SUM1R, match_opcode, 0 },
+{"sha512sig0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG0, MASK_SHA512SIG0, match_opcode, 0 },
+{"sha512sig1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG1, MASK_SHA512SIG1, match_opcode, 0 },
+{"sha512sum0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM0, MASK_SHA512SUM0, match_opcode, 0 },
+{"sha512sum1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM1, MASK_SHA512SUM1, match_opcode, 0 },
+
+/* Zksed instructions */
+{"sm4ed", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4ED, MASK_SM4ED, match_opcode, 0 },
+{"sm4ks", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4KS, MASK_SM4KS, match_opcode, 0 },
+
+/* Zksh instructions */
+{"sm3p0", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P0, MASK_SM3P0, match_opcode, 0 },
+{"sm3p1", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P1, MASK_SM3P1, match_opcode, 0 },
+
/* Terminate the list. */
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
};
--
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases
2021-11-04 5:56 [PATCH v3 0/3] RISC-V: Support Scalar Cryptography extension jiawei
2021-11-04 5:56 ` [PATCH v3 1/3] RISC-V: Minimal support of scalar crypto extension jiawei
2021-11-04 5:56 ` [PATCH v3 2/3] RISC-V: Scalar crypto instructions and operand set jiawei
@ 2021-11-04 5:56 ` jiawei
2 siblings, 0 replies; 7+ messages in thread
From: jiawei @ 2021-11-04 5:56 UTC (permalink / raw)
To: binutils
Cc: kito.cheng, nelson.chu, jimw, philipp.tomsich, mjos,
ben.marshall, cmuellner, palmer, andrew, lazyparser, siyu,
schwab, jbeulich, jiawei
Add testcases for Scalar Crypto extension, with total testcase contain all instructions in k-ext/k-ext-64 and sub-extension testcase for zbk* zk*. Also add testcase for new CSR name 'seed' which is the Entropy Source in zkr.
---
gas/testsuite/gas/riscv/k-ext-64.d | 47 +++++++++++++++++++
gas/testsuite/gas/riscv/k-ext-64.s | 38 +++++++++++++++
gas/testsuite/gas/riscv/k-ext.d | 44 +++++++++++++++++
gas/testsuite/gas/riscv/k-ext.s | 35 ++++++++++++++
.../gas/riscv/priv-reg-version-1p10.d | 1 +
.../gas/riscv/priv-reg-version-1p11.d | 1 +
.../gas/riscv/priv-reg-version-1p9p1.d | 1 +
gas/testsuite/gas/riscv/priv-reg.s | 3 ++
gas/testsuite/gas/riscv/zbkb-32.d | 22 +++++++++
gas/testsuite/gas/riscv/zbkb-32.s | 13 +++++
gas/testsuite/gas/riscv/zbkb-64.d | 24 ++++++++++
gas/testsuite/gas/riscv/zbkb-64.s | 15 ++++++
gas/testsuite/gas/riscv/zbkc-32.d | 12 +++++
gas/testsuite/gas/riscv/zbkc-64.d | 12 +++++
gas/testsuite/gas/riscv/zbkc.s | 3 ++
gas/testsuite/gas/riscv/zbkx-32.d | 12 +++++
gas/testsuite/gas/riscv/zbkx-64.d | 12 +++++
gas/testsuite/gas/riscv/zbkx.s | 3 ++
gas/testsuite/gas/riscv/zknd-32.d | 12 +++++
gas/testsuite/gas/riscv/zknd-32.s | 3 ++
gas/testsuite/gas/riscv/zknd-64.d | 15 ++++++
gas/testsuite/gas/riscv/zknd-64.s | 6 +++
gas/testsuite/gas/riscv/zkne-32.d | 12 +++++
gas/testsuite/gas/riscv/zkne-32.s | 3 ++
gas/testsuite/gas/riscv/zkne-64.d | 14 ++++++
gas/testsuite/gas/riscv/zkne-64.s | 5 ++
gas/testsuite/gas/riscv/zknh-32.d | 20 ++++++++
gas/testsuite/gas/riscv/zknh-32.s | 11 +++++
gas/testsuite/gas/riscv/zknh-64.d | 18 +++++++
gas/testsuite/gas/riscv/zknh-64.s | 9 ++++
gas/testsuite/gas/riscv/zksed-32.d | 12 +++++
gas/testsuite/gas/riscv/zksed-64.d | 12 +++++
gas/testsuite/gas/riscv/zksed.s | 3 ++
gas/testsuite/gas/riscv/zksh-32.d | 12 +++++
gas/testsuite/gas/riscv/zksh-64.d | 12 +++++
gas/testsuite/gas/riscv/zksh.s | 3 ++
36 files changed, 480 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/k-ext-64.d
create mode 100644 gas/testsuite/gas/riscv/k-ext-64.s
create mode 100644 gas/testsuite/gas/riscv/k-ext.d
create mode 100644 gas/testsuite/gas/riscv/k-ext.s
create mode 100644 gas/testsuite/gas/riscv/zbkb-32.d
create mode 100644 gas/testsuite/gas/riscv/zbkb-32.s
create mode 100644 gas/testsuite/gas/riscv/zbkb-64.d
create mode 100644 gas/testsuite/gas/riscv/zbkb-64.s
create mode 100644 gas/testsuite/gas/riscv/zbkc-32.d
create mode 100644 gas/testsuite/gas/riscv/zbkc-64.d
create mode 100644 gas/testsuite/gas/riscv/zbkc.s
create mode 100644 gas/testsuite/gas/riscv/zbkx-32.d
create mode 100644 gas/testsuite/gas/riscv/zbkx-64.d
create mode 100644 gas/testsuite/gas/riscv/zbkx.s
create mode 100644 gas/testsuite/gas/riscv/zknd-32.d
create mode 100644 gas/testsuite/gas/riscv/zknd-32.s
create mode 100644 gas/testsuite/gas/riscv/zknd-64.d
create mode 100644 gas/testsuite/gas/riscv/zknd-64.s
create mode 100644 gas/testsuite/gas/riscv/zkne-32.d
create mode 100644 gas/testsuite/gas/riscv/zkne-32.s
create mode 100644 gas/testsuite/gas/riscv/zkne-64.d
create mode 100644 gas/testsuite/gas/riscv/zkne-64.s
create mode 100644 gas/testsuite/gas/riscv/zknh-32.d
create mode 100644 gas/testsuite/gas/riscv/zknh-32.s
create mode 100644 gas/testsuite/gas/riscv/zknh-64.d
create mode 100644 gas/testsuite/gas/riscv/zknh-64.s
create mode 100644 gas/testsuite/gas/riscv/zksed-32.d
create mode 100644 gas/testsuite/gas/riscv/zksed-64.d
create mode 100644 gas/testsuite/gas/riscv/zksed.s
create mode 100644 gas/testsuite/gas/riscv/zksh-32.d
create mode 100644 gas/testsuite/gas/riscv/zksh-64.d
create mode 100644 gas/testsuite/gas/riscv/zksh.s
diff --git a/gas/testsuite/gas/riscv/k-ext-64.d b/gas/testsuite/gas/riscv/k-ext-64.d
new file mode 100644
index 00000000000..06f47566ac8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext-64.d
@@ -0,0 +1,47 @@
+#as: -march=rv64i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
+#source: k-ext-64.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
+[ ]+.*:[ ]+.*[ ]+rorw[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rolw[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+roriw[ ]+a0,a1,0x2
+[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+packw[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64ds[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64dsm[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64im[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+aes64ks1i[ ]+a0,a1,0x4
+[ ]+.*:[ ]+.*[ ]+aes64ks2[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64es[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64esm[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sig0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sig1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sum0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sum1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/k-ext-64.s b/gas/testsuite/gas/riscv/k-ext-64.s
new file mode 100644
index 00000000000..302b82ea005
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext-64.s
@@ -0,0 +1,38 @@
+target:
+ ror a0, a1, a2
+ rol a0, a1, a2
+ rori a0, a1, 2
+ rorw a0, a1, a2
+ rolw a0, a1, a2
+ roriw a0, a1, 2
+ andn a0, a1, a2
+ orn a0, a1, a2
+ xnor a0, a1, a2
+ pack a0, a1, a2
+ packh a0, a1, a2
+ packw a0, a1, a2
+ brev8 a0, a0
+ rev8 a0, a0
+ clmul a0, a1, a2
+ clmulh a0, a1, a2
+ xperm4 a0, a1, a2
+ xperm8 a0, a1, a2
+ aes64ds a0, a1, a2
+ aes64dsm a0, a1, a2
+ aes64im a0, a0
+ aes64ks1i a0, a1, 4
+ aes64ks2 a0, a1, a2
+ aes64es a0, a1, a2
+ aes64esm a0, a1, a2
+ sha256sig0 a0, a0
+ sha256sig1 a0, a0
+ sha256sum0 a0, a0
+ sha256sum1 a0, a0
+ sha512sig0 a0, a0
+ sha512sig1 a0, a0
+ sha512sum0 a0, a0
+ sha512sum1 a0, a0
+ sm4ed a0, a1, a2, 2
+ sm4ks a0, a1, a2, 2
+ sm3p0 a0, a0
+ sm3p1 a0, a0
diff --git a/gas/testsuite/gas/riscv/k-ext.d b/gas/testsuite/gas/riscv/k-ext.d
new file mode 100644
index 00000000000..3ba65aadc74
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext.d
@@ -0,0 +1,44 @@
+#as: -march=rv32i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
+#source: k-ext.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
+[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+zip[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+unzip[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes32dsi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+aes32dsmi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+aes32esi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+aes32esmi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sig0h[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sig0l[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sig1h[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sig1l[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sum0r[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sum1r[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/k-ext.s b/gas/testsuite/gas/riscv/k-ext.s
new file mode 100644
index 00000000000..8eb27684710
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext.s
@@ -0,0 +1,35 @@
+target:
+ ror a0, a1, a2
+ rol a0, a1, a2
+ rori a0, a1, 2
+ andn a0, a1, a2
+ orn a0, a1, a2
+ xnor a0, a1, a2
+ pack a0, a1, a2
+ packh a0, a1, a2
+ brev8 a0, a0
+ rev8 a0, a0
+ zip a0, a0
+ unzip a0, a0
+ clmul a0, a1, a2
+ clmulh a0, a1, a2
+ xperm4 a0, a1, a2
+ xperm8 a0, a1, a2
+ aes32dsi a0, a1, a2, 2
+ aes32dsmi a0, a1, a2, 2
+ aes32esi a0, a1, a2, 2
+ aes32esmi a0, a1, a2, 2
+ sha256sig0 a0, a0
+ sha256sig1 a0, a0
+ sha256sum0 a0, a0
+ sha256sum1 a0, a0
+ sha512sig0h a0, a1, a2
+ sha512sig0l a0, a1, a2
+ sha512sig1h a0, a1, a2
+ sha512sig1l a0, a1, a2
+ sha512sum0r a0, a1, a2
+ sha512sum1r a0, a1, a2
+ sm4ed a0, a1, a2, 2
+ sm4ks a0, a1, a2, 2
+ sm3p0 a0, a0
+ sm3p1 a0, a0
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
index 3ad8eebe851..78c683d3dea 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
@@ -265,3 +265,4 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
index 5824bc5e1f6..6c1cc70479b 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
@@ -265,3 +265,4 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
index 569b9587e29..3d2ab74eb35 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
@@ -265,3 +265,4 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed
diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
index c40d28862b7..85ff2a6f466 100644
--- a/gas/testsuite/gas/riscv/priv-reg.s
+++ b/gas/testsuite/gas/riscv/priv-reg.s
@@ -282,3 +282,6 @@
csr etrigger # 0x7a1, alias to tdata1
csr textra32 # 0x7a3, alias to tdata3
csr textra64 # 0x7a3, alias to tdata3
+
+ # Scalar crypto
+ csr seed # 0x015, Entropy Source
diff --git a/gas/testsuite/gas/riscv/zbkb-32.d b/gas/testsuite/gas/riscv/zbkb-32.d
new file mode 100644
index 00000000000..75a9259c5d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkb-32.d
@@ -0,0 +1,22 @@
+#as: -march=rv32i_zbkb
+#source: zbkb-32.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
+[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+zip[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+unzip[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zbkb-32.s b/gas/testsuite/gas/riscv/zbkb-32.s
new file mode 100644
index 00000000000..6f917154517
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkb-32.s
@@ -0,0 +1,13 @@
+target:
+ ror a0, a1, a2
+ rol a0, a1, a2
+ rori a0, a1, 2
+ andn a0, a1, a2
+ orn a0, a1, a2
+ xnor a0, a1, a2
+ pack a0, a1, a2
+ packh a0, a1, a2
+ brev8 a0, a0
+ rev8 a0, a0
+ zip a0, a0
+ unzip a0, a0
diff --git a/gas/testsuite/gas/riscv/zbkb-64.d b/gas/testsuite/gas/riscv/zbkb-64.d
new file mode 100644
index 00000000000..2f51db19f06
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkb-64.d
@@ -0,0 +1,24 @@
+#as: -march=rv64i_zbkb
+#source: zbkb-64.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
+[ ]+.*:[ ]+.*[ ]+rorw[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rolw[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+roriw[ ]+a0,a1,0x2
+[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+packw[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zbkb-64.s b/gas/testsuite/gas/riscv/zbkb-64.s
new file mode 100644
index 00000000000..b5cf79f890e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkb-64.s
@@ -0,0 +1,15 @@
+target:
+ ror a0, a1, a2
+ rol a0, a1, a2
+ rori a0, a1, 2
+ rorw a0, a1, a2
+ rolw a0, a1, a2
+ roriw a0, a1, 2
+ andn a0, a1, a2
+ orn a0, a1, a2
+ xnor a0, a1, a2
+ pack a0, a1, a2
+ packh a0, a1, a2
+ packw a0, a1, a2
+ brev8 a0, a0
+ rev8 a0, a0
diff --git a/gas/testsuite/gas/riscv/zbkc-32.d b/gas/testsuite/gas/riscv/zbkc-32.d
new file mode 100644
index 00000000000..7052f4be451
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkc-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zbkc
+#source: zbkc.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkc-64.d b/gas/testsuite/gas/riscv/zbkc-64.d
new file mode 100644
index 00000000000..1620ea9c8db
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkc-64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zbkc
+#source: zbkc.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkc.s b/gas/testsuite/gas/riscv/zbkc.s
new file mode 100644
index 00000000000..2a987746e7b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkc.s
@@ -0,0 +1,3 @@
+target:
+ clmul a0, a1, a2
+ clmulh a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zbkx-32.d b/gas/testsuite/gas/riscv/zbkx-32.d
new file mode 100644
index 00000000000..3306ab42e32
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkx-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zbkx
+#source: zbkx.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkx-64.d b/gas/testsuite/gas/riscv/zbkx-64.d
new file mode 100644
index 00000000000..95cca8e9049
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkx-64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zbkx
+#source: zbkx.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkx.s b/gas/testsuite/gas/riscv/zbkx.s
new file mode 100644
index 00000000000..8c3077105fe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkx.s
@@ -0,0 +1,3 @@
+target:
+ xperm4 a0, a1, a2
+ xperm8 a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zknd-32.d b/gas/testsuite/gas/riscv/zknd-32.d
new file mode 100644
index 00000000000..4571261e494
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknd-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zknd
+#source: zknd-32.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+aes32dsi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+aes32dsmi[ ]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zknd-32.s b/gas/testsuite/gas/riscv/zknd-32.s
new file mode 100644
index 00000000000..0d09badd1c6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknd-32.s
@@ -0,0 +1,3 @@
+target:
+ aes32dsi a0, a1, a2, 2
+ aes32dsmi a0, a1, a2, 2
diff --git a/gas/testsuite/gas/riscv/zknd-64.d b/gas/testsuite/gas/riscv/zknd-64.d
new file mode 100644
index 00000000000..e12b3ef204b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknd-64.d
@@ -0,0 +1,15 @@
+#as: -march=rv64i_zknd
+#source: zknd-64.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+aes64ds[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64dsm[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64im[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+aes64ks1i[ ]+a0,a1,0x4
+[ ]+.*:[ ]+.*[ ]+aes64ks2[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zknd-64.s b/gas/testsuite/gas/riscv/zknd-64.s
new file mode 100644
index 00000000000..4846e93c16f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknd-64.s
@@ -0,0 +1,6 @@
+target:
+ aes64ds a0, a1, a2
+ aes64dsm a0, a1, a2
+ aes64im a0, a0
+ aes64ks1i a0, a1, 4
+ aes64ks2 a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zkne-32.d b/gas/testsuite/gas/riscv/zkne-32.d
new file mode 100644
index 00000000000..2f5735971cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zkne-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zkne
+#source: zkne-32.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+aes32esi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+aes32esmi[ ]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zkne-32.s b/gas/testsuite/gas/riscv/zkne-32.s
new file mode 100644
index 00000000000..f864fc1778b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zkne-32.s
@@ -0,0 +1,3 @@
+target:
+ aes32esi a0, a1, a2, 2
+ aes32esmi a0, a1, a2, 2
diff --git a/gas/testsuite/gas/riscv/zkne-64.d b/gas/testsuite/gas/riscv/zkne-64.d
new file mode 100644
index 00000000000..6f6e9c31116
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zkne-64.d
@@ -0,0 +1,14 @@
+#as: -march=rv64i_zkne
+#source: zkne-64.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+aes64es[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64esm[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64ks1i[ ]+a0,a1,0x4
+[ ]+.*:[ ]+.*[ ]+aes64ks2[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zkne-64.s b/gas/testsuite/gas/riscv/zkne-64.s
new file mode 100644
index 00000000000..9b5612001af
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zkne-64.s
@@ -0,0 +1,5 @@
+target:
+ aes64es a0, a1, a2
+ aes64esm a0, a1, a2
+ aes64ks1i a0, a1, 4
+ aes64ks2 a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zknh-32.d b/gas/testsuite/gas/riscv/zknh-32.d
new file mode 100644
index 00000000000..ac4b2447629
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknh-32.d
@@ -0,0 +1,20 @@
+#as: -march=rv32i_zknh
+#source: zknh-32.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sig0h[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sig0l[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sig1h[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sig1l[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sum0r[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sum1r[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zknh-32.s b/gas/testsuite/gas/riscv/zknh-32.s
new file mode 100644
index 00000000000..dc2cd3c6657
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknh-32.s
@@ -0,0 +1,11 @@
+target:
+ sha256sig0 a0, a0
+ sha256sig1 a0, a0
+ sha256sum0 a0, a0
+ sha256sum1 a0, a0
+ sha512sig0h a0, a1, a2
+ sha512sig0l a0, a1, a2
+ sha512sig1h a0, a1, a2
+ sha512sig1l a0, a1, a2
+ sha512sum0r a0, a1, a2
+ sha512sum1r a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zknh-64.d b/gas/testsuite/gas/riscv/zknh-64.d
new file mode 100644
index 00000000000..890d5d826f3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknh-64.d
@@ -0,0 +1,18 @@
+#as: -march=rv64i_zknh
+#source: zknh-64.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sig0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sig1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sum0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sum1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zknh-64.s b/gas/testsuite/gas/riscv/zknh-64.s
new file mode 100644
index 00000000000..897dc0ba32e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknh-64.s
@@ -0,0 +1,9 @@
+target:
+ sha256sig0 a0, a0
+ sha256sig1 a0, a0
+ sha256sum0 a0, a0
+ sha256sum1 a0, a0
+ sha512sig0 a0, a0
+ sha512sig1 a0, a0
+ sha512sum0 a0, a0
+ sha512sum1 a0, a0
diff --git a/gas/testsuite/gas/riscv/zksed-32.d b/gas/testsuite/gas/riscv/zksed-32.d
new file mode 100644
index 00000000000..228130ae4c1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksed-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zksed
+#source: zksed.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zksed-64.d b/gas/testsuite/gas/riscv/zksed-64.d
new file mode 100644
index 00000000000..9a4efdff649
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksed-64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zksed
+#source: zksed.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zksed.s b/gas/testsuite/gas/riscv/zksed.s
new file mode 100644
index 00000000000..ee95c7a8584
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksed.s
@@ -0,0 +1,3 @@
+target:
+ sm4ed a0, a1, a2, 2
+ sm4ks a0, a1, a2, 2
diff --git a/gas/testsuite/gas/riscv/zksh-32.d b/gas/testsuite/gas/riscv/zksh-32.d
new file mode 100644
index 00000000000..ab22b3f1f4f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksh-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zksh
+#source: zksh.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zksh-64.d b/gas/testsuite/gas/riscv/zksh-64.d
new file mode 100644
index 00000000000..91a3f16e511
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksh-64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zksh
+#source: zksh.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zksh.s b/gas/testsuite/gas/riscv/zksh.s
new file mode 100644
index 00000000000..b321c26f2b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksh.s
@@ -0,0 +1,3 @@
+target:
+ sm3p0 a0, a0
+ sm3p1 a0, a0
--
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 1/3] RISC-V: Minimal support of scalar crypto extension
2021-11-04 5:56 ` [PATCH v3 1/3] RISC-V: Minimal support of scalar crypto extension jiawei
@ 2021-11-10 2:38 ` Nelson Chu
0 siblings, 0 replies; 7+ messages in thread
From: Nelson Chu @ 2021-11-10 2:38 UTC (permalink / raw)
To: jiawei
Cc: Binutils, Kito Cheng, Jim Wilson, Philipp Tomsich, mjos,
ben.marshall, cmuellner, Palmer Dabbelt, Andrew Waterman,
Wei Wu (吴伟),
siyu, Andreas Schwab, Jan Beulich
On Thu, Nov 4, 2021 at 1:56 PM jiawei <jiawei@iscas.ac.cn> wrote:
>
> Minimal support of scalar crypto extension, add "k" in riscv_supported_std_ext[] to make the order check right with "zk" behind "zb". "zbk*" is sub-extension for k-ext, so it added behind "zbs" in riscv_supported_std_z_ext[].
> ---
> bfd/elfxx-riscv.c | 28 ++++++++++++++++++++++++++++
> gas/config/tc-riscv.c | 25 +++++++++++++++++++++++++
> include/opcode/riscv.h | 11 +++++++++++
> 3 files changed, 64 insertions(+)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index cdb4fa0996a..045b5a68a10 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1075,6 +1075,20 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
> {"q", "d", check_implicit_always},
> {"d", "f", check_implicit_always},
> {"f", "zicsr", check_implicit_always},
> + {"zk", "zkn", check_implicit_always},
> + {"zk", "zkr", check_implicit_always},
> + {"zk", "zkt", check_implicit_always},
> + {"zkn", "zbkb", check_implicit_always},
> + {"zkn", "zbkc", check_implicit_always},
> + {"zkn", "zbkx", check_implicit_always},
> + {"zkn", "zkne", check_implicit_always},
> + {"zkn", "zknd", check_implicit_always},
> + {"zkn", "zknh", check_implicit_always},
> + {"zks", "zbkb", check_implicit_always},
> + {"zks", "zbkc", check_implicit_always},
> + {"zks", "zbkx", check_implicit_always},
> + {"zks", "zksed", check_implicit_always},
> + {"zks", "zksh", check_implicit_always},
> {NULL, NULL, NULL}
> };
>
> @@ -1128,6 +1142,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
> {"c", ISA_SPEC_CLASS_2P2, 2, 0, 0 },
> {"b", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
> {"j", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
> + {"k", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
> {"t", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
> {"p", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
> {"v", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
After checking the table 27.1 (Standard ISA extension names...) in the
riscv ISA spec, I think the k extension should be placed after b, and
before j extension.
> @@ -1146,6 +1161,19 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
> {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zbkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zbkc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zbkx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zk", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zknd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zkne", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zknh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zkr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zkt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {NULL, 0, 0, 0, 0}
> };
>
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index eb626f8e1d5..5e7009b5696 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -301,6 +301,31 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
> return riscv_subset_supports ("zbc");
> case INSN_CLASS_ZBS:
> return riscv_subset_supports ("zbs");
> + case INSN_CLASS_ZBKB:
> + return riscv_subset_supports ("zbkb");
> + case INSN_CLASS_ZBKC:
> + return riscv_subset_supports ("zbkc");
> + case INSN_CLASS_ZBKX:
> + return riscv_subset_supports ("zbkx");
> + case INSN_CLASS_ZBB_OR_ZBKB:
> + return (riscv_subset_supports ("zbb")
> + || riscv_subset_supports ("zbkb"));
> + case INSN_CLASS_ZBC_OR_ZBKC:
> + return (riscv_subset_supports ("zbc")
> + || riscv_subset_supports ("zbkc"));
> + case INSN_CLASS_ZKND:
> + return riscv_subset_supports ("zknd");
> + case INSN_CLASS_ZKNE:
> + return riscv_subset_supports ("zkne");
> + case INSN_CLASS_ZKNH:
> + return riscv_subset_supports ("zknh");
> + case INSN_CLASS_ZKND_OR_ZKNE:
> + return (riscv_subset_supports ("zknd")
> + || riscv_subset_supports ("zkne"));
> + case INSN_CLASS_ZKSED:
> + return riscv_subset_supports ("zksed");
> + case INSN_CLASS_ZKSH:
> + return riscv_subset_supports ("zksh");
> default:
> as_fatal ("internal: unreachable");
> return false;
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index afcd41ff1dd..f61004bdf95 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -320,6 +320,17 @@ enum riscv_insn_class
> INSN_CLASS_ZBB,
> INSN_CLASS_ZBC,
> INSN_CLASS_ZBS,
> + INSN_CLASS_ZBKB,
> + INSN_CLASS_ZBKC,
> + INSN_CLASS_ZBKX,
> + INSN_CLASS_ZKND,
> + INSN_CLASS_ZKNE,
> + INSN_CLASS_ZKNH,
> + INSN_CLASS_ZKSED,
> + INSN_CLASS_ZKSH,
> + INSN_CLASS_ZBB_OR_ZBKB,
> + INSN_CLASS_ZBC_OR_ZBKC,
> + INSN_CLASS_ZKND_OR_ZKNE,
> };
>
> /* This structure holds information for a particular instruction. */
> --
Likewise, the INSN_CLASS* classes can be moved to the later patches,
so this patch can focus on the architecture string parser support.
Except for the above comments, this patch looks good to me.
Thanks
Nelson
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 2/3] RISC-V: Scalar crypto instructions and operand set
2021-11-04 5:56 ` [PATCH v3 2/3] RISC-V: Scalar crypto instructions and operand set jiawei
@ 2021-11-10 9:26 ` Nelson Chu
2021-11-11 3:30 ` 陈嘉炜
0 siblings, 1 reply; 7+ messages in thread
From: Nelson Chu @ 2021-11-10 9:26 UTC (permalink / raw)
To: jiawei
Cc: Binutils, Kito Cheng, Jim Wilson, Philipp Tomsich, mjos,
ben.marshall, cmuellner, Palmer Dabbelt, Andrew Waterman,
Wei Wu (吴伟),
siyu, Andreas Schwab, Jan Beulich
On Thu, Nov 4, 2021 at 1:56 PM jiawei <jiawei@iscas.ac.cn> wrote:
>
> Add instructions in k-ext, some instruction in zbkb, zbkc is reuse from zbb,zbc, we just change the class attribute to make them both support.
>
> The 'aes64ks1i' and 'aes64ks2' instructions are present in both the Zknd and Zkne extensions on rv64.
>
> Add new operand letter 'y' to present 'bs' symbol and 'Y' to present 'rnum' symbolc for zkn instructions.
>
> Add new Entropy Source CSR define 'seed' located at address 0x015.
> ---
> gas/config/tc-riscv.c | 24 +++++++++++
> include/opcode/riscv-opc.h | 75 ++++++++++++++++++++++++++++++++
> include/opcode/riscv.h | 7 +++
> opcodes/riscv-dis.c | 8 ++++
> opcodes/riscv-opc.c | 87 ++++++++++++++++++++++++++++++--------
> 5 files changed, 184 insertions(+), 17 deletions(-)
>
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 5e7009b5696..2812432b8d6 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -1183,6 +1183,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
> case 'I': break; /* Macro operand, must be constant. */
> case 'D': /* RD, floating point. */
> case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
> + case 'y': USE_BITS (OP_MASK_BS, OP_SH_BS); break;
> + case 'Y': USE_BITS (OP_MASK_RNUM, OP_SH_RNUM); break;
> case 'Z': /* RS1, CSR number. */
> case 'S': /* RS1, floating point. */
> case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
> @@ -2804,6 +2806,28 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
> }
> break;
>
> + case 'y': /* bs immediate */
> + my_getExpression (imm_expr, asarg);
> + check_absolute_expr (ip, imm_expr, FALSE);
> + if ((unsigned long)imm_expr->X_add_number > 3)
> + as_bad(_("Improper bs immediate (%lu)"),
> + (unsigned long)imm_expr->X_add_number);
> + INSERT_OPERAND(BS, *ip, imm_expr->X_add_number);
> + imm_expr->X_op = O_absent;
> + asarg = expr_end;
> + continue;
> +
> + case 'Y': /* rcon immediate */
rnum, is this a typo?
> + my_getExpression (imm_expr, asarg);
> + check_absolute_expr (ip, imm_expr, FALSE);
> + if ((unsigned long)imm_expr->X_add_number > 10)
> + as_bad(_("Improper rnum immediate (%lu)"),
> + (unsigned long)imm_expr->X_add_number);
> + INSERT_OPERAND(RNUM, *ip, imm_expr->X_add_number);
> + imm_expr->X_op = O_absent;
> + asarg = expr_end;
> + continue;
> +
> case 'z':
> if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
> || imm_expr->X_op != O_constant
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 45a207da0cd..16a7cf243a9 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -443,6 +443,8 @@
> #define MASK_SEXT_H 0xfff0707f
> #define MATCH_PACK 0x8004033
> #define MASK_PACK 0xfe00707f
> +#define MATCH_PACKH 0x8007033
> +#define MASK_PACKH 0xfe00707f
> #define MATCH_PACKW 0x800403b
> #define MASK_PACKW 0xfe00707f
> #define MATCH_ANDN 0x40007033
> @@ -461,6 +463,10 @@
> #define MASK_GREVI 0xfc00707f
> #define MATCH_GORCI 0x28005013
> #define MASK_GORCI 0xfc00707f
> +#define MATCH_SHFLI 0x8001013
> +#define MASK_SHFLI 0xfc00707f
Consider current bitmanip spec,
https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/insns/zip.adoc
The encoding should be,
31-25, 24-20, 19-15, 14-12, 11-7, 6-2, 1-0
0x4, 0x1e, rs1, 0x1, rd, 0x4, 0x3
0000100, 11110, rs1, 001, rd, 00100, 11
1111111, 11111, rs1(00000), 111, rd(00000), 11111, 11, so the MASK_ZIP
should be 0xfff0707f.
But in the past, we usually use shfli/unshfli to encode the zip/unzip,
so consider the old spec,
https://github.com/riscv/riscv-bitmanip/blob/main-history/bitmanip-draft.pdf
31-26, 25-20, 19-15, 14-12, 11-7, 6-2, 1-0
000010, imm, rs1, 0x1, rd, 0x4, 0x3
1111111, imm, rs1, 001, rd, 00100, 11
1111111, imm(000000), rs1(00000), 111, rd(00000), 11111, 11, so the
MASK_SHFLI should be 0xfe00707f, rather than 0xfc00707f.
> +#define MATCH_UNSHFLI 0x8005013
> +#define MASK_UNSHFLI 0xfc00707f
Likewise, the MASK_UNSHFLI should be 0xfe00707f.
> #define MATCH_CLZW 0x6000101b
> #define MASK_CLZW 0xfff0707f
> #define MATCH_CTZW 0x6010101b
> @@ -495,6 +501,10 @@
> #define MASK_CLMULH 0xfe00707f
> #define MATCH_CLMULR 0xa002033
> #define MASK_CLMULR 0xfe00707f
> +#define MATCH_XPERM4 0x28002033
> +#define MASK_XPERM4 0xfe00707f
> +#define MATCH_XPERM8 0x28004033
> +#define MASK_XPERM8 0xfe00707f
> #define MATCH_BCLRI 0x48001013
> #define MASK_BCLRI 0xfc00707f
> #define MATCH_BSETI 0x28001013
> @@ -637,6 +647,64 @@
> #define MASK_C_LDSP 0xe003
> #define MATCH_C_SDSP 0xe002
> #define MASK_C_SDSP 0xe003
> +#define MATCH_SM3P0 0x10801013
> +#define MASK_SM3P0 0xfff0707f
> +#define MATCH_SM3P1 0x10901013
> +#define MASK_SM3P1 0xfff0707f
> +#define MATCH_SHA256SUM0 0x10001013
> +#define MASK_SHA256SUM0 0xfff0707f
> +#define MATCH_SHA256SUM1 0x10101013
> +#define MASK_SHA256SUM1 0xfff0707f
> +#define MATCH_SHA256SIG0 0x10201013
> +#define MASK_SHA256SIG0 0xfff0707f
> +#define MATCH_SHA256SIG1 0x10301013
> +#define MASK_SHA256SIG1 0xfff0707f
> +#define MATCH_SHA512SUM0R 0x50000033
> +#define MASK_SHA512SUM0R 0xfe00707f
> +#define MATCH_SHA512SUM1R 0x52000033
> +#define MASK_SHA512SUM1R 0xfe00707f
> +#define MATCH_SHA512SIG0L 0x54000033
> +#define MASK_SHA512SIG0L 0xfe00707f
> +#define MATCH_SHA512SIG0H 0x5c000033
> +#define MASK_SHA512SIG0H 0xfe00707f
> +#define MATCH_SHA512SIG1L 0x56000033
> +#define MASK_SHA512SIG1L 0xfe00707f
> +#define MATCH_SHA512SIG1H 0x5e000033
> +#define MASK_SHA512SIG1H 0xfe00707f
> +#define MATCH_SM4ED 0x30000033
> +#define MASK_SM4ED 0x3e00707f
> +#define MATCH_SM4KS 0x34000033
> +#define MASK_SM4KS 0x3e00707f
> +#define MATCH_AES32ESMI 0x26000033
> +#define MASK_AES32ESMI 0x3e00707f
> +#define MATCH_AES32ESI 0x22000033
> +#define MASK_AES32ESI 0x3e00707f
> +#define MATCH_AES32DSMI 0x2e000033
> +#define MASK_AES32DSMI 0x3e00707f
> +#define MATCH_AES32DSI 0x2a000033
> +#define MASK_AES32DSI 0x3e00707f
> +#define MATCH_SHA512SUM0 0x10401013
> +#define MASK_SHA512SUM0 0xfff0707f
> +#define MATCH_SHA512SUM1 0x10501013
> +#define MASK_SHA512SUM1 0xfff0707f
> +#define MATCH_SHA512SIG0 0x10601013
> +#define MASK_SHA512SIG0 0xfff0707f
> +#define MATCH_SHA512SIG1 0x10701013
> +#define MASK_SHA512SIG1 0xfff0707f
> +#define MATCH_AES64KS1I 0x31001013
> +#define MASK_AES64KS1I 0xff00707f
> +#define MATCH_AES64IM 0x30001013
> +#define MASK_AES64IM 0xfff0707f
> +#define MATCH_AES64KS2 0x7e000033
> +#define MASK_AES64KS2 0xfe00707f
> +#define MATCH_AES64ESM 0x36000033
> +#define MASK_AES64ESM 0xfe00707f
> +#define MATCH_AES64ES 0x32000033
> +#define MASK_AES64ES 0xfe00707f
> +#define MATCH_AES64DSM 0x3e000033
> +#define MASK_AES64DSM 0xfe00707f
> +#define MATCH_AES64DS 0x3a000033
> +#define MASK_AES64DS 0xfe00707f
> /* Privileged CSR addresses. */
> #define CSR_USTATUS 0x0
> #define CSR_UIE 0x4
> @@ -884,6 +952,7 @@
> #define CSR_TCONTROL 0x7a5
> #define CSR_MCONTEXT 0x7a8
> #define CSR_SCONTEXT 0x7aa
> +#define CSR_SEED 0x015
> #endif /* RISCV_ENCODING_H */
> #ifdef DECLARE_INSN
> DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
> @@ -1118,6 +1187,11 @@ DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
> DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
> DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
> DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
> +DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
> +DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
> +DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
> +DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4)
> +DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8)
> DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
> DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
> DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
> @@ -1436,6 +1510,7 @@ DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_C
> DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> +DECLARE_CSR(seed, CSR_SEED, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
Should the class be CSR_CLASS_ZKR? If so, then we need to update the
enum riscv_csr_class and riscv_csr_address, to make the -mcsr-check
option work for zkr extension. For example, added,
switch (csr_class)
{
case CSR_CLASS_ZKR:
result = riscv_subset_supports ("zkr");
need_check_version = false;
...
> #endif /* DECLARE_CSR */
> #ifdef DECLARE_CSR_ALIAS
> DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index f61004bdf95..1b5b7cb6ffc 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -261,6 +261,13 @@ static const char * const riscv_pred_succ[16] =
> #define OP_MASK_CFUNCT2 0x3
> #define OP_SH_CFUNCT2 5
>
> +/* Scalar crypto fields. */
> +
> +#define OP_SH_BS 30
> +#define OP_MASK_BS 3
> +#define OP_SH_RNUM 20
> +#define OP_MASK_RNUM 0xf
> +
> /* ABI names for selected x-registers. */
>
> #define X_RA 1
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index 1a094404fc5..9ef6e526690 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -362,6 +362,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
> print (info->stream, "%s", riscv_gpr_names[rd]);
> break;
>
> + case 'y':
> + print (info->stream, "0x%x", (int)EXTRACT_OPERAND (BS, l));
> + break;
> +
> case 'z':
> print (info->stream, "%s", riscv_gpr_names[0]);
> break;
> @@ -427,6 +431,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
> break;
> }
>
> + case 'Y':
> + print (info->stream, "0x%x", (int)EXTRACT_OPERAND (RNUM, l));
> + break;
> +
> case 'Z':
> print (info->stream, "%d", rs1);
> break;
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index b756bae64ab..a8f91e30b51 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -84,6 +84,9 @@ const char * const riscv_fpr_names_abi[NFPR] =
> #define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
> #define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
> #define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
> +#define MATCH_SHAMT_BREV8_32 (0b00111 << OP_SH_SHAMT)
> +#define MATCH_SHAMT_BREV8_64 (0b000111 << OP_SH_SHAMT)
> +#define MATCH_SHAMT_ZIP_32 (0b1111 << OP_SH_SHAMT)
> #define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
Not sure if it is necessary to keep the original M_PERM structure
here, since these rvbc pseudo IMM can actually be calculated. For
example, something like,
#define ENCODE_PERM_IMM(xlen, prefix, suffix) \
(ENCODE_ITYPE_IMM ((((xlen) - 1) & (((xlen) - 1) << (prefix)) & (suffix))))
#define MATCH_PERM_IMM(xlen) (ENCODE_PERM_IMM ((xlen), 0, -1))
#define MATCH_PERMP_IMM(xlen) (ENCODE_PERM_IMM ((xlen), 0, 0x1))
...
#define MATCH_PERM_SHFL_IMM(xlen) (ENCODE_PERM_IMM ((xlen/2), 0, -1))
...
{"rev", 32, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM_IMM (32),
MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
{"rev", 64, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM_IMM (64),
MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
{"orc.p", 32, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERMP_IMM (32),
MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
{"orc.p", 64, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERMP_IMM (64),
MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
...
{"zip", 32, INSN_CLASS_B, "d,s", MATCH_SHFLI | MATCH_PERM_SHFL_IMM
(32), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
{"zip", 64, INSN_CLASS_B, "d,s", MATCH_SHFLI | MATCH_PERM_SHFL_IMM
(64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
...
This doesn't really matter for now, but once we have supported the
whole rvb and rvbk extensions, keeping the M_PERM here may be helpful
for maintenance. I used to have an internal patch doing something
similar, if you are interested to complete this, maybe we could
discuss it in the later mails.
> static int
> @@ -783,7 +786,7 @@ const struct riscv_opcode riscv_opcodes[] =
> {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
> {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
>
> -/* Zbb instructions */
> +/* Zbb or zbkb instructions */
> {"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
> {"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
> {"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
> @@ -798,23 +801,30 @@ const struct riscv_opcode riscv_opcodes[] =
> {"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
> {"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
> {"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
> -{"andn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
> -{"orn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
> -{"xnor", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
> -{"rol", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
> -{"rori", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
> -{"ror", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
> -{"ror", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
> -{"rev8", 32, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> -{"rev8", 64, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> {"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_SHAMT_ORC_B, MASK_GORCI | MASK_SHAMT, match_opcode, 0 },
> {"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
> {"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
> {"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
> -{"rolw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
> -{"roriw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
> -{"rorw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
> -{"rorw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
> +{"brev8", 32, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> +{"brev8", 64, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
The MATCH_SHAMT_BREV8_32 and MATCH_SHAMT_BREV8_64 are the same, so we
probably don't need two entries but handle the same encoding.
> +{"zip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
> +{"unzip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
> +{"pack", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
> +{"packh", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
> +{"packw", 64, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
> +{"andn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
> +{"orn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
> +{"xnor", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
> +{"rol", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
> +{"rori", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
> +{"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
> +{"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
> +{"rev8", 32, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> +{"rev8", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> +{"rolw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
> +{"roriw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
> +{"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
> +{"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
>
> /* Zba instructions */
> {"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
> @@ -828,9 +838,9 @@ const struct riscv_opcode riscv_opcodes[] =
> {"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
> {"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
>
> -/* Zbc instructions */
> -{"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
> -{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
> +/* Zbc or zbkc instructions */
> +{"clmul", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
> +{"clmulh", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
> {"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
>
> /* Zbs instructions */
> @@ -847,6 +857,49 @@ const struct riscv_opcode riscv_opcodes[] =
> {"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
> {"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
>
> +/* Zbkx instructions */
> +{"xperm4", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM4, MASK_XPERM4, match_opcode, 0 },
> +{"xperm8", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM8, MASK_XPERM8, match_opcode, 0 },
> +
> +/* Zknd instructions */
> +{"aes32dsi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSI, MASK_AES32DSI, match_opcode, 0 },
> +{"aes32dsmi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSMI, MASK_AES32DSMI, match_opcode, 0 },
> +{"aes64ds", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DS, MASK_AES64DS, match_opcode, 0 },
> +{"aes64dsm", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DSM, MASK_AES64DSM, match_opcode, 0 },
> +{"aes64im", 64, INSN_CLASS_ZKND, "d,s", MATCH_AES64IM, MASK_AES64IM, match_opcode, 0 },
> +{"aes64ks1i", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,Y", MATCH_AES64KS1I, MASK_AES64KS1I, match_opcode, 0 },
> +{"aes64ks2", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,t", MATCH_AES64KS2, MASK_AES64KS2, match_opcode, 0 },
> +
> +/* Zkne instructions */
> +{"aes32esi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESI, MASK_AES32ESI, match_opcode, 0 },
> +{"aes32esmi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESMI, MASK_AES32ESMI, match_opcode, 0 },
> +{"aes64es", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ES, MASK_AES64ES, match_opcode, 0 },
> +{"aes64esm", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ESM, MASK_AES64ESM, match_opcode, 0 },
> +
> +/* Zknh instructions */
> +{"sha256sig0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG0, MASK_SHA256SIG0, match_opcode, 0 },
> +{"sha256sig1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG1, MASK_SHA256SIG1, match_opcode, 0 },
> +{"sha256sum0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM0, MASK_SHA256SUM0, match_opcode, 0 },
> +{"sha256sum1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM1, MASK_SHA256SUM1, match_opcode, 0 },
> +{"sha512sig0h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0H, MASK_SHA512SIG0H, match_opcode, 0 },
> +{"sha512sig0l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0L, MASK_SHA512SIG0L, match_opcode, 0 },
> +{"sha512sig1h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1H, MASK_SHA512SIG1H, match_opcode, 0 },
> +{"sha512sig1l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1L, MASK_SHA512SIG1L, match_opcode, 0 },
> +{"sha512sum0r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM0R, MASK_SHA512SUM0R, match_opcode, 0 },
> +{"sha512sum1r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM1R, MASK_SHA512SUM1R, match_opcode, 0 },
> +{"sha512sig0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG0, MASK_SHA512SIG0, match_opcode, 0 },
> +{"sha512sig1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG1, MASK_SHA512SIG1, match_opcode, 0 },
> +{"sha512sum0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM0, MASK_SHA512SUM0, match_opcode, 0 },
> +{"sha512sum1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM1, MASK_SHA512SUM1, match_opcode, 0 },
> +
> +/* Zksed instructions */
> +{"sm4ed", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4ED, MASK_SM4ED, match_opcode, 0 },
> +{"sm4ks", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4KS, MASK_SM4KS, match_opcode, 0 },
> +
> +/* Zksh instructions */
> +{"sm3p0", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P0, MASK_SM3P0, match_opcode, 0 },
> +{"sm3p1", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P1, MASK_SM3P1, match_opcode, 0 },
> +
> /* Terminate the list. */
> {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
> };
> --
>
Except the above comments, the encodings should be all correct, so
this looks good to me.
Thanks
Nelson
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: Re: [PATCH v3 2/3] RISC-V: Scalar crypto instructions and operand set
2021-11-10 9:26 ` Nelson Chu
@ 2021-11-11 3:30 ` 陈嘉炜
0 siblings, 0 replies; 7+ messages in thread
From: 陈嘉炜 @ 2021-11-11 3:30 UTC (permalink / raw)
To: Nelson Chu
Cc: Binutils, Kito Cheng, Jim Wilson, Philipp Tomsich, mjos,
ben.marshall, cmuellner, Palmer Dabbelt, Andrew Waterman,
Wei Wu (吴伟),
siyu, Andreas Schwab, Jan Beulich
> -----原始邮件-----
> 发件人: "Nelson Chu" <nelson.chu@sifive.com>
> 发送时间: 2021-11-10 17:26:38 (星期三)
> 收件人: jiawei <jiawei@iscas.ac.cn>
> 抄送: Binutils <binutils@sourceware.org>, "Kito Cheng" <kito.cheng@sifive.com>, "Jim Wilson" <jimw@sifive.com>, "Philipp Tomsich" <philipp.tomsich@vrull.eu>, mjos@pqshield.com, ben.marshall@pqshield.com, cmuellner@ventanamicro.com, "Palmer Dabbelt" <palmer@dabbelt.com>, "Andrew Waterman" <andrew@sifive.com>, "Wei Wu (吴伟)" <lazyparser@gmail.com>, siyu@isrc.iscas.ac.cn, "Andreas Schwab" <schwab@linux-m68k.org>, "Jan Beulich" <jbeulich@suse.com>
> 主题: Re: [PATCH v3 2/3] RISC-V: Scalar crypto instructions and operand set
>
> On Thu, Nov 4, 2021 at 1:56 PM jiawei <jiawei@iscas.ac.cn> wrote:
> >
> > Add instructions in k-ext, some instruction in zbkb, zbkc is reuse from zbb,zbc, we just change the class attribute to make them both support.
> >
> > The 'aes64ks1i' and 'aes64ks2' instructions are present in both the Zknd and Zkne extensions on rv64.
> >
> > Add new operand letter 'y' to present 'bs' symbol and 'Y' to present 'rnum' symbolc for zkn instructions.
> >
> > Add new Entropy Source CSR define 'seed' located at address 0x015.
> > ---
> > gas/config/tc-riscv.c | 24 +++++++++++
> > include/opcode/riscv-opc.h | 75 ++++++++++++++++++++++++++++++++
> > include/opcode/riscv.h | 7 +++
> > opcodes/riscv-dis.c | 8 ++++
> > opcodes/riscv-opc.c | 87 ++++++++++++++++++++++++++++++--------
> > 5 files changed, 184 insertions(+), 17 deletions(-)
> >
> > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> > index 5e7009b5696..2812432b8d6 100644
> > --- a/gas/config/tc-riscv.c
> > +++ b/gas/config/tc-riscv.c
> > @@ -1183,6 +1183,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
> > case 'I': break; /* Macro operand, must be constant. */
> > case 'D': /* RD, floating point. */
> > case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
> > + case 'y': USE_BITS (OP_MASK_BS, OP_SH_BS); break;
> > + case 'Y': USE_BITS (OP_MASK_RNUM, OP_SH_RNUM); break;
> > case 'Z': /* RS1, CSR number. */
> > case 'S': /* RS1, floating point. */
> > case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
> > @@ -2804,6 +2806,28 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
> > }
> > break;
> >
> > + case 'y': /* bs immediate */
> > + my_getExpression (imm_expr, asarg);
> > + check_absolute_expr (ip, imm_expr, FALSE);
> > + if ((unsigned long)imm_expr->X_add_number > 3)
> > + as_bad(_("Improper bs immediate (%lu)"),
> > + (unsigned long)imm_expr->X_add_number);
> > + INSERT_OPERAND(BS, *ip, imm_expr->X_add_number);
> > + imm_expr->X_op = O_absent;
> > + asarg = expr_end;
> > + continue;
> > +
> > + case 'Y': /* rcon immediate */
>
> rnum, is this a typo?
Sorry for the error typo, I had fix it.
> > + my_getExpression (imm_expr, asarg);
> > + check_absolute_expr (ip, imm_expr, FALSE);
> > + if ((unsigned long)imm_expr->X_add_number > 10)
> > + as_bad(_("Improper rnum immediate (%lu)"),
> > + (unsigned long)imm_expr->X_add_number);
> > + INSERT_OPERAND(RNUM, *ip, imm_expr->X_add_number);
> > + imm_expr->X_op = O_absent;
> > + asarg = expr_end;
> > + continue;
> > +
> > case 'z':
> > if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
> > || imm_expr->X_op != O_constant
> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> > index 45a207da0cd..16a7cf243a9 100644
> > --- a/include/opcode/riscv-opc.h
> > +++ b/include/opcode/riscv-opc.h
> > @@ -443,6 +443,8 @@
> > #define MASK_SEXT_H 0xfff0707f
> > #define MATCH_PACK 0x8004033
> > #define MASK_PACK 0xfe00707f
> > +#define MATCH_PACKH 0x8007033
> > +#define MASK_PACKH 0xfe00707f
> > #define MATCH_PACKW 0x800403b
> > #define MASK_PACKW 0xfe00707f
> > #define MATCH_ANDN 0x40007033
> > @@ -461,6 +463,10 @@
> > #define MASK_GREVI 0xfc00707f
> > #define MATCH_GORCI 0x28005013
> > #define MASK_GORCI 0xfc00707f
> > +#define MATCH_SHFLI 0x8001013
> > +#define MASK_SHFLI 0xfc00707f
>
> Consider current bitmanip spec,
> https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/insns/zip.adoc
>
> The encoding should be,
> 31-25, 24-20, 19-15, 14-12, 11-7, 6-2, 1-0
> 0x4, 0x1e, rs1, 0x1, rd, 0x4, 0x3
> 0000100, 11110, rs1, 001, rd, 00100, 11
> 1111111, 11111, rs1(00000), 111, rd(00000), 11111, 11, so the MASK_ZIP
> should be 0xfff0707f.
>
> But in the past, we usually use shfli/unshfli to encode the zip/unzip,
> so consider the old spec,
> https://github.com/riscv/riscv-bitmanip/blob/main-history/bitmanip-draft.pdf
>
> 31-26, 25-20, 19-15, 14-12, 11-7, 6-2, 1-0
> 000010, imm, rs1, 0x1, rd, 0x4, 0x3
> 1111111, imm, rs1, 001, rd, 00100, 11
> 1111111, imm(000000), rs1(00000), 111, rd(00000), 11111, 11, so the
> MASK_SHFLI should be 0xfe00707f, rather than 0xfc00707f.
>
> > +#define MATCH_UNSHFLI 0x8005013
> > +#define MASK_UNSHFLI 0xfc00707f
>
> Likewise, the MASK_UNSHFLI should be 0xfe00707f.
>
Thank you for the mention, it will be fixed in next version.
> > #define MATCH_CLZW 0x6000101b
> > #define MASK_CLZW 0xfff0707f
> > #define MATCH_CTZW 0x6010101b
> > @@ -495,6 +501,10 @@
> > #define MASK_CLMULH 0xfe00707f
> > #define MATCH_CLMULR 0xa002033
> > #define MASK_CLMULR 0xfe00707f
> > +#define MATCH_XPERM4 0x28002033
> > +#define MASK_XPERM4 0xfe00707f
> > +#define MATCH_XPERM8 0x28004033
> > +#define MASK_XPERM8 0xfe00707f
> > #define MATCH_BCLRI 0x48001013
> > #define MASK_BCLRI 0xfc00707f
> > #define MATCH_BSETI 0x28001013
> > @@ -637,6 +647,64 @@
> > #define MASK_C_LDSP 0xe003
> > #define MATCH_C_SDSP 0xe002
> > #define MASK_C_SDSP 0xe003
> > +#define MATCH_SM3P0 0x10801013
> > +#define MASK_SM3P0 0xfff0707f
> > +#define MATCH_SM3P1 0x10901013
> > +#define MASK_SM3P1 0xfff0707f
> > +#define MATCH_SHA256SUM0 0x10001013
> > +#define MASK_SHA256SUM0 0xfff0707f
> > +#define MATCH_SHA256SUM1 0x10101013
> > +#define MASK_SHA256SUM1 0xfff0707f
> > +#define MATCH_SHA256SIG0 0x10201013
> > +#define MASK_SHA256SIG0 0xfff0707f
> > +#define MATCH_SHA256SIG1 0x10301013
> > +#define MASK_SHA256SIG1 0xfff0707f
> > +#define MATCH_SHA512SUM0R 0x50000033
> > +#define MASK_SHA512SUM0R 0xfe00707f
> > +#define MATCH_SHA512SUM1R 0x52000033
> > +#define MASK_SHA512SUM1R 0xfe00707f
> > +#define MATCH_SHA512SIG0L 0x54000033
> > +#define MASK_SHA512SIG0L 0xfe00707f
> > +#define MATCH_SHA512SIG0H 0x5c000033
> > +#define MASK_SHA512SIG0H 0xfe00707f
> > +#define MATCH_SHA512SIG1L 0x56000033
> > +#define MASK_SHA512SIG1L 0xfe00707f
> > +#define MATCH_SHA512SIG1H 0x5e000033
> > +#define MASK_SHA512SIG1H 0xfe00707f
> > +#define MATCH_SM4ED 0x30000033
> > +#define MASK_SM4ED 0x3e00707f
> > +#define MATCH_SM4KS 0x34000033
> > +#define MASK_SM4KS 0x3e00707f
> > +#define MATCH_AES32ESMI 0x26000033
> > +#define MASK_AES32ESMI 0x3e00707f
> > +#define MATCH_AES32ESI 0x22000033
> > +#define MASK_AES32ESI 0x3e00707f
> > +#define MATCH_AES32DSMI 0x2e000033
> > +#define MASK_AES32DSMI 0x3e00707f
> > +#define MATCH_AES32DSI 0x2a000033
> > +#define MASK_AES32DSI 0x3e00707f
> > +#define MATCH_SHA512SUM0 0x10401013
> > +#define MASK_SHA512SUM0 0xfff0707f
> > +#define MATCH_SHA512SUM1 0x10501013
> > +#define MASK_SHA512SUM1 0xfff0707f
> > +#define MATCH_SHA512SIG0 0x10601013
> > +#define MASK_SHA512SIG0 0xfff0707f
> > +#define MATCH_SHA512SIG1 0x10701013
> > +#define MASK_SHA512SIG1 0xfff0707f
> > +#define MATCH_AES64KS1I 0x31001013
> > +#define MASK_AES64KS1I 0xff00707f
> > +#define MATCH_AES64IM 0x30001013
> > +#define MASK_AES64IM 0xfff0707f
> > +#define MATCH_AES64KS2 0x7e000033
> > +#define MASK_AES64KS2 0xfe00707f
> > +#define MATCH_AES64ESM 0x36000033
> > +#define MASK_AES64ESM 0xfe00707f
> > +#define MATCH_AES64ES 0x32000033
> > +#define MASK_AES64ES 0xfe00707f
> > +#define MATCH_AES64DSM 0x3e000033
> > +#define MASK_AES64DSM 0xfe00707f
> > +#define MATCH_AES64DS 0x3a000033
> > +#define MASK_AES64DS 0xfe00707f
> > /* Privileged CSR addresses. */
> > #define CSR_USTATUS 0x0
> > #define CSR_UIE 0x4
> > @@ -884,6 +952,7 @@
> > #define CSR_TCONTROL 0x7a5
> > #define CSR_MCONTEXT 0x7a8
> > #define CSR_SCONTEXT 0x7aa
> > +#define CSR_SEED 0x015
> > #endif /* RISCV_ENCODING_H */
> > #ifdef DECLARE_INSN
> > DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
> > @@ -1118,6 +1187,11 @@ DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
> > DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
> > DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
> > DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
> > +DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
> > +DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
> > +DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
> > +DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4)
> > +DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8)
> > DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
> > DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
> > DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
> > @@ -1436,6 +1510,7 @@ DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_C
> > DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> > DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> > DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> > +DECLARE_CSR(seed, CSR_SEED, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
>
> Should the class be CSR_CLASS_ZKR? If so, then we need to update the
> enum riscv_csr_class and riscv_csr_address, to make the -mcsr-check
> option work for zkr extension. For example, added,
>
I am not sure if there need to add a need CSR class, since the ZKR only have one new register, temply I will add it in next version, thanks for the suggestion.
> switch (csr_class)
> {
> case CSR_CLASS_ZKR:
> result = riscv_subset_supports ("zkr");
> need_check_version = false;
> ...
>
> > #endif /* DECLARE_CSR */
> > #ifdef DECLARE_CSR_ALIAS
> > DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
> > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> > index f61004bdf95..1b5b7cb6ffc 100644
> > --- a/include/opcode/riscv.h
> > +++ b/include/opcode/riscv.h
> > @@ -261,6 +261,13 @@ static const char * const riscv_pred_succ[16] =
> > #define OP_MASK_CFUNCT2 0x3
> > #define OP_SH_CFUNCT2 5
> >
> > +/* Scalar crypto fields. */
> > +
> > +#define OP_SH_BS 30
> > +#define OP_MASK_BS 3
> > +#define OP_SH_RNUM 20
> > +#define OP_MASK_RNUM 0xf
> > +
> > /* ABI names for selected x-registers. */
> >
> > #define X_RA 1
> > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> > index 1a094404fc5..9ef6e526690 100644
> > --- a/opcodes/riscv-dis.c
> > +++ b/opcodes/riscv-dis.c
> > @@ -362,6 +362,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
> > print (info->stream, "%s", riscv_gpr_names[rd]);
> > break;
> >
> > + case 'y':
> > + print (info->stream, "0x%x", (int)EXTRACT_OPERAND (BS, l));
> > + break;
> > +
> > case 'z':
> > print (info->stream, "%s", riscv_gpr_names[0]);
> > break;
> > @@ -427,6 +431,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
> > break;
> > }
> >
> > + case 'Y':
> > + print (info->stream, "0x%x", (int)EXTRACT_OPERAND (RNUM, l));
> > + break;
> > +
> > case 'Z':
> > print (info->stream, "%d", rs1);
> > break;
> > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> > index b756bae64ab..a8f91e30b51 100644
> > --- a/opcodes/riscv-opc.c
> > +++ b/opcodes/riscv-opc.c
> > @@ -84,6 +84,9 @@ const char * const riscv_fpr_names_abi[NFPR] =
> > #define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
> > #define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
> > #define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
> > +#define MATCH_SHAMT_BREV8_32 (0b00111 << OP_SH_SHAMT)
> > +#define MATCH_SHAMT_BREV8_64 (0b000111 << OP_SH_SHAMT)
> > +#define MATCH_SHAMT_ZIP_32 (0b1111 << OP_SH_SHAMT)
> > #define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
>
> Not sure if it is necessary to keep the original M_PERM structure
> here, since these rvbc pseudo IMM can actually be calculated. For
> example, something like,
>
> #define ENCODE_PERM_IMM(xlen, prefix, suffix) \
> (ENCODE_ITYPE_IMM ((((xlen) - 1) & (((xlen) - 1) << (prefix)) & (suffix))))
>
> #define MATCH_PERM_IMM(xlen) (ENCODE_PERM_IMM ((xlen), 0, -1))
> #define MATCH_PERMP_IMM(xlen) (ENCODE_PERM_IMM ((xlen), 0, 0x1))
> ...
> #define MATCH_PERM_SHFL_IMM(xlen) (ENCODE_PERM_IMM ((xlen/2), 0, -1))
> ...
> {"rev", 32, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM_IMM (32),
> MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
> {"rev", 64, INSN_CLASS_B, "d,s", MATCH_GREVI | MATCH_PERM_IMM (64),
> MASK_GREVI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
> {"orc.p", 32, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERMP_IMM (32),
> MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
> {"orc.p", 64, INSN_CLASS_B, "d,s", MATCH_GORCI | MATCH_PERMP_IMM (64),
> MASK_GORCI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
> ...
> {"zip", 32, INSN_CLASS_B, "d,s", MATCH_SHFLI | MATCH_PERM_SHFL_IMM
> (32), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
> {"zip", 64, INSN_CLASS_B, "d,s", MATCH_SHFLI | MATCH_PERM_SHFL_IMM
> (64), MASK_SHFLI | MASK_RVB_IMM, match_opcode, INSN_ALIAS },
> ...
>
> This doesn't really matter for now, but once we have supported the
> whole rvb and rvbk extensions, keeping the M_PERM here may be helpful
> for maintenance. I used to have an internal patch doing something
> similar, if you are interested to complete this, maybe we could
> discuss it in the later mails.
Since there still have a lot of pseudo-instructions with zip/unzip not implement,
like zip2/zip4/zip8/zip.b/zip.n..., so I think keeping the M_PERM is good.
>
> > static int
> > @@ -783,7 +786,7 @@ const struct riscv_opcode riscv_opcodes[] =
> > {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
> > {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
> >
> > -/* Zbb instructions */
> > +/* Zbb or zbkb instructions */
> > {"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
> > {"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
> > {"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
> > @@ -798,23 +801,30 @@ const struct riscv_opcode riscv_opcodes[] =
> > {"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
> > {"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
> > {"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
> > -{"andn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
> > -{"orn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
> > -{"xnor", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
> > -{"rol", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
> > -{"rori", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
> > -{"ror", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
> > -{"ror", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
> > -{"rev8", 32, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> > -{"rev8", 64, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> > {"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_SHAMT_ORC_B, MASK_GORCI | MASK_SHAMT, match_opcode, 0 },
> > {"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
> > {"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
> > {"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
> > -{"rolw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
> > -{"roriw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
> > -{"rorw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
> > -{"rorw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
> > +{"brev8", 32, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> > +{"brev8", 64, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
>
> The MATCH_SHAMT_BREV8_32 and MATCH_SHAMT_BREV8_64 are the same, so we
> probably don't need two entries but handle the same encoding.
I will merge them in next version, thanks!
>
> > +{"zip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
> > +{"unzip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
> > +{"pack", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
> > +{"packh", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
> > +{"packw", 64, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
> > +{"andn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
> > +{"orn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
> > +{"xnor", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
> > +{"rol", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
> > +{"rori", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
> > +{"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
> > +{"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
> > +{"rev8", 32, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> > +{"rev8", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> > +{"rolw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
> > +{"roriw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
> > +{"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
> > +{"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
> >
> > /* Zba instructions */
> > {"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
> > @@ -828,9 +838,9 @@ const struct riscv_opcode riscv_opcodes[] =
> > {"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
> > {"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
> >
> > -/* Zbc instructions */
> > -{"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
> > -{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
> > +/* Zbc or zbkc instructions */
> > +{"clmul", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
> > +{"clmulh", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
> > {"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
> >
> > /* Zbs instructions */
> > @@ -847,6 +857,49 @@ const struct riscv_opcode riscv_opcodes[] =
> > {"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
> > {"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
> >
> > +/* Zbkx instructions */
> > +{"xperm4", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM4, MASK_XPERM4, match_opcode, 0 },
> > +{"xperm8", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM8, MASK_XPERM8, match_opcode, 0 },
> > +
> > +/* Zknd instructions */
> > +{"aes32dsi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSI, MASK_AES32DSI, match_opcode, 0 },
> > +{"aes32dsmi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSMI, MASK_AES32DSMI, match_opcode, 0 },
> > +{"aes64ds", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DS, MASK_AES64DS, match_opcode, 0 },
> > +{"aes64dsm", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DSM, MASK_AES64DSM, match_opcode, 0 },
> > +{"aes64im", 64, INSN_CLASS_ZKND, "d,s", MATCH_AES64IM, MASK_AES64IM, match_opcode, 0 },
> > +{"aes64ks1i", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,Y", MATCH_AES64KS1I, MASK_AES64KS1I, match_opcode, 0 },
> > +{"aes64ks2", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,t", MATCH_AES64KS2, MASK_AES64KS2, match_opcode, 0 },
> > +
> > +/* Zkne instructions */
> > +{"aes32esi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESI, MASK_AES32ESI, match_opcode, 0 },
> > +{"aes32esmi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESMI, MASK_AES32ESMI, match_opcode, 0 },
> > +{"aes64es", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ES, MASK_AES64ES, match_opcode, 0 },
> > +{"aes64esm", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ESM, MASK_AES64ESM, match_opcode, 0 },
> > +
> > +/* Zknh instructions */
> > +{"sha256sig0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG0, MASK_SHA256SIG0, match_opcode, 0 },
> > +{"sha256sig1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG1, MASK_SHA256SIG1, match_opcode, 0 },
> > +{"sha256sum0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM0, MASK_SHA256SUM0, match_opcode, 0 },
> > +{"sha256sum1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM1, MASK_SHA256SUM1, match_opcode, 0 },
> > +{"sha512sig0h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0H, MASK_SHA512SIG0H, match_opcode, 0 },
> > +{"sha512sig0l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0L, MASK_SHA512SIG0L, match_opcode, 0 },
> > +{"sha512sig1h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1H, MASK_SHA512SIG1H, match_opcode, 0 },
> > +{"sha512sig1l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1L, MASK_SHA512SIG1L, match_opcode, 0 },
> > +{"sha512sum0r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM0R, MASK_SHA512SUM0R, match_opcode, 0 },
> > +{"sha512sum1r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM1R, MASK_SHA512SUM1R, match_opcode, 0 },
> > +{"sha512sig0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG0, MASK_SHA512SIG0, match_opcode, 0 },
> > +{"sha512sig1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG1, MASK_SHA512SIG1, match_opcode, 0 },
> > +{"sha512sum0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM0, MASK_SHA512SUM0, match_opcode, 0 },
> > +{"sha512sum1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM1, MASK_SHA512SUM1, match_opcode, 0 },
> > +
> > +/* Zksed instructions */
> > +{"sm4ed", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4ED, MASK_SM4ED, match_opcode, 0 },
> > +{"sm4ks", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4KS, MASK_SM4KS, match_opcode, 0 },
> > +
> > +/* Zksh instructions */
> > +{"sm3p0", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P0, MASK_SM3P0, match_opcode, 0 },
> > +{"sm3p1", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P1, MASK_SM3P1, match_opcode, 0 },
> > +
> > /* Terminate the list. */
> > {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
> > };
> > --
> >
>
> Except the above comments, the encodings should be all correct, so
> this looks good to me.
>
> Thanks
> Nelson
Best wishes
Jiawei</jiawei@iscas.ac.cn></jbeulich@suse.com></schwab@linux-m68k.org></lazyparser@gmail.com></andrew@sifive.com></palmer@dabbelt.com></philipp.tomsich@vrull.eu></jimw@sifive.com></kito.cheng@sifive.com></binutils@sourceware.org></jiawei@iscas.ac.cn></nelson.chu@sifive.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
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Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2021-11-04 5:56 [PATCH v3 0/3] RISC-V: Support Scalar Cryptography extension jiawei
2021-11-04 5:56 ` [PATCH v3 1/3] RISC-V: Minimal support of scalar crypto extension jiawei
2021-11-10 2:38 ` Nelson Chu
2021-11-04 5:56 ` [PATCH v3 2/3] RISC-V: Scalar crypto instructions and operand set jiawei
2021-11-10 9:26 ` Nelson Chu
2021-11-11 3:30 ` 陈嘉炜
2021-11-04 5:56 ` [PATCH v3 3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases jiawei
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