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From: Vineet Gupta <vineetg@rivosinc.com>
To: Binutils <binutils@sourceware.org>, Nelson Chu <nelson.chu@sifive.com>
Cc: Kito Cheng <kito.cheng@sifive.com>,
	jim.wilson.gcc@gmail.com, palmer@dabbelt.com,
	Vineet Gupta <vineetg@rivosinc.com>
Subject: [v1 4/4] RISC-V: fix a comment for adding CSR entry and annotate switch-break
Date: Mon, 20 Dec 2021 18:34:15 -0800	[thread overview]
Message-ID: <20211221023415.2211328-5-vineetg@rivosinc.com> (raw)
In-Reply-To: <20211221023415.2211328-1-vineetg@rivosinc.com>

Nothing functional ...

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
---
 gas/config/tc-riscv.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index e8061217e7cd..dbf0e23c4563 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -82,7 +82,7 @@ struct riscv_csr_extra
   enum riscv_spec_class define_version;
 
   /* Record the CSR is aborted/invalid from which versions.  If it isn't
-     aborted in the current version, then it should be CSR_CLASS_VDRAFT.  */
+     aborted in the current version, then it should be PRIV_SPEC_CLASS_DRAFT.  */
   enum riscv_spec_class abort_version;
 
   /* The CSR may have more than one setting.  */
@@ -1104,7 +1104,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	    default:
 	      goto unknown_validate_operand;
 	    }
-	  break;
+	  break;  /* end RVC */
 	case 'V': /* RVV */
 	  switch (*++oparg)
 	    {
@@ -1128,7 +1128,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	    default:
 	      goto unknown_validate_operand;
 	    }
-	  break;
+	  break; /* end RVV */
 	case ',': break;
 	case '(': break;
 	case ')': break;
@@ -2605,7 +2605,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		default:
 		  goto unknown_riscv_ip_operand;
 		}
-	      break;
+	      break; /* end RVC */
 
 	    case 'V': /* RVV */
 	      switch (*++oparg)
@@ -2771,7 +2771,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		default:
 		  goto unknown_riscv_ip_operand;
 		}
-	      break;
+	      break; /* end RVV */
 
 	    case ',':
 	      ++argnum;
-- 
2.30.2


  parent reply	other threads:[~2021-12-21  2:34 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-21  2:34 [v1 0/4]riscv/binutils support Hypervisor Extension Vineet Gupta
2021-12-21  2:34 ` [v1 1/4] RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/tests Vineet Gupta
2021-12-24  8:23   ` Nelson Chu
2021-12-21  2:34 ` [v1 2/4] RISC-V: Hypervisor ext: support Privileged Spec 1.12 Vineet Gupta
2021-12-24  8:40   ` Nelson Chu
2022-01-04  8:09   ` Jan Beulich
2022-01-04 18:10     ` Vineet Gupta
2021-12-21  2:34 ` [v1 3/4] RISC-V: Hypervisor Ext: Add tests Vineet Gupta
2022-01-04  8:12   ` Jan Beulich
2022-01-04 18:46     ` Vineet Gupta
2021-12-21  2:34 ` Vineet Gupta [this message]
2021-12-23  1:35 ` [v1 0/4]riscv/binutils support Hypervisor Extension Palmer Dabbelt
2021-12-24  8:51   ` Nelson Chu
2021-12-28 17:54     ` Vineet Gupta

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