* [v1 0/4]riscv/binutils support Hypervisor Extension
@ 2021-12-21 2:34 Vineet Gupta
2021-12-21 2:34 ` [v1 1/4] RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/tests Vineet Gupta
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Vineet Gupta @ 2021-12-21 2:34 UTC (permalink / raw)
To: Binutils, Nelson Chu; +Cc: Kito Cheng, jim.wilson.gcc, palmer, Vineet Gupta
Hi,
This patchset adds support for Hypervisor Extension ratified recently
[1].
Changes since RFC [2]:
- Drop support for single-letter arch string "h".
'H' extension is currently supported unconditionally so keep status quo.
- H-ext support in Priv spec 1.9.1 dropped, broken out as seperate patch.
Please review/comment !
Thx,
-Vineet
[1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions
[2] https://sourceware.org/pipermail/binutils/2021-December/118914.html
Vineet Gupta (4):
RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1
implementation/tests
RISC-V: Hypervisor ext: support Privileged Spec 1.12
RISC-V: Hypervisor Ext: Add tests
RISC-V: fix a comment for adding CSR entry and annotate switch-break
bfd/cpu-riscv.c | 1 +
bfd/cpu-riscv.h | 1 +
bfd/elfxx-riscv.c | 6 +
gas/config/tc-riscv.c | 10 +-
gas/testsuite/gas/riscv/csr-dw-regnums.d | 10 --
gas/testsuite/gas/riscv/csr-dw-regnums.s | 10 --
gas/testsuite/gas/riscv/h-ext-32.d | 74 ++++++++++++
gas/testsuite/gas/riscv/h-ext-32.s | 64 ++++++++++
gas/testsuite/gas/riscv/h-ext-64.d | 73 ++++++++++++
gas/testsuite/gas/riscv/h-ext-64.s | 63 ++++++++++
.../gas/riscv/priv-reg-fail-read-only-01.s | 10 --
.../gas/riscv/priv-reg-fail-version-1p10.l | 10 --
.../gas/riscv/priv-reg-fail-version-1p11.l | 10 --
.../gas/riscv/priv-reg-version-1p10.d | 10 --
.../gas/riscv/priv-reg-version-1p11.d | 10 --
.../gas/riscv/priv-reg-version-1p9p1.d | 10 --
gas/testsuite/gas/riscv/priv-reg.s | 10 --
gas/testsuite/gas/riscv/svinval-and-h.d | 15 +++
gas/testsuite/gas/riscv/svinval-and-h.s | 5 +
include/opcode/riscv-opc.h | 110 ++++++++++++++----
include/opcode/riscv.h | 2 +
opcodes/riscv-opc.c | 26 ++++-
22 files changed, 423 insertions(+), 117 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/h-ext-32.d
create mode 100644 gas/testsuite/gas/riscv/h-ext-32.s
create mode 100644 gas/testsuite/gas/riscv/h-ext-64.d
create mode 100644 gas/testsuite/gas/riscv/h-ext-64.s
create mode 100644 gas/testsuite/gas/riscv/svinval-and-h.d
create mode 100644 gas/testsuite/gas/riscv/svinval-and-h.s
--
2.30.2
^ permalink raw reply [flat|nested] 14+ messages in thread* [v1 1/4] RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/tests 2021-12-21 2:34 [v1 0/4]riscv/binutils support Hypervisor Extension Vineet Gupta @ 2021-12-21 2:34 ` Vineet Gupta 2021-12-24 8:23 ` Nelson Chu 2021-12-21 2:34 ` [v1 2/4] RISC-V: Hypervisor ext: support Privileged Spec 1.12 Vineet Gupta ` (3 subsequent siblings) 4 siblings, 1 reply; 14+ messages in thread From: Vineet Gupta @ 2021-12-21 2:34 UTC (permalink / raw) To: Binutils, Nelson Chu; +Cc: Kito Cheng, jim.wilson.gcc, palmer, Vineet Gupta This makes way for a clean 1.12 based Hypervisor Ext support. There are no known implementors of 1.9.1 H-ext. (Per Jim, kendryte k210 is based on priv spec 1.9.1, but it seems unlikely that they implemented H-ext). Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> --- gas/testsuite/gas/riscv/csr-dw-regnums.d | 10 ---------- gas/testsuite/gas/riscv/csr-dw-regnums.s | 10 ---------- .../gas/riscv/priv-reg-fail-read-only-01.s | 10 ---------- .../gas/riscv/priv-reg-fail-version-1p10.l | 10 ---------- .../gas/riscv/priv-reg-fail-version-1p11.l | 10 ---------- .../gas/riscv/priv-reg-version-1p10.d | 10 ---------- .../gas/riscv/priv-reg-version-1p11.d | 10 ---------- .../gas/riscv/priv-reg-version-1p9p1.d | 10 ---------- gas/testsuite/gas/riscv/priv-reg.s | 10 ---------- include/opcode/riscv-opc.h | 20 ------------------- 10 files changed, 110 deletions(-) diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d index de17ad81fbde..ea0a445c39ce 100644 --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d @@ -229,16 +229,6 @@ Contents of the .* section: DW_CFA_offset_extended_sf: r4925 \(mhpmevent29\) at cfa\+3316 DW_CFA_offset_extended_sf: r4926 \(mhpmevent30\) at cfa\+3320 DW_CFA_offset_extended_sf: r4927 \(mhpmevent31\) at cfa\+3324 - DW_CFA_offset_extended_sf: r4608 \(hstatus\) at cfa\+2048 - DW_CFA_offset_extended_sf: r4610 \(hedeleg\) at cfa\+2056 - DW_CFA_offset_extended_sf: r4611 \(hideleg\) at cfa\+2060 - DW_CFA_offset_extended_sf: r4612 \(hie\) at cfa\+2064 - DW_CFA_offset_extended_sf: r4613 \(htvec\) at cfa\+2068 - DW_CFA_offset_extended_sf: r4672 \(hscratch\) at cfa\+2304 - DW_CFA_offset_extended_sf: r4673 \(hepc\) at cfa\+2308 - DW_CFA_offset_extended_sf: r4674 \(hcause\) at cfa\+2312 - DW_CFA_offset_extended_sf: r4675 \(hbadaddr\) at cfa\+2316 - DW_CFA_offset_extended_sf: r4676 \(hip\) at cfa\+2320 DW_CFA_offset_extended_sf: r4992 \(mbase\) at cfa\+3584 DW_CFA_offset_extended_sf: r4993 \(mbound\) at cfa\+3588 DW_CFA_offset_extended_sf: r4994 \(mibase\) at cfa\+3592 diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s index ecc801469763..549475d650e8 100644 --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s @@ -220,16 +220,6 @@ _start: .cfi_offset mhpmevent30, 3320 .cfi_offset mhpmevent31, 3324 # dropped - .cfi_offset hstatus, 2048 - .cfi_offset hedeleg, 2056 - .cfi_offset hideleg, 2060 - .cfi_offset hie, 2064 - .cfi_offset htvec, 2068 - .cfi_offset hscratch, 2304 - .cfi_offset hepc, 2308 - .cfi_offset hcause, 2312 - .cfi_offset hbadaddr, 2316 - .cfi_offset hip, 2320 .cfi_offset mbase, 3584 .cfi_offset mbound, 3588 .cfi_offset mibase, 3592 diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s index af0fc4e14a42..aff34e9a3470 100644 --- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s +++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s @@ -249,16 +249,6 @@ csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11 csr dscratch # 0x7b2 in 1.10, but the value is dscratch0 since 1.11 - csr hstatus # 0x200, dropped in 1.10 - csr hedeleg # 0x202, dropped in 1.10 - csr hideleg # 0x203, dropped in 1.10 - csr hie # 0x204, dropped in 1.10 - csr htvec # 0x205, dropped in 1.10 - csr hscratch # 0x240, dropped in 1.10 - csr hepc # 0x241, dropped in 1.10 - csr hcause # 0x242, dropped in 1.10 - csr hbadaddr # 0x243, dropped in 1.10 - csr hip # 0x244, dropped in 1.10 csr mbase # 0x380, dropped in 1.10 csr mbound # 0x381, dropped in 1.10 csr mibase # 0x382, dropped in 1.10 diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l index fbba6e525670..5f7a8d60d7dd 100644 --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l @@ -5,16 +5,6 @@ .*Warning: invalid CSR `sptbr' for the privileged spec `1.10' .*Warning: invalid CSR `mbadaddr' for the privileged spec `1.10' .*Warning: invalid CSR `mucounteren' for the privileged spec `1.10' -.*Warning: invalid CSR `hstatus' for the privileged spec `1.10' -.*Warning: invalid CSR `hedeleg' for the privileged spec `1.10' -.*Warning: invalid CSR `hideleg' for the privileged spec `1.10' -.*Warning: invalid CSR `hie' for the privileged spec `1.10' -.*Warning: invalid CSR `htvec' for the privileged spec `1.10' -.*Warning: invalid CSR `hscratch' for the privileged spec `1.10' -.*Warning: invalid CSR `hepc' for the privileged spec `1.10' -.*Warning: invalid CSR `hcause' for the privileged spec `1.10' -.*Warning: invalid CSR `hbadaddr' for the privileged spec `1.10' -.*Warning: invalid CSR `hip' for the privileged spec `1.10' .*Warning: invalid CSR `mbase' for the privileged spec `1.10' .*Warning: invalid CSR `mbound' for the privileged spec `1.10' .*Warning: invalid CSR `mibase' for the privileged spec `1.10' diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l index 68354ce25ce9..888cbb211d7f 100644 --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l @@ -4,16 +4,6 @@ .*Warning: invalid CSR `sptbr' for the privileged spec `1.11' .*Warning: invalid CSR `mbadaddr' for the privileged spec `1.11' .*Warning: invalid CSR `mucounteren' for the privileged spec `1.11' -.*Warning: invalid CSR `hstatus' for the privileged spec `1.11' -.*Warning: invalid CSR `hedeleg' for the privileged spec `1.11' -.*Warning: invalid CSR `hideleg' for the privileged spec `1.11' -.*Warning: invalid CSR `hie' for the privileged spec `1.11' -.*Warning: invalid CSR `htvec' for the privileged spec `1.11' -.*Warning: invalid CSR `hscratch' for the privileged spec `1.11' -.*Warning: invalid CSR `hepc' for the privileged spec `1.11' -.*Warning: invalid CSR `hcause' for the privileged spec `1.11' -.*Warning: invalid CSR `hbadaddr' for the privileged spec `1.11' -.*Warning: invalid CSR `hip' for the privileged spec `1.11' .*Warning: invalid CSR `mbase' for the privileged spec `1.11' .*Warning: invalid CSR `mbound' for the privileged spec `1.11' .*Warning: invalid CSR `mibase' for the privileged spec `1.11' diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d index ee4f405adaae..44e9af63a31f 100644 --- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d @@ -225,16 +225,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp [ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval [ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,0x320 -[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,0x200 -[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,0x202 -[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,0x203 -[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,0x204 -[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,0x205 -[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,0x240 -[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,0x241 -[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,0x242 -[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,0x243 -[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,0x244 [ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,0x380 [ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,0x381 [ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,0x382 diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d index 185e84dbd70f..c456cb945689 100644 --- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d @@ -225,16 +225,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp [ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval [ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit -[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,0x200 -[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,0x202 -[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,0x203 -[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,0x204 -[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,0x205 -[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,0x240 -[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,0x241 -[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,0x242 -[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,0x243 -[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,0x244 [ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,0x380 [ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,0x381 [ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,0x382 diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d index 0e0ba7797014..432aecc6691c 100644 --- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d @@ -225,16 +225,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,sptbr [ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mbadaddr [ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mucounteren -[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,hstatus -[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg -[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,hideleg -[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,hie -[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,htvec -[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,hscratch -[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,hepc -[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,hcause -[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr -[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,hip [ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,mbase [ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,mbound [ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,mibase diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s index 5cf3ebc1b3e0..8c507fec4bb9 100644 --- a/gas/testsuite/gas/riscv/priv-reg.s +++ b/gas/testsuite/gas/riscv/priv-reg.s @@ -234,16 +234,6 @@ csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10 csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11 - csr hstatus # 0x200, dropped in 1.10 - csr hedeleg # 0x202, dropped in 1.10 - csr hideleg # 0x203, dropped in 1.10 - csr hie # 0x204, dropped in 1.10 - csr htvec # 0x205, dropped in 1.10 - csr hscratch # 0x240, dropped in 1.10 - csr hepc # 0x241, dropped in 1.10 - csr hcause # 0x242, dropped in 1.10 - csr hbadaddr # 0x243, dropped in 1.10 - csr hip # 0x244, dropped in 1.10 csr mbase # 0x380, dropped in 1.10 csr mbound # 0x381, dropped in 1.10 csr mibase # 0x382, dropped in 1.10 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index a6ece366fa48..2486f13c9fd3 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2211,16 +2211,6 @@ #define CSR_MHPMEVENT29 0x33d #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f -#define CSR_HSTATUS 0x200 -#define CSR_HEDELEG 0x202 -#define CSR_HIDELEG 0x203 -#define CSR_HIE 0x204 -#define CSR_HTVEC 0x205 -#define CSR_HSCRATCH 0x240 -#define CSR_HEPC 0x241 -#define CSR_HCAUSE 0x242 -#define CSR_HBADADDR 0x243 -#define CSR_HIP 0x244 #define CSR_MBASE 0x380 #define CSR_MBOUND 0x381 #define CSR_MIBASE 0x382 @@ -2781,16 +2771,6 @@ DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) /* Dropped CSRs. */ -DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) -DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) -DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) -DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) -DECLARE_CSR(htvec, CSR_HTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) -DECLARE_CSR(hscratch, CSR_HSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) -DECLARE_CSR(hepc, CSR_HEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) -DECLARE_CSR(hcause, CSR_HCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) -DECLARE_CSR(hbadaddr, CSR_HBADADDR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) -DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) -- 2.30.2 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v1 1/4] RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/tests 2021-12-21 2:34 ` [v1 1/4] RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/tests Vineet Gupta @ 2021-12-24 8:23 ` Nelson Chu 0 siblings, 0 replies; 14+ messages in thread From: Nelson Chu @ 2021-12-24 8:23 UTC (permalink / raw) To: Vineet Gupta; +Cc: Binutils, Kito Cheng, Jim Wilson, Palmer Dabbelt LGTM, committed. Thanks Nelson On Tue, Dec 21, 2021 at 10:34 AM Vineet Gupta <vineetg@rivosinc.com> wrote: > > This makes way for a clean 1.12 based Hypervisor Ext support. > > There are no known implementors of 1.9.1 H-ext. (Per Jim, kendryte k210 > is based on priv spec 1.9.1, but it seems unlikely that they implemented > H-ext). > > Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> > --- > gas/testsuite/gas/riscv/csr-dw-regnums.d | 10 ---------- > gas/testsuite/gas/riscv/csr-dw-regnums.s | 10 ---------- > .../gas/riscv/priv-reg-fail-read-only-01.s | 10 ---------- > .../gas/riscv/priv-reg-fail-version-1p10.l | 10 ---------- > .../gas/riscv/priv-reg-fail-version-1p11.l | 10 ---------- > .../gas/riscv/priv-reg-version-1p10.d | 10 ---------- > .../gas/riscv/priv-reg-version-1p11.d | 10 ---------- > .../gas/riscv/priv-reg-version-1p9p1.d | 10 ---------- > gas/testsuite/gas/riscv/priv-reg.s | 10 ---------- > include/opcode/riscv-opc.h | 20 ------------------- > 10 files changed, 110 deletions(-) > > diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d > index de17ad81fbde..ea0a445c39ce 100644 > --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d > +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d > @@ -229,16 +229,6 @@ Contents of the .* section: > DW_CFA_offset_extended_sf: r4925 \(mhpmevent29\) at cfa\+3316 > DW_CFA_offset_extended_sf: r4926 \(mhpmevent30\) at cfa\+3320 > DW_CFA_offset_extended_sf: r4927 \(mhpmevent31\) at cfa\+3324 > - DW_CFA_offset_extended_sf: r4608 \(hstatus\) at cfa\+2048 > - DW_CFA_offset_extended_sf: r4610 \(hedeleg\) at cfa\+2056 > - DW_CFA_offset_extended_sf: r4611 \(hideleg\) at cfa\+2060 > - DW_CFA_offset_extended_sf: r4612 \(hie\) at cfa\+2064 > - DW_CFA_offset_extended_sf: r4613 \(htvec\) at cfa\+2068 > - DW_CFA_offset_extended_sf: r4672 \(hscratch\) at cfa\+2304 > - DW_CFA_offset_extended_sf: r4673 \(hepc\) at cfa\+2308 > - DW_CFA_offset_extended_sf: r4674 \(hcause\) at cfa\+2312 > - DW_CFA_offset_extended_sf: r4675 \(hbadaddr\) at cfa\+2316 > - DW_CFA_offset_extended_sf: r4676 \(hip\) at cfa\+2320 > DW_CFA_offset_extended_sf: r4992 \(mbase\) at cfa\+3584 > DW_CFA_offset_extended_sf: r4993 \(mbound\) at cfa\+3588 > DW_CFA_offset_extended_sf: r4994 \(mibase\) at cfa\+3592 > diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s > index ecc801469763..549475d650e8 100644 > --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s > +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s > @@ -220,16 +220,6 @@ _start: > .cfi_offset mhpmevent30, 3320 > .cfi_offset mhpmevent31, 3324 > # dropped > - .cfi_offset hstatus, 2048 > - .cfi_offset hedeleg, 2056 > - .cfi_offset hideleg, 2060 > - .cfi_offset hie, 2064 > - .cfi_offset htvec, 2068 > - .cfi_offset hscratch, 2304 > - .cfi_offset hepc, 2308 > - .cfi_offset hcause, 2312 > - .cfi_offset hbadaddr, 2316 > - .cfi_offset hip, 2320 > .cfi_offset mbase, 3584 > .cfi_offset mbound, 3588 > .cfi_offset mibase, 3592 > diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s > index af0fc4e14a42..aff34e9a3470 100644 > --- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s > +++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s > @@ -249,16 +249,6 @@ > csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11 > csr dscratch # 0x7b2 in 1.10, but the value is dscratch0 since 1.11 > > - csr hstatus # 0x200, dropped in 1.10 > - csr hedeleg # 0x202, dropped in 1.10 > - csr hideleg # 0x203, dropped in 1.10 > - csr hie # 0x204, dropped in 1.10 > - csr htvec # 0x205, dropped in 1.10 > - csr hscratch # 0x240, dropped in 1.10 > - csr hepc # 0x241, dropped in 1.10 > - csr hcause # 0x242, dropped in 1.10 > - csr hbadaddr # 0x243, dropped in 1.10 > - csr hip # 0x244, dropped in 1.10 > csr mbase # 0x380, dropped in 1.10 > csr mbound # 0x381, dropped in 1.10 > csr mibase # 0x382, dropped in 1.10 > diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l > index fbba6e525670..5f7a8d60d7dd 100644 > --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l > +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l > @@ -5,16 +5,6 @@ > .*Warning: invalid CSR `sptbr' for the privileged spec `1.10' > .*Warning: invalid CSR `mbadaddr' for the privileged spec `1.10' > .*Warning: invalid CSR `mucounteren' for the privileged spec `1.10' > -.*Warning: invalid CSR `hstatus' for the privileged spec `1.10' > -.*Warning: invalid CSR `hedeleg' for the privileged spec `1.10' > -.*Warning: invalid CSR `hideleg' for the privileged spec `1.10' > -.*Warning: invalid CSR `hie' for the privileged spec `1.10' > -.*Warning: invalid CSR `htvec' for the privileged spec `1.10' > -.*Warning: invalid CSR `hscratch' for the privileged spec `1.10' > -.*Warning: invalid CSR `hepc' for the privileged spec `1.10' > -.*Warning: invalid CSR `hcause' for the privileged spec `1.10' > -.*Warning: invalid CSR `hbadaddr' for the privileged spec `1.10' > -.*Warning: invalid CSR `hip' for the privileged spec `1.10' > .*Warning: invalid CSR `mbase' for the privileged spec `1.10' > .*Warning: invalid CSR `mbound' for the privileged spec `1.10' > .*Warning: invalid CSR `mibase' for the privileged spec `1.10' > diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l > index 68354ce25ce9..888cbb211d7f 100644 > --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l > +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l > @@ -4,16 +4,6 @@ > .*Warning: invalid CSR `sptbr' for the privileged spec `1.11' > .*Warning: invalid CSR `mbadaddr' for the privileged spec `1.11' > .*Warning: invalid CSR `mucounteren' for the privileged spec `1.11' > -.*Warning: invalid CSR `hstatus' for the privileged spec `1.11' > -.*Warning: invalid CSR `hedeleg' for the privileged spec `1.11' > -.*Warning: invalid CSR `hideleg' for the privileged spec `1.11' > -.*Warning: invalid CSR `hie' for the privileged spec `1.11' > -.*Warning: invalid CSR `htvec' for the privileged spec `1.11' > -.*Warning: invalid CSR `hscratch' for the privileged spec `1.11' > -.*Warning: invalid CSR `hepc' for the privileged spec `1.11' > -.*Warning: invalid CSR `hcause' for the privileged spec `1.11' > -.*Warning: invalid CSR `hbadaddr' for the privileged spec `1.11' > -.*Warning: invalid CSR `hip' for the privileged spec `1.11' > .*Warning: invalid CSR `mbase' for the privileged spec `1.11' > .*Warning: invalid CSR `mbound' for the privileged spec `1.11' > .*Warning: invalid CSR `mibase' for the privileged spec `1.11' > diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d > index ee4f405adaae..44e9af63a31f 100644 > --- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d > +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d > @@ -225,16 +225,6 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp > [ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval > [ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,0x320 > -[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,0x200 > -[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,0x202 > -[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,0x203 > -[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,0x204 > -[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,0x205 > -[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,0x240 > -[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,0x241 > -[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,0x242 > -[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,0x243 > -[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,0x244 > [ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,0x380 > [ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,0x381 > [ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,0x382 > diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d > index 185e84dbd70f..c456cb945689 100644 > --- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d > +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d > @@ -225,16 +225,6 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp > [ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval > [ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit > -[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,0x200 > -[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,0x202 > -[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,0x203 > -[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,0x204 > -[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,0x205 > -[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,0x240 > -[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,0x241 > -[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,0x242 > -[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,0x243 > -[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,0x244 > [ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,0x380 > [ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,0x381 > [ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,0x382 > diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d > index 0e0ba7797014..432aecc6691c 100644 > --- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d > +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d > @@ -225,16 +225,6 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,sptbr > [ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mbadaddr > [ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mucounteren > -[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,hstatus > -[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg > -[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,hideleg > -[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,hie > -[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,htvec > -[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,hscratch > -[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,hepc > -[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,hcause > -[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr > -[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,hip > [ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,mbase > [ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,mbound > [ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,mibase > diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s > index 5cf3ebc1b3e0..8c507fec4bb9 100644 > --- a/gas/testsuite/gas/riscv/priv-reg.s > +++ b/gas/testsuite/gas/riscv/priv-reg.s > @@ -234,16 +234,6 @@ > csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10 > csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11 > > - csr hstatus # 0x200, dropped in 1.10 > - csr hedeleg # 0x202, dropped in 1.10 > - csr hideleg # 0x203, dropped in 1.10 > - csr hie # 0x204, dropped in 1.10 > - csr htvec # 0x205, dropped in 1.10 > - csr hscratch # 0x240, dropped in 1.10 > - csr hepc # 0x241, dropped in 1.10 > - csr hcause # 0x242, dropped in 1.10 > - csr hbadaddr # 0x243, dropped in 1.10 > - csr hip # 0x244, dropped in 1.10 > csr mbase # 0x380, dropped in 1.10 > csr mbound # 0x381, dropped in 1.10 > csr mibase # 0x382, dropped in 1.10 > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > index a6ece366fa48..2486f13c9fd3 100644 > --- a/include/opcode/riscv-opc.h > +++ b/include/opcode/riscv-opc.h > @@ -2211,16 +2211,6 @@ > #define CSR_MHPMEVENT29 0x33d > #define CSR_MHPMEVENT30 0x33e > #define CSR_MHPMEVENT31 0x33f > -#define CSR_HSTATUS 0x200 > -#define CSR_HEDELEG 0x202 > -#define CSR_HIDELEG 0x203 > -#define CSR_HIE 0x204 > -#define CSR_HTVEC 0x205 > -#define CSR_HSCRATCH 0x240 > -#define CSR_HEPC 0x241 > -#define CSR_HCAUSE 0x242 > -#define CSR_HBADADDR 0x243 > -#define CSR_HIP 0x244 > #define CSR_MBASE 0x380 > #define CSR_MBOUND 0x381 > #define CSR_MIBASE 0x382 > @@ -2781,16 +2771,6 @@ DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR > DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) > DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) > /* Dropped CSRs. */ > -DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) > -DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) > -DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) > -DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) > -DECLARE_CSR(htvec, CSR_HTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) > -DECLARE_CSR(hscratch, CSR_HSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) > -DECLARE_CSR(hepc, CSR_HEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) > -DECLARE_CSR(hcause, CSR_HCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) > -DECLARE_CSR(hbadaddr, CSR_HBADADDR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) > -DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) > DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) > DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) > DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) > -- > 2.30.2 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* [v1 2/4] RISC-V: Hypervisor ext: support Privileged Spec 1.12 2021-12-21 2:34 [v1 0/4]riscv/binutils support Hypervisor Extension Vineet Gupta 2021-12-21 2:34 ` [v1 1/4] RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/tests Vineet Gupta @ 2021-12-21 2:34 ` Vineet Gupta 2021-12-24 8:40 ` Nelson Chu 2022-01-04 8:09 ` Jan Beulich 2021-12-21 2:34 ` [v1 3/4] RISC-V: Hypervisor Ext: Add tests Vineet Gupta ` (2 subsequent siblings) 4 siblings, 2 replies; 14+ messages in thread From: Vineet Gupta @ 2021-12-21 2:34 UTC (permalink / raw) To: Binutils, Nelson Chu; +Cc: Kito Cheng, jim.wilson.gcc, palmer, Vineet Gupta This is the Hypervisor Extension 1.0 - Hypervisor Memory-Management Instructions HFENCE.VVMA, HFENCE.GVMA, - Hypervisor Virtual Machine Load and Store Instructions HLV.B, HLV.BU, HSV.B, HLV.H, HLV.HU, HLVX.HU, HSB.H, HLV.W, HLV.WU, HLVX.WU, HSV.W, HLV.D, HSV.D - Hypervisor CSRs (some new, some address changed) hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip, htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah, vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp, Note that following were added already as part of svinval extension support: HINVAL.GVMA, HINVAL.VVMA Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> --- bfd/cpu-riscv.c | 1 + bfd/cpu-riscv.h | 1 + bfd/elfxx-riscv.c | 6 +++ include/opcode/riscv-opc.h | 90 ++++++++++++++++++++++++++++++++++++++ include/opcode/riscv.h | 2 + opcodes/riscv-opc.c | 26 ++++++++++- 6 files changed, 124 insertions(+), 2 deletions(-) diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c index 813f2c3df8d9..5038029ce014 100644 --- a/bfd/cpu-riscv.c +++ b/bfd/cpu-riscv.c @@ -117,6 +117,7 @@ const struct riscv_spec riscv_priv_specs[] = {"1.9.1", PRIV_SPEC_CLASS_1P9P1}, {"1.10", PRIV_SPEC_CLASS_1P10}, {"1.11", PRIV_SPEC_CLASS_1P11}, + {"1.12", PRIV_SPEC_CLASS_1P12}, }; /* Get the corresponding CSR version class by giving privilege diff --git a/bfd/cpu-riscv.h b/bfd/cpu-riscv.h index ed5ee7e60d58..b251d6312b82 100644 --- a/bfd/cpu-riscv.h +++ b/bfd/cpu-riscv.h @@ -32,6 +32,7 @@ enum riscv_spec_class PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P11, + PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT, }; diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index c575ab093f96..074e637dd590 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -2406,6 +2406,12 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, || riscv_subset_supports (rps, "zve32f")); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); + case INSN_CLASS_SVINVAL_AND_H: + return riscv_subset_supports (rps, "svinval"); + /* TODO: currently Hypervisor extension is enabled by default. + switch to its own arch string when implemented. */ + case INSN_CLASS_H: + return riscv_subset_supports (rps, "i"); default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 2486f13c9fd3..da9ef81d33f5 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -1987,6 +1987,22 @@ #define MASK_VDOTUVV 0xfc00707f #define MATCH_VFDOTVV 0xe4001057 #define MASK_VFDOTVV 0xfc00707f +#define MASK_HLV 0xfff0707f +#define MATCH_HLVB 0x60004073 +#define MATCH_HLVBU 0x60104073 +#define MATCH_HLVH 0x64004073 +#define MATCH_HLVHU 0x64104073 +#define MATCH_HLVXHU 0x64304073 +#define MATCH_HLVW 0x68004073 +#define MATCH_HLVXWU 0x68304073 +#define MATCH_HLVWU 0x68104073 +#define MATCH_HLVD 0x6c004073 + +#define MASK_HSV 0xfe007fff +#define MATCH_HSVB 0x62004073 +#define MATCH_HSVH 0x66004073 +#define MATCH_HSVW 0x6a004073 +#define MATCH_HSVD 0x6e004073 /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -1994,6 +2010,10 @@ #define MASK_SFENCE_W_INVAL 0xffffffff #define MATCH_SFENCE_INVAL_IR 0x18100073 #define MASK_SFENCE_INVAL_IR 0xffffffff +#define MASK_HFENCE_VVMA 0xfe007fff +#define MATCH_HFENCE_VVMA 0x22000073 +#define MASK_HFENCE_GVMA 0xfe007fff +#define MATCH_HFENCE_GVMA 0x62000073 #define MATCH_HINVAL_VVMA 0x26000073 #define MASK_HINVAL_VVMA 0xfe007fff #define MATCH_HINVAL_GVMA 0x66000073 @@ -2211,6 +2231,33 @@ #define CSR_MHPMEVENT29 0x33d #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f +/* Hypervisor Extension v1.0 (Privileged spec 1.12). */ +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HIE 0x604 +#define CSR_HCOUNTEREN 0x606 +#define CSR_HGEIE 0x607 +#define CSR_HTVAL 0x643 +#define CSR_HIP 0x644 +#define CSR_HVIP 0x645 +#define CSR_HTINST 0x64a +#define CSR_HGEIP 0xe12 +#define CSR_HENVCFG 0x60a +#define CSR_HENVCFGH 0x61a +#define CSR_HGATP 0x680 +#define CSR_HCONTEXT 0x6a8 +#define CSR_HTIMEDELTA 0x605 +#define CSR_HTIMEDELTAH 0x615 +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSATP 0x280 #define CSR_MBASE 0x380 #define CSR_MBOUND 0x381 #define CSR_MIBASE 0x382 @@ -2553,8 +2600,23 @@ DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA) DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL) DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR) +DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE) +DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE) DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA) DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA) +DECLARE_INSN(hlv_b, MATCH_HLVB, MASK_HLV) +DECLARE_INSN(hlv_h, MATCH_HLVH, MASK_HLV) +DECLARE_INSN(hlv_w, MATCH_HLVW, MASK_HLV) +DECLARE_INSN(hlv_d, MATCH_HLVD, MASK_HLV) +DECLARE_INSN(hlv_bu, MATCH_HLVBU, MASK_HLV) +DECLARE_INSN(hlv_hu, MATCH_HLVHU, MASK_HLV) +DECLARE_INSN(hlv_wu, MATCH_HLVWU, MASK_HLV) +DECLARE_INSN(hlvx_hu, MATCH_HLVXHU, MASK_HLV) +DECLARE_INSN(hlvx_wu, MATCH_HLVXWU, MASK_HLV) +DECLARE_INSN(hsv_b, MATCH_HSVB, MASK_HSV) +DECLARE_INSN(hsv_h, MATCH_HSVH, MASK_HSV) +DECLARE_INSN(hsv_w, MATCH_HSVW, MASK_HSV) +DECLARE_INSN(hsv_d, MATCH_HSVD, MASK_HSV) #endif /* DECLARE_INSN */ #ifdef DECLARE_CSR /* Privileged CSRs. */ @@ -2770,6 +2832,34 @@ DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +/* Hypervisor Ext v1.0 (Privileged spec 1.12). */ +/* TODO: Fix to CSR_CLASS_H when explicit h-ext arch string is introduced. */ +DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hcounteren, CSR_HCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hgeie, CSR_HGEIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(htval, CSR_HTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hvip, CSR_HVIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(htinst, CSR_HTINST, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hgeip, CSR_HGEIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(henvcfg, CSR_HENVCFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(henvcfgh, CSR_HENVCFGH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hgatp, CSR_HGATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(hcontext, CSR_HCONTEXT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(htimedelta, CSR_HTIMEDELTA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vsstatus, CSR_VSSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vsie, CSR_VSIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vstvec, CSR_VSTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vsscratch, CSR_VSSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vsepc, CSR_VSEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vscause, CSR_VSCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vstval, CSR_VSTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vsip, CSR_VSIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(vsatp, CSR_VSATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) /* Dropped CSRs. */ DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index cbc90b00008f..e054d0b18666 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -388,6 +388,8 @@ enum riscv_insn_class INSN_CLASS_V, INSN_CLASS_ZVEF, INSN_CLASS_SVINVAL, + INSN_CLASS_H, + INSN_CLASS_SVINVAL_AND_H, }; /* This structure holds information for a particular instruction. */ diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index f220006fc93f..f5f4b9a28dcd 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1729,8 +1729,30 @@ const struct riscv_opcode riscv_opcodes[] = {"sinval.vma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 }, {"sfence.w.inval", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 }, {"sfence.inval.ir", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR, match_opcode, 0 }, -{"hinval.vvma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA, match_opcode, 0 }, -{"hinval.gvma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA, match_opcode, 0 }, + +/* Svinval instructions + Hypervisor Ext v1.0. */ +{"hinval.vvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA, match_opcode, 0 }, +{"hinval.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA, match_opcode, 0 }, +{"hfence.vvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA, match_opcode, 0 }, +{"hfence.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS1|MASK_RS2, match_opcode, 0 }, +{"hfence.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "s", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS2, match_opcode, 0 }, +{"hfence.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA, match_opcode, 0 }, + +/* Hypervisor Ext v1.0 (Privileged spec 1.12). */ +{"hlv.b", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVB, MASK_HLV, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"hlv.bu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVBU, MASK_HLV, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"hlv.h", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVH, MASK_HLV, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"hlv.hu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVHU, MASK_HLV, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"hlvx.hu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVXHU, MASK_HLV, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"hlv.w", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVW, MASK_HLV, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"hlv.wu", 64, INSN_CLASS_H, "d,0(s)", MATCH_HLVWU, MASK_HLV, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"hlvx.wu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVXWU, MASK_HLV, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"hlv.d", 64, INSN_CLASS_H, "d,0(s)", MATCH_HLVD, MASK_HLV, match_opcode, INSN_DREF|INSN_8_BYTE }, + +{"hsv.b", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSVB, MASK_HSV, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"hsv.h", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSVH, MASK_HSV, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"hsv.w", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSVW, MASK_HSV, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSVD, MASK_HSV, match_opcode, INSN_DREF|INSN_8_BYTE }, /* Terminate the list. */ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} -- 2.30.2 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v1 2/4] RISC-V: Hypervisor ext: support Privileged Spec 1.12 2021-12-21 2:34 ` [v1 2/4] RISC-V: Hypervisor ext: support Privileged Spec 1.12 Vineet Gupta @ 2021-12-24 8:40 ` Nelson Chu 2022-01-04 8:09 ` Jan Beulich 1 sibling, 0 replies; 14+ messages in thread From: Nelson Chu @ 2021-12-24 8:40 UTC (permalink / raw) To: Vineet Gupta; +Cc: Binutils, Kito Cheng, Jim Wilson, Palmer Dabbelt LGTM, just some minor issues that I didn't think of before. So I rebased the remaining three patches into the one, and then committed with some minor changes, and the missing ChangLogs. Thanks Nelson On Tue, Dec 21, 2021 at 10:34 AM Vineet Gupta <vineetg@rivosinc.com> wrote: > > This is the Hypervisor Extension 1.0 > > - Hypervisor Memory-Management Instructions > HFENCE.VVMA, HFENCE.GVMA, > > - Hypervisor Virtual Machine Load and Store Instructions > HLV.B, HLV.BU, HSV.B, > HLV.H, HLV.HU, HLVX.HU, HSB.H, > HLV.W, HLV.WU, HLVX.WU, HSV.W, > HLV.D, HSV.D > > - Hypervisor CSRs (some new, some address changed) > hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip, > htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah, > vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp, > > Note that following were added already as part of svinval extension > support: > HINVAL.GVMA, HINVAL.VVMA > > Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> > --- > bfd/cpu-riscv.c | 1 + > bfd/cpu-riscv.h | 1 + > bfd/elfxx-riscv.c | 6 +++ > include/opcode/riscv-opc.h | 90 ++++++++++++++++++++++++++++++++++++++ > include/opcode/riscv.h | 2 + > opcodes/riscv-opc.c | 26 ++++++++++- > 6 files changed, 124 insertions(+), 2 deletions(-) > > diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c > index 813f2c3df8d9..5038029ce014 100644 > --- a/bfd/cpu-riscv.c > +++ b/bfd/cpu-riscv.c > @@ -117,6 +117,7 @@ const struct riscv_spec riscv_priv_specs[] = > {"1.9.1", PRIV_SPEC_CLASS_1P9P1}, > {"1.10", PRIV_SPEC_CLASS_1P10}, > {"1.11", PRIV_SPEC_CLASS_1P11}, > + {"1.12", PRIV_SPEC_CLASS_1P12}, > }; > > /* Get the corresponding CSR version class by giving privilege > diff --git a/bfd/cpu-riscv.h b/bfd/cpu-riscv.h > index ed5ee7e60d58..b251d6312b82 100644 > --- a/bfd/cpu-riscv.h > +++ b/bfd/cpu-riscv.h > @@ -32,6 +32,7 @@ enum riscv_spec_class > PRIV_SPEC_CLASS_1P9P1, > PRIV_SPEC_CLASS_1P10, > PRIV_SPEC_CLASS_1P11, > + PRIV_SPEC_CLASS_1P12, > PRIV_SPEC_CLASS_DRAFT, > }; > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index c575ab093f96..074e637dd590 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -2406,6 +2406,12 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, > || riscv_subset_supports (rps, "zve32f")); > case INSN_CLASS_SVINVAL: > return riscv_subset_supports (rps, "svinval"); > + case INSN_CLASS_SVINVAL_AND_H: > + return riscv_subset_supports (rps, "svinval"); > + /* TODO: currently Hypervisor extension is enabled by default. > + switch to its own arch string when implemented. */ > + case INSN_CLASS_H: > + return riscv_subset_supports (rps, "i"); For now we don't have `h' in the arch string, so just replacing the INSN_CLASS_H with INSN_CLASS_I should be enough. We could add the new INSN_CLASS_SVINVAL_AND_H and INSN_CLASS_H in the future patches, when the canonical order of h is proposed and mentioned in the ISA spec. > default: > rps->error_handler > (_("internal: unreachable INSN_CLASS_*")); > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > index 2486f13c9fd3..da9ef81d33f5 100644 > --- a/include/opcode/riscv-opc.h > +++ b/include/opcode/riscv-opc.h > @@ -1987,6 +1987,22 @@ > #define MASK_VDOTUVV 0xfc00707f > #define MATCH_VFDOTVV 0xe4001057 > #define MASK_VFDOTVV 0xfc00707f > +#define MASK_HLV 0xfff0707f > +#define MATCH_HLVB 0x60004073 > +#define MATCH_HLVBU 0x60104073 > +#define MATCH_HLVH 0x64004073 > +#define MATCH_HLVHU 0x64104073 > +#define MATCH_HLVXHU 0x64304073 > +#define MATCH_HLVW 0x68004073 > +#define MATCH_HLVXWU 0x68304073 > +#define MATCH_HLVWU 0x68104073 > +#define MATCH_HLVD 0x6c004073 > + > +#define MASK_HSV 0xfe007fff > +#define MATCH_HSVB 0x62004073 > +#define MATCH_HSVH 0x66004073 > +#define MATCH_HSVW 0x6a004073 > +#define MATCH_HSVD 0x6e004073 We are used to writing a pair of MATCH and MASK for one instruction, so keeping them the same as the others should be better. > /* Svinval instruction. */ > #define MATCH_SINVAL_VMA 0x16000073 > #define MASK_SINVAL_VMA 0xfe007fff > @@ -1994,6 +2010,10 @@ > #define MASK_SFENCE_W_INVAL 0xffffffff > #define MATCH_SFENCE_INVAL_IR 0x18100073 > #define MASK_SFENCE_INVAL_IR 0xffffffff > +#define MASK_HFENCE_VVMA 0xfe007fff > +#define MATCH_HFENCE_VVMA 0x22000073 > +#define MASK_HFENCE_GVMA 0xfe007fff > +#define MATCH_HFENCE_GVMA 0x62000073 > #define MATCH_HINVAL_VVMA 0x26000073 > #define MASK_HINVAL_VVMA 0xfe007fff > #define MATCH_HINVAL_GVMA 0x66000073 > @@ -2211,6 +2231,33 @@ > #define CSR_MHPMEVENT29 0x33d > #define CSR_MHPMEVENT30 0x33e > #define CSR_MHPMEVENT31 0x33f > +/* Hypervisor Extension v1.0 (Privileged spec 1.12). */ > +#define CSR_HSTATUS 0x600 > +#define CSR_HEDELEG 0x602 > +#define CSR_HIDELEG 0x603 > +#define CSR_HIE 0x604 > +#define CSR_HCOUNTEREN 0x606 > +#define CSR_HGEIE 0x607 > +#define CSR_HTVAL 0x643 > +#define CSR_HIP 0x644 > +#define CSR_HVIP 0x645 > +#define CSR_HTINST 0x64a > +#define CSR_HGEIP 0xe12 > +#define CSR_HENVCFG 0x60a > +#define CSR_HENVCFGH 0x61a > +#define CSR_HGATP 0x680 > +#define CSR_HCONTEXT 0x6a8 > +#define CSR_HTIMEDELTA 0x605 > +#define CSR_HTIMEDELTAH 0x615 > +#define CSR_VSSTATUS 0x200 > +#define CSR_VSIE 0x204 > +#define CSR_VSTVEC 0x205 > +#define CSR_VSSCRATCH 0x240 > +#define CSR_VSEPC 0x241 > +#define CSR_VSCAUSE 0x242 > +#define CSR_VSTVAL 0x243 > +#define CSR_VSIP 0x244 > +#define CSR_VSATP 0x280 > #define CSR_MBASE 0x380 > #define CSR_MBOUND 0x381 > #define CSR_MIBASE 0x382 > @@ -2553,8 +2600,23 @@ DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) > DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA) > DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL) > DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR) > +DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE) > +DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE) > DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA) > DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA) > +DECLARE_INSN(hlv_b, MATCH_HLVB, MASK_HLV) > +DECLARE_INSN(hlv_h, MATCH_HLVH, MASK_HLV) > +DECLARE_INSN(hlv_w, MATCH_HLVW, MASK_HLV) > +DECLARE_INSN(hlv_d, MATCH_HLVD, MASK_HLV) > +DECLARE_INSN(hlv_bu, MATCH_HLVBU, MASK_HLV) > +DECLARE_INSN(hlv_hu, MATCH_HLVHU, MASK_HLV) > +DECLARE_INSN(hlv_wu, MATCH_HLVWU, MASK_HLV) > +DECLARE_INSN(hlvx_hu, MATCH_HLVXHU, MASK_HLV) > +DECLARE_INSN(hlvx_wu, MATCH_HLVXWU, MASK_HLV) > +DECLARE_INSN(hsv_b, MATCH_HSVB, MASK_HSV) > +DECLARE_INSN(hsv_h, MATCH_HSVH, MASK_HSV) > +DECLARE_INSN(hsv_w, MATCH_HSVW, MASK_HSV) > +DECLARE_INSN(hsv_d, MATCH_HSVD, MASK_HSV) > #endif /* DECLARE_INSN */ > #ifdef DECLARE_CSR > /* Privileged CSRs. */ > @@ -2770,6 +2832,34 @@ DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR > DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) > DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) > DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) > +/* Hypervisor Ext v1.0 (Privileged spec 1.12). */ > +/* TODO: Fix to CSR_CLASS_H when explicit h-ext arch string is introduced. */ > +DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(hcounteren, CSR_HCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(hgeie, CSR_HGEIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(htval, CSR_HTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(hvip, CSR_HVIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(htinst, CSR_HTINST, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(hgeip, CSR_HGEIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(henvcfg, CSR_HENVCFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(henvcfgh, CSR_HENVCFGH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) Should be CSR_CLASS_I_32. > +DECLARE_CSR(hgatp, CSR_HGATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(hcontext, CSR_HCONTEXT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(htimedelta, CSR_HTIMEDELTA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) Likewise, CSR_CLASS_I_32. > +DECLARE_CSR(vsstatus, CSR_VSSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(vsie, CSR_VSIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(vstvec, CSR_VSTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(vsscratch, CSR_VSSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(vsepc, CSR_VSEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(vscause, CSR_VSCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(vstval, CSR_VSTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(vsip, CSR_VSIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > +DECLARE_CSR(vsatp, CSR_VSATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) > /* Dropped CSRs. */ > DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) > DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index cbc90b00008f..e054d0b18666 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -388,6 +388,8 @@ enum riscv_insn_class > INSN_CLASS_V, > INSN_CLASS_ZVEF, > INSN_CLASS_SVINVAL, > + INSN_CLASS_H, > + INSN_CLASS_SVINVAL_AND_H, > }; > > /* This structure holds information for a particular instruction. */ > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index f220006fc93f..f5f4b9a28dcd 100644. > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -1729,8 +1729,30 @@ const struct riscv_opcode riscv_opcodes[] = > {"sinval.vma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 }, > {"sfence.w.inval", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 }, > {"sfence.inval.ir", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR, match_opcode, 0 }, > -{"hinval.vvma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA, match_opcode, 0 }, > -{"hinval.gvma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA, match_opcode, 0 }, > + > +/* Svinval instructions + Hypervisor Ext v1.0. */ > +{"hinval.vvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA, match_opcode, 0 }, > +{"hinval.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA, match_opcode, 0 }, > +{"hfence.vvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA, match_opcode, 0 }, > +{"hfence.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS1|MASK_RS2, match_opcode, 0 }, > +{"hfence.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "s", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS2, match_opcode, 0 }, > +{"hfence.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA, match_opcode, 0 }, I think hfence.gvma and hfence.vvma are not belonged to svinval extension, they are belonged to h extension. For the syntax "" and "s", we should add INSN_ALIAS at last. Besides, looks like the hfence.vvma should have the same assembly syntax with hfence.gvma. > +/* Hypervisor Ext v1.0 (Privileged spec 1.12). */ > +{"hlv.b", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVB, MASK_HLV, match_opcode, INSN_DREF|INSN_1_BYTE }, > +{"hlv.bu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVBU, MASK_HLV, match_opcode, INSN_DREF|INSN_1_BYTE }, > +{"hlv.h", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVH, MASK_HLV, match_opcode, INSN_DREF|INSN_2_BYTE }, > +{"hlv.hu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVHU, MASK_HLV, match_opcode, INSN_DREF|INSN_2_BYTE }, > +{"hlvx.hu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVXHU, MASK_HLV, match_opcode, INSN_DREF|INSN_2_BYTE }, > +{"hlv.w", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVW, MASK_HLV, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"hlv.wu", 64, INSN_CLASS_H, "d,0(s)", MATCH_HLVWU, MASK_HLV, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"hlvx.wu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVXWU, MASK_HLV, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"hlv.d", 64, INSN_CLASS_H, "d,0(s)", MATCH_HLVD, MASK_HLV, match_opcode, INSN_DREF|INSN_8_BYTE }, > + > +{"hsv.b", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSVB, MASK_HSV, match_opcode, INSN_DREF|INSN_1_BYTE }, > +{"hsv.h", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSVH, MASK_HSV, match_opcode, INSN_DREF|INSN_2_BYTE }, > +{"hsv.w", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSVW, MASK_HSV, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSVD, MASK_HSV, match_opcode, INSN_DREF|INSN_8_BYTE }, > > /* Terminate the list. */ > {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} > -- > 2.30.2 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v1 2/4] RISC-V: Hypervisor ext: support Privileged Spec 1.12 2021-12-21 2:34 ` [v1 2/4] RISC-V: Hypervisor ext: support Privileged Spec 1.12 Vineet Gupta 2021-12-24 8:40 ` Nelson Chu @ 2022-01-04 8:09 ` Jan Beulich 2022-01-04 18:10 ` Vineet Gupta 1 sibling, 1 reply; 14+ messages in thread From: Jan Beulich @ 2022-01-04 8:09 UTC (permalink / raw) To: Vineet Gupta; +Cc: Kito Cheng, Binutils, Nelson Chu > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -1729,8 +1729,30 @@ const struct riscv_opcode riscv_opcodes[] = > {"sinval.vma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 }, > {"sfence.w.inval", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 }, > {"sfence.inval.ir", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR, match_opcode, 0 }, > -{"hinval.vvma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA, match_opcode, 0 }, > -{"hinval.gvma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA, match_opcode, 0 }, > + > +/* Svinval instructions + Hypervisor Ext v1.0. */ > +{"hinval.vvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA, match_opcode, 0 }, > +{"hinval.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA, match_opcode, 0 }, > +{"hfence.vvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA, match_opcode, 0 }, > +{"hfence.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS1|MASK_RS2, match_opcode, 0 }, > +{"hfence.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "s", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS2, match_opcode, 0 }, > +{"hfence.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA, match_opcode, 0 }, I've not been able to spot pseudos with zero or one operands in the spec. Did I miss anything? Same actually appears to apply to the pre-existing sfence.vma ... Jan ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v1 2/4] RISC-V: Hypervisor ext: support Privileged Spec 1.12 2022-01-04 8:09 ` Jan Beulich @ 2022-01-04 18:10 ` Vineet Gupta 0 siblings, 0 replies; 14+ messages in thread From: Vineet Gupta @ 2022-01-04 18:10 UTC (permalink / raw) To: Jan Beulich; +Cc: Kito Cheng, Binutils, Nelson Chu, Anup Patel +CC Anup On 1/4/22 12:09 AM, Jan Beulich wrote: >> --- a/opcodes/riscv-opc.c >> +++ b/opcodes/riscv-opc.c >> @@ -1729,8 +1729,30 @@ const struct riscv_opcode riscv_opcodes[] = >> {"sinval.vma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 }, >> {"sfence.w.inval", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 }, >> {"sfence.inval.ir", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR, match_opcode, 0 }, >> -{"hinval.vvma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA, match_opcode, 0 }, >> -{"hinval.gvma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA, match_opcode, 0 }, >> + >> +/* Svinval instructions + Hypervisor Ext v1.0. */ >> +{"hinval.vvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA, match_opcode, 0 }, >> +{"hinval.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA, match_opcode, 0 }, >> +{"hfence.vvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA, match_opcode, 0 }, >> +{"hfence.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS1|MASK_RS2, match_opcode, 0 }, >> +{"hfence.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "s", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS2, match_opcode, 0 }, >> +{"hfence.gvma", 0, INSN_CLASS_SVINVAL_AND_H, "s,t", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA, match_opcode, 0 }, > I've not been able to spot pseudos with zero or one operands in the spec. > Did I miss anything? Same actually appears to apply to the pre-existing > sfence.vma ... Some of that information is there but scattered. e.g. last but one paragraph 8.3.2 "HFENCE.GVMA with rs1=x0 (and rs2 set to either x0 or the VMID)" When I did the RFC, I was pointed to a post from Anup from lkml [1] where the additional encodings were specified. Perhaps there needs to be a pull request to priv spec to explicit'ify it. [1] https://sourceware.org/pipermail/binutils/2021-December/118944.html ^ permalink raw reply [flat|nested] 14+ messages in thread
* [v1 3/4] RISC-V: Hypervisor Ext: Add tests 2021-12-21 2:34 [v1 0/4]riscv/binutils support Hypervisor Extension Vineet Gupta 2021-12-21 2:34 ` [v1 1/4] RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/tests Vineet Gupta 2021-12-21 2:34 ` [v1 2/4] RISC-V: Hypervisor ext: support Privileged Spec 1.12 Vineet Gupta @ 2021-12-21 2:34 ` Vineet Gupta 2022-01-04 8:12 ` Jan Beulich 2021-12-21 2:34 ` [v1 4/4] RISC-V: fix a comment for adding CSR entry and annotate switch-break Vineet Gupta 2021-12-23 1:35 ` [v1 0/4]riscv/binutils support Hypervisor Extension Palmer Dabbelt 4 siblings, 1 reply; 14+ messages in thread From: Vineet Gupta @ 2021-12-21 2:34 UTC (permalink / raw) To: Binutils, Nelson Chu; +Cc: Kito Cheng, jim.wilson.gcc, palmer, Vineet Gupta Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> --- gas/testsuite/gas/riscv/h-ext-32.d | 74 +++++++++++++++++++++++++ gas/testsuite/gas/riscv/h-ext-32.s | 64 +++++++++++++++++++++ gas/testsuite/gas/riscv/h-ext-64.d | 73 ++++++++++++++++++++++++ gas/testsuite/gas/riscv/h-ext-64.s | 63 +++++++++++++++++++++ gas/testsuite/gas/riscv/svinval-and-h.d | 15 +++++ gas/testsuite/gas/riscv/svinval-and-h.s | 5 ++ 6 files changed, 294 insertions(+) create mode 100644 gas/testsuite/gas/riscv/h-ext-32.d create mode 100644 gas/testsuite/gas/riscv/h-ext-32.s create mode 100644 gas/testsuite/gas/riscv/h-ext-64.d create mode 100644 gas/testsuite/gas/riscv/h-ext-64.s create mode 100644 gas/testsuite/gas/riscv/svinval-and-h.d create mode 100644 gas/testsuite/gas/riscv/svinval-and-h.s diff --git a/gas/testsuite/gas/riscv/h-ext-32.d b/gas/testsuite/gas/riscv/h-ext-32.d new file mode 100644 index 000000000000..8126c7bf85e2 --- /dev/null +++ b/gas/testsuite/gas/riscv/h-ext-32.d @@ -0,0 +1,74 @@ +#as: -march=rv32g -mpriv-spec=1.12 +#source: h-ext-32.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6015c573[ ]+hlv.bu[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+640645f3[ ]+hlv.h[ ]+a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+6415c5f3[ ]+hlv.hu[ ]+a1,\(a1\) +[ ]+[0-9a-f]+:[ ]+643645f3[ ]+hlvx.hu[ ]+a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+68064673[ ]+hlv.w[ ]+a2,\(a2\) +[ ]+[0-9a-f]+:[ ]+6836c673[ ]+hlvx.wu[ ]+a2,\(a3\) +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+66a5c073[ ]+hsv.h[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6aa5c073[ ]+hsv.w[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+60002573[ ]+csrr[ ]+a0,hstatus +[ ]+[0-9a-f]+:[ ]+60059073[ ]+csrw[ ]+hstatus,a1 +[ ]+[0-9a-f]+:[ ]+60202573[ ]+csrr[ ]+a0,hedeleg +[ ]+[0-9a-f]+:[ ]+60259073[ ]+csrw[ ]+hedeleg,a1 +[ ]+[0-9a-f]+:[ ]+60302573[ ]+csrr[ ]+a0,hideleg +[ ]+[0-9a-f]+:[ ]+60359073[ ]+csrw[ ]+hideleg,a1 +[ ]+[0-9a-f]+:[ ]+60402573[ ]+csrr[ ]+a0,hie +[ ]+[0-9a-f]+:[ ]+60459073[ ]+csrw[ ]+hie,a1 +[ ]+[0-9a-f]+:[ ]+60602573[ ]+csrr[ ]+a0,hcounteren +[ ]+[0-9a-f]+:[ ]+60659073[ ]+csrw[ ]+hcounteren,a1 +[ ]+[0-9a-f]+:[ ]+60702573[ ]+csrr[ ]+a0,hgeie +[ ]+[0-9a-f]+:[ ]+60759073[ ]+csrw[ ]+hgeie,a1 +[ ]+[0-9a-f]+:[ ]+64302573[ ]+csrr[ ]+a0,htval +[ ]+[0-9a-f]+:[ ]+64359073[ ]+csrw[ ]+htval,a1 +[ ]+[0-9a-f]+:[ ]+64402573[ ]+csrr[ ]+a0,hip +[ ]+[0-9a-f]+:[ ]+64459073[ ]+csrw[ ]+hip,a1 +[ ]+[0-9a-f]+:[ ]+64502573[ ]+csrr[ ]+a0,hvip +[ ]+[0-9a-f]+:[ ]+64559073[ ]+csrw[ ]+hvip,a1 +[ ]+[0-9a-f]+:[ ]+64a02573[ ]+csrr[ ]+a0,htinst +[ ]+[0-9a-f]+:[ ]+64a59073[ ]+csrw[ ]+htinst,a1 +[ ]+[0-9a-f]+:[ ]+e1202573[ ]+csrr[ ]+a0,hgeip +[ ]+[0-9a-f]+:[ ]+e1259073[ ]+csrw[ ]+hgeip,a1 +[ ]+[0-9a-f]+:[ ]+60a02573[ ]+csrr[ ]+a0,henvcfg +[ ]+[0-9a-f]+:[ ]+60a59073[ ]+csrw[ ]+henvcfg,a1 +[ ]+[0-9a-f]+:[ ]+61a02573[ ]+csrr[ ]+a0,henvcfgh +[ ]+[0-9a-f]+:[ ]+61a59073[ ]+csrw[ ]+henvcfgh,a1 +[ ]+[0-9a-f]+:[ ]+68002573[ ]+csrr[ ]+a0,hgatp +[ ]+[0-9a-f]+:[ ]+68059073[ ]+csrw[ ]+hgatp,a1 +[ ]+[0-9a-f]+:[ ]+6a802573[ ]+csrr[ ]+a0,hcontext +[ ]+[0-9a-f]+:[ ]+6a859073[ ]+csrw[ ]+hcontext,a1 +[ ]+[0-9a-f]+:[ ]+60502573[ ]+csrr[ ]+a0,htimedelta +[ ]+[0-9a-f]+:[ ]+60559073[ ]+csrw[ ]+htimedelta,a1 +[ ]+[0-9a-f]+:[ ]+61502573[ ]+csrr[ ]+a0,htimedeltah +[ ]+[0-9a-f]+:[ ]+61559073[ ]+csrw[ ]+htimedeltah,a1 +[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,vsstatus +[ ]+[0-9a-f]+:[ ]+20059073[ ]+csrw[ ]+vsstatus,a1 +[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,vsie +[ ]+[0-9a-f]+:[ ]+20459073[ ]+csrw[ ]+vsie,a1 +[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,vstvec +[ ]+[0-9a-f]+:[ ]+20559073[ ]+csrw[ ]+vstvec,a1 +[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,vsscratch +[ ]+[0-9a-f]+:[ ]+24059073[ ]+csrw[ ]+vsscratch,a1 +[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,vsepc +[ ]+[0-9a-f]+:[ ]+24159073[ ]+csrw[ ]+vsepc,a1 +[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,vscause +[ ]+[0-9a-f]+:[ ]+24259073[ ]+csrw[ ]+vscause,a1 +[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,vstval +[ ]+[0-9a-f]+:[ ]+24359073[ ]+csrw[ ]+vstval,a1 +[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,vsip +[ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1 +[ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp +[ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1 diff --git a/gas/testsuite/gas/riscv/h-ext-32.s b/gas/testsuite/gas/riscv/h-ext-32.s new file mode 100644 index 000000000000..976ec7c97510 --- /dev/null +++ b/gas/testsuite/gas/riscv/h-ext-32.s @@ -0,0 +1,64 @@ + hlv.b a0, (a1) + hlv.b a0,0(a1) + hlv.bu a0, (a1) + hlv.h a1, (a2) + hlv.hu a1, (a1) + hlvx.hu a1, (a2) + hlv.w a2, (a2) + hlvx.wu a2, (a3) + hsv.b a0, (a1) + hsv.b a0,0(a1) + hsv.h a0, (a1) + hsv.w a0, (a1) + csrr a0, hstatus + csrw hstatus, a1 + csrr a0, hedeleg + csrw hedeleg, a1 + csrr a0, hideleg + csrw hideleg, a1 + csrr a0, hie + csrw hie, a1 + csrr a0, hcounteren + csrw hcounteren, a1 + csrr a0, hgeie + csrw hgeie, a1 + csrr a0, htval + csrw htval, a1 + csrr a0, hip + csrw hip, a1 + csrr a0, hvip + csrw hvip, a1 + csrr a0, htinst + csrw htinst, a1 + csrr a0, hgeip + csrw hgeip, a1 + csrr a0, henvcfg + csrw henvcfg, a1 + csrr a0, henvcfgh + csrw henvcfgh, a1 + csrr a0, hgatp + csrw hgatp, a1 + csrr a0, hcontext + csrw hcontext, a1 + csrr a0, htimedelta + csrw htimedelta, a1 + csrr a0, htimedeltah + csrw htimedeltah, a1 + csrr a0, vsstatus + csrw vsstatus, a1 + csrr a0, vsie + csrw vsie, a1 + csrr a0, vstvec + csrw vstvec, a1 + csrr a0, vsscratch + csrw vsscratch, a1 + csrr a0, vsepc + csrw vsepc, a1 + csrr a0, vscause + csrw vscause, a1 + csrr a0, vstval + csrw vstval, a1 + csrr a0, vsip + csrw vsip, a1 + csrr a0, vsatp + csrw vsatp, a1 diff --git a/gas/testsuite/gas/riscv/h-ext-64.d b/gas/testsuite/gas/riscv/h-ext-64.d new file mode 100644 index 000000000000..d75c6ebbde6b --- /dev/null +++ b/gas/testsuite/gas/riscv/h-ext-64.d @@ -0,0 +1,73 @@ +#as: -march=rv64g -mpriv-spec=1.12 +#source: h-ext-64.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6015c573[ ]+hlv.bu[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+640645f3[ ]+hlv.h[ ]+a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+6415c5f3[ ]+hlv.hu[ ]+a1,\(a1\) +[ ]+[0-9a-f]+:[ ]+643645f3[ ]+hlvx.hu[ ]+a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+68064673[ ]+hlv.w[ ]+a2,\(a2\) +[ ]+[0-9a-f]+:[ ]+6816c673[ ]+hlv.wu[ ]+a2,\(a3\) +[ ]+[0-9a-f]+:[ ]+6836c673[ ]+hlvx.wu[ ]+a2,\(a3\) +[ ]+[0-9a-f]+:[ ]+6c0746f3[ ]+hlv.d[ ]+a3,\(a4\) +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+66a5c073[ ]+hsv.h[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6aa5c073[ ]+hsv.w[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+6ea5c073[ ]+hsv.d[ ]+a0,\(a1\) +[ ]+[0-9a-f]+:[ ]+60002573[ ]+csrr[ ]+a0,hstatus +[ ]+[0-9a-f]+:[ ]+60059073[ ]+csrw[ ]+hstatus,a1 +[ ]+[0-9a-f]+:[ ]+60202573[ ]+csrr[ ]+a0,hedeleg +[ ]+[0-9a-f]+:[ ]+60259073[ ]+csrw[ ]+hedeleg,a1 +[ ]+[0-9a-f]+:[ ]+60302573[ ]+csrr[ ]+a0,hideleg +[ ]+[0-9a-f]+:[ ]+60359073[ ]+csrw[ ]+hideleg,a1 +[ ]+[0-9a-f]+:[ ]+60402573[ ]+csrr[ ]+a0,hie +[ ]+[0-9a-f]+:[ ]+60459073[ ]+csrw[ ]+hie,a1 +[ ]+[0-9a-f]+:[ ]+60602573[ ]+csrr[ ]+a0,hcounteren +[ ]+[0-9a-f]+:[ ]+60659073[ ]+csrw[ ]+hcounteren,a1 +[ ]+[0-9a-f]+:[ ]+60702573[ ]+csrr[ ]+a0,hgeie +[ ]+[0-9a-f]+:[ ]+60759073[ ]+csrw[ ]+hgeie,a1 +[ ]+[0-9a-f]+:[ ]+64302573[ ]+csrr[ ]+a0,htval +[ ]+[0-9a-f]+:[ ]+64359073[ ]+csrw[ ]+htval,a1 +[ ]+[0-9a-f]+:[ ]+64402573[ ]+csrr[ ]+a0,hip +[ ]+[0-9a-f]+:[ ]+64459073[ ]+csrw[ ]+hip,a1 +[ ]+[0-9a-f]+:[ ]+64502573[ ]+csrr[ ]+a0,hvip +[ ]+[0-9a-f]+:[ ]+64559073[ ]+csrw[ ]+hvip,a1 +[ ]+[0-9a-f]+:[ ]+64a02573[ ]+csrr[ ]+a0,htinst +[ ]+[0-9a-f]+:[ ]+64a59073[ ]+csrw[ ]+htinst,a1 +[ ]+[0-9a-f]+:[ ]+e1202573[ ]+csrr[ ]+a0,hgeip +[ ]+[0-9a-f]+:[ ]+e1259073[ ]+csrw[ ]+hgeip,a1 +[ ]+[0-9a-f]+:[ ]+60a02573[ ]+csrr[ ]+a0,henvcfg +[ ]+[0-9a-f]+:[ ]+60a59073[ ]+csrw[ ]+henvcfg,a1 +[ ]+[0-9a-f]+:[ ]+68002573[ ]+csrr[ ]+a0,hgatp +[ ]+[0-9a-f]+:[ ]+68059073[ ]+csrw[ ]+hgatp,a1 +[ ]+[0-9a-f]+:[ ]+6a802573[ ]+csrr[ ]+a0,hcontext +[ ]+[0-9a-f]+:[ ]+6a859073[ ]+csrw[ ]+hcontext,a1 +[ ]+[0-9a-f]+:[ ]+60502573[ ]+csrr[ ]+a0,htimedelta +[ ]+[0-9a-f]+:[ ]+60559073[ ]+csrw[ ]+htimedelta,a1 +[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,vsstatus +[ ]+[0-9a-f]+:[ ]+20059073[ ]+csrw[ ]+vsstatus,a1 +[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,vsie +[ ]+[0-9a-f]+:[ ]+20459073[ ]+csrw[ ]+vsie,a1 +[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,vstvec +[ ]+[0-9a-f]+:[ ]+20559073[ ]+csrw[ ]+vstvec,a1 +[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,vsscratch +[ ]+[0-9a-f]+:[ ]+24059073[ ]+csrw[ ]+vsscratch,a1 +[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,vsepc +[ ]+[0-9a-f]+:[ ]+24159073[ ]+csrw[ ]+vsepc,a1 +[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,vscause +[ ]+[0-9a-f]+:[ ]+24259073[ ]+csrw[ ]+vscause,a1 +[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,vstval +[ ]+[0-9a-f]+:[ ]+24359073[ ]+csrw[ ]+vstval,a1 +[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,vsip +[ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1 +[ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp +[ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1 diff --git a/gas/testsuite/gas/riscv/h-ext-64.s b/gas/testsuite/gas/riscv/h-ext-64.s new file mode 100644 index 000000000000..5b535d013877 --- /dev/null +++ b/gas/testsuite/gas/riscv/h-ext-64.s @@ -0,0 +1,63 @@ + hlv.b a0, (a1) + hlv.b a0,0(a1) + hlv.bu a0, (a1) + hlv.h a1, (a2) + hlv.hu a1, (a1) + hlvx.hu a1, (a2) + hlv.w a2, (a2) + hlv.wu a2, (a3) + hlvx.wu a2, (a3) + hlv.d a3, (a4) + hsv.b a0, (a1) + hsv.b a0,0(a1) + hsv.h a0, (a1) + hsv.w a0, (a1) + hsv.d a0, (a1) + csrr a0, hstatus + csrw hstatus, a1 + csrr a0, hedeleg + csrw hedeleg, a1 + csrr a0, hideleg + csrw hideleg, a1 + csrr a0, hie + csrw hie, a1 + csrr a0, hcounteren + csrw hcounteren, a1 + csrr a0, hgeie + csrw hgeie, a1 + csrr a0, htval + csrw htval, a1 + csrr a0, hip + csrw hip, a1 + csrr a0, hvip + csrw hvip, a1 + csrr a0, htinst + csrw htinst, a1 + csrr a0, hgeip + csrw hgeip, a1 + csrr a0, henvcfg + csrw henvcfg, a1 + csrr a0, hgatp + csrw hgatp, a1 + csrr a0, hcontext + csrw hcontext, a1 + csrr a0, htimedelta + csrw htimedelta, a1 + csrr a0, vsstatus + csrw vsstatus, a1 + csrr a0, vsie + csrw vsie, a1 + csrr a0, vstvec + csrw vstvec, a1 + csrr a0, vsscratch + csrw vsscratch, a1 + csrr a0, vsepc + csrw vsepc, a1 + csrr a0, vscause + csrw vscause, a1 + csrr a0, vstval + csrw vstval, a1 + csrr a0, vsip + csrw vsip, a1 + csrr a0, vsatp + csrw vsatp, a1 diff --git a/gas/testsuite/gas/riscv/svinval-and-h.d b/gas/testsuite/gas/riscv/svinval-and-h.d new file mode 100644 index 000000000000..7821377a5eb5 --- /dev/null +++ b/gas/testsuite/gas/riscv/svinval-and-h.d @@ -0,0 +1,15 @@ +#as: -march=rv64i_svinval +#source: svinval-and-h.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+0:[ ]+22b50073[ ]+hfence.vvma[ ]+a0,a1 +[ ]+4:[ ]+62000073[ ]+hfence.gvma +[ ]+8:[ ]+62050073[ ]+hfence.gvma[ ]+a0 +[ ]+c:[ ]+62b00073[ ]+hfence.gvma[ ]+zero,a1 +[ ]+10:[ ]+62c58073[ ]+hfence.gvma[ ]+a1,a2 diff --git a/gas/testsuite/gas/riscv/svinval-and-h.s b/gas/testsuite/gas/riscv/svinval-and-h.s new file mode 100644 index 000000000000..bdf4abd8020a --- /dev/null +++ b/gas/testsuite/gas/riscv/svinval-and-h.s @@ -0,0 +1,5 @@ + hfence.vvma a0, a1 + hfence.gvma + hfence.gvma a0 + hfence.gvma x0, a1 + hfence.gvma a1, a2 -- 2.30.2 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v1 3/4] RISC-V: Hypervisor Ext: Add tests 2021-12-21 2:34 ` [v1 3/4] RISC-V: Hypervisor Ext: Add tests Vineet Gupta @ 2022-01-04 8:12 ` Jan Beulich 2022-01-04 18:46 ` Vineet Gupta 0 siblings, 1 reply; 14+ messages in thread From: Jan Beulich @ 2022-01-04 8:12 UTC (permalink / raw) To: Vineet Gupta; +Cc: Kito Cheng, Binutils, Nelson Chu On 21.12.2021 03:34, Vineet Gupta wrote: > --- /dev/null > +++ b/gas/testsuite/gas/riscv/h-ext-32.s > @@ -0,0 +1,64 @@ > + hlv.b a0, (a1) > + hlv.b a0,0(a1) > + hlv.bu a0, (a1) > + hlv.h a1, (a2) > + hlv.hu a1, (a1) > + hlvx.hu a1, (a2) > + hlv.w a2, (a2) > + hlvx.wu a2, (a3) > + hsv.b a0, (a1) > + hsv.b a0,0(a1) > + hsv.h a0, (a1) > + hsv.w a0, (a1) > + csrr a0, hstatus > + csrw hstatus, a1 > + csrr a0, hedeleg > + csrw hedeleg, a1 > + csrr a0, hideleg > + csrw hideleg, a1 > + csrr a0, hie > + csrw hie, a1 > + csrr a0, hcounteren > + csrw hcounteren, a1 > + csrr a0, hgeie > + csrw hgeie, a1 > + csrr a0, htval > + csrw htval, a1 > + csrr a0, hip > + csrw hip, a1 > + csrr a0, hvip > + csrw hvip, a1 > + csrr a0, htinst > + csrw htinst, a1 > + csrr a0, hgeip > + csrw hgeip, a1 I this actually a good thing to test? Aiui this csr is r/o; I'd expect the assembler to at least warn about write attempts ... Jan ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v1 3/4] RISC-V: Hypervisor Ext: Add tests 2022-01-04 8:12 ` Jan Beulich @ 2022-01-04 18:46 ` Vineet Gupta 0 siblings, 0 replies; 14+ messages in thread From: Vineet Gupta @ 2022-01-04 18:46 UTC (permalink / raw) To: Jan Beulich; +Cc: Kito Cheng, Binutils, Nelson Chu On 1/4/22 12:12 AM, Jan Beulich wrote: >> + csrr a0, hgeip >> + csrw hgeip, a1 > I this actually a good thing to test? Aiui this csr is r/o; I'd expect > the assembler to at least warn about write attempts ... The assembler does warn when testsuite is run (-mcsr-check). This exact code snippet was changed by Nelson as part of csr test consolidation, but test still tries to write to it (and so do a whole bunch of other R/O csrs) - I'm not sure if this is intended (to show that assembler does warn if user were to do this) or if needs to be fixed in the tests. ^ permalink raw reply [flat|nested] 14+ messages in thread
* [v1 4/4] RISC-V: fix a comment for adding CSR entry and annotate switch-break 2021-12-21 2:34 [v1 0/4]riscv/binutils support Hypervisor Extension Vineet Gupta ` (2 preceding siblings ...) 2021-12-21 2:34 ` [v1 3/4] RISC-V: Hypervisor Ext: Add tests Vineet Gupta @ 2021-12-21 2:34 ` Vineet Gupta 2021-12-23 1:35 ` [v1 0/4]riscv/binutils support Hypervisor Extension Palmer Dabbelt 4 siblings, 0 replies; 14+ messages in thread From: Vineet Gupta @ 2021-12-21 2:34 UTC (permalink / raw) To: Binutils, Nelson Chu; +Cc: Kito Cheng, jim.wilson.gcc, palmer, Vineet Gupta Nothing functional ... Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> --- gas/config/tc-riscv.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index e8061217e7cd..dbf0e23c4563 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -82,7 +82,7 @@ struct riscv_csr_extra enum riscv_spec_class define_version; /* Record the CSR is aborted/invalid from which versions. If it isn't - aborted in the current version, then it should be CSR_CLASS_VDRAFT. */ + aborted in the current version, then it should be PRIV_SPEC_CLASS_DRAFT. */ enum riscv_spec_class abort_version; /* The CSR may have more than one setting. */ @@ -1104,7 +1104,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) default: goto unknown_validate_operand; } - break; + break; /* end RVC */ case 'V': /* RVV */ switch (*++oparg) { @@ -1128,7 +1128,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) default: goto unknown_validate_operand; } - break; + break; /* end RVV */ case ',': break; case '(': break; case ')': break; @@ -2605,7 +2605,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, default: goto unknown_riscv_ip_operand; } - break; + break; /* end RVC */ case 'V': /* RVV */ switch (*++oparg) @@ -2771,7 +2771,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, default: goto unknown_riscv_ip_operand; } - break; + break; /* end RVV */ case ',': ++argnum; -- 2.30.2 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v1 0/4]riscv/binutils support Hypervisor Extension 2021-12-21 2:34 [v1 0/4]riscv/binutils support Hypervisor Extension Vineet Gupta ` (3 preceding siblings ...) 2021-12-21 2:34 ` [v1 4/4] RISC-V: fix a comment for adding CSR entry and annotate switch-break Vineet Gupta @ 2021-12-23 1:35 ` Palmer Dabbelt 2021-12-24 8:51 ` Nelson Chu 4 siblings, 1 reply; 14+ messages in thread From: Palmer Dabbelt @ 2021-12-23 1:35 UTC (permalink / raw) To: Vineet Gupta; +Cc: binutils, Nelson Chu, kito.cheng, Jim Wilson, Vineet Gupta On Mon, 20 Dec 2021 18:34:11 PST (-0800), Vineet Gupta wrote: > Hi, > > This patchset adds support for Hypervisor Extension ratified recently > [1]. > > Changes since RFC [2]: > > - Drop support for single-letter arch string "h". > 'H' extension is currently supported unconditionally so keep status quo. WFM: there's no name for this, so just keeping it as part of the base ISA seems like the best we can do. It certainly matches the precedent we've set a bunch of times before, and holding this up because we can't name it is just silly. > - H-ext support in Priv spec 1.9.1 dropped, broken out as seperate patch. > > Please review/comment ! I think I said this in the RFC, but we generally don't drop support for stuff we have. In theory removing the 1.9.1 CSRs is something that would break users, but I think we're pretty safe here because these vestigial bits of the hypervisor extension never really did anything so Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> In the unlikely event that anyone's actually using this, now's the time to speak up! Thanks! > Thx, > -Vineet > > [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions > [2] https://sourceware.org/pipermail/binutils/2021-December/118914.html > > Vineet Gupta (4): > RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 > implementation/tests > RISC-V: Hypervisor ext: support Privileged Spec 1.12 > RISC-V: Hypervisor Ext: Add tests > RISC-V: fix a comment for adding CSR entry and annotate switch-break > > bfd/cpu-riscv.c | 1 + > bfd/cpu-riscv.h | 1 + > bfd/elfxx-riscv.c | 6 + > gas/config/tc-riscv.c | 10 +- > gas/testsuite/gas/riscv/csr-dw-regnums.d | 10 -- > gas/testsuite/gas/riscv/csr-dw-regnums.s | 10 -- > gas/testsuite/gas/riscv/h-ext-32.d | 74 ++++++++++++ > gas/testsuite/gas/riscv/h-ext-32.s | 64 ++++++++++ > gas/testsuite/gas/riscv/h-ext-64.d | 73 ++++++++++++ > gas/testsuite/gas/riscv/h-ext-64.s | 63 ++++++++++ > .../gas/riscv/priv-reg-fail-read-only-01.s | 10 -- > .../gas/riscv/priv-reg-fail-version-1p10.l | 10 -- > .../gas/riscv/priv-reg-fail-version-1p11.l | 10 -- > .../gas/riscv/priv-reg-version-1p10.d | 10 -- > .../gas/riscv/priv-reg-version-1p11.d | 10 -- > .../gas/riscv/priv-reg-version-1p9p1.d | 10 -- > gas/testsuite/gas/riscv/priv-reg.s | 10 -- > gas/testsuite/gas/riscv/svinval-and-h.d | 15 +++ > gas/testsuite/gas/riscv/svinval-and-h.s | 5 + > include/opcode/riscv-opc.h | 110 ++++++++++++++---- > include/opcode/riscv.h | 2 + > opcodes/riscv-opc.c | 26 ++++- > 22 files changed, 423 insertions(+), 117 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/h-ext-32.d > create mode 100644 gas/testsuite/gas/riscv/h-ext-32.s > create mode 100644 gas/testsuite/gas/riscv/h-ext-64.d > create mode 100644 gas/testsuite/gas/riscv/h-ext-64.s > create mode 100644 gas/testsuite/gas/riscv/svinval-and-h.d > create mode 100644 gas/testsuite/gas/riscv/svinval-and-h.s ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v1 0/4]riscv/binutils support Hypervisor Extension 2021-12-23 1:35 ` [v1 0/4]riscv/binutils support Hypervisor Extension Palmer Dabbelt @ 2021-12-24 8:51 ` Nelson Chu 2021-12-28 17:54 ` Vineet Gupta 0 siblings, 1 reply; 14+ messages in thread From: Nelson Chu @ 2021-12-24 8:51 UTC (permalink / raw) To: Palmer Dabbelt; +Cc: Vineet Gupta, Binutils, Kito Cheng, Jim Wilson Hi Palmer, Hi Vineet, Thanks for all the series of patches, looks good to me, except some minor issues, so I leave some comments in the related patches. But since I need to commit the rewritten csr testcases, I committed Vineet patches with the minor changes directly. Thanks Nelson On Thu, Dec 23, 2021 at 9:35 AM Palmer Dabbelt <palmer@dabbelt.com> wrote: > > On Mon, 20 Dec 2021 18:34:11 PST (-0800), Vineet Gupta wrote: > > Hi, > > > > This patchset adds support for Hypervisor Extension ratified recently > > [1]. > > > > Changes since RFC [2]: > > > > - Drop support for single-letter arch string "h". > > 'H' extension is currently supported unconditionally so keep status quo. > > WFM: there's no name for this, so just keeping it as part of the base > ISA seems like the best we can do. It certainly matches the precedent > we've set a bunch of times before, and holding this up because we can't > name it is just silly. > > > - H-ext support in Priv spec 1.9.1 dropped, broken out as seperate patch. > > > > Please review/comment ! > > I think I said this in the RFC, but we generally don't drop support for > stuff we have. In theory removing the 1.9.1 CSRs is something that > would break users, but I think we're pretty safe here because these > vestigial bits of the hypervisor extension never really did anything so > > Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> > > In the unlikely event that anyone's actually using this, now's the time > to speak up! > > Thanks! > > > Thx, > > -Vineet > > > > [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions > > [2] https://sourceware.org/pipermail/binutils/2021-December/118914.html > > > > Vineet Gupta (4): > > RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 > > implementation/tests > > RISC-V: Hypervisor ext: support Privileged Spec 1.12 > > RISC-V: Hypervisor Ext: Add tests > > RISC-V: fix a comment for adding CSR entry and annotate switch-break > > > > bfd/cpu-riscv.c | 1 + > > bfd/cpu-riscv.h | 1 + > > bfd/elfxx-riscv.c | 6 + > > gas/config/tc-riscv.c | 10 +- > > gas/testsuite/gas/riscv/csr-dw-regnums.d | 10 -- > > gas/testsuite/gas/riscv/csr-dw-regnums.s | 10 -- > > gas/testsuite/gas/riscv/h-ext-32.d | 74 ++++++++++++ > > gas/testsuite/gas/riscv/h-ext-32.s | 64 ++++++++++ > > gas/testsuite/gas/riscv/h-ext-64.d | 73 ++++++++++++ > > gas/testsuite/gas/riscv/h-ext-64.s | 63 ++++++++++ > > .../gas/riscv/priv-reg-fail-read-only-01.s | 10 -- > > .../gas/riscv/priv-reg-fail-version-1p10.l | 10 -- > > .../gas/riscv/priv-reg-fail-version-1p11.l | 10 -- > > .../gas/riscv/priv-reg-version-1p10.d | 10 -- > > .../gas/riscv/priv-reg-version-1p11.d | 10 -- > > .../gas/riscv/priv-reg-version-1p9p1.d | 10 -- > > gas/testsuite/gas/riscv/priv-reg.s | 10 -- > > gas/testsuite/gas/riscv/svinval-and-h.d | 15 +++ > > gas/testsuite/gas/riscv/svinval-and-h.s | 5 + > > include/opcode/riscv-opc.h | 110 ++++++++++++++---- > > include/opcode/riscv.h | 2 + > > opcodes/riscv-opc.c | 26 ++++- > > 22 files changed, 423 insertions(+), 117 deletions(-) > > create mode 100644 gas/testsuite/gas/riscv/h-ext-32.d > > create mode 100644 gas/testsuite/gas/riscv/h-ext-32.s > > create mode 100644 gas/testsuite/gas/riscv/h-ext-64.d > > create mode 100644 gas/testsuite/gas/riscv/h-ext-64.s > > create mode 100644 gas/testsuite/gas/riscv/svinval-and-h.d > > create mode 100644 gas/testsuite/gas/riscv/svinval-and-h.s ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v1 0/4]riscv/binutils support Hypervisor Extension 2021-12-24 8:51 ` Nelson Chu @ 2021-12-28 17:54 ` Vineet Gupta 0 siblings, 0 replies; 14+ messages in thread From: Vineet Gupta @ 2021-12-28 17:54 UTC (permalink / raw) To: Nelson Chu, Palmer Dabbelt; +Cc: Binutils, Kito Cheng, Jim Wilson Hi Nelson, On 12/24/21 12:51 AM, Nelson Chu wrote: > Hi Palmer, Hi Vineet, > > Thanks for all the series of patches, looks good to me, except some > minor issues, so I leave some comments in the related patches. But > since I need to commit the rewritten csr testcases, I committed Vineet > patches with the minor changes directly. Many thanks for the fixups and quickly getting these in. Happy Holidays ! cheers, -Vineet > > Thanks > Nelson > > On Thu, Dec 23, 2021 at 9:35 AM Palmer Dabbelt <palmer@dabbelt.com> wrote: >> On Mon, 20 Dec 2021 18:34:11 PST (-0800), Vineet Gupta wrote: >>> Hi, >>> >>> This patchset adds support for Hypervisor Extension ratified recently >>> [1]. >>> >>> Changes since RFC [2]: >>> >>> - Drop support for single-letter arch string "h". >>> 'H' extension is currently supported unconditionally so keep status quo. >> WFM: there's no name for this, so just keeping it as part of the base >> ISA seems like the best we can do. It certainly matches the precedent >> we've set a bunch of times before, and holding this up because we can't >> name it is just silly. >> >>> - H-ext support in Priv spec 1.9.1 dropped, broken out as seperate patch. >>> >>> Please review/comment ! >> I think I said this in the RFC, but we generally don't drop support for >> stuff we have. In theory removing the 1.9.1 CSRs is something that >> would break users, but I think we're pretty safe here because these >> vestigial bits of the hypervisor extension never really did anything so >> >> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> >> >> In the unlikely event that anyone's actually using this, now's the time >> to speak up! >> >> Thanks! >> >>> Thx, >>> -Vineet >>> >>> [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions >>> [2] https://sourceware.org/pipermail/binutils/2021-December/118914.html >>> >>> Vineet Gupta (4): >>> RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 >>> implementation/tests >>> RISC-V: Hypervisor ext: support Privileged Spec 1.12 >>> RISC-V: Hypervisor Ext: Add tests >>> RISC-V: fix a comment for adding CSR entry and annotate switch-break >>> >>> bfd/cpu-riscv.c | 1 + >>> bfd/cpu-riscv.h | 1 + >>> bfd/elfxx-riscv.c | 6 + >>> gas/config/tc-riscv.c | 10 +- >>> gas/testsuite/gas/riscv/csr-dw-regnums.d | 10 -- >>> gas/testsuite/gas/riscv/csr-dw-regnums.s | 10 -- >>> gas/testsuite/gas/riscv/h-ext-32.d | 74 ++++++++++++ >>> gas/testsuite/gas/riscv/h-ext-32.s | 64 ++++++++++ >>> gas/testsuite/gas/riscv/h-ext-64.d | 73 ++++++++++++ >>> gas/testsuite/gas/riscv/h-ext-64.s | 63 ++++++++++ >>> .../gas/riscv/priv-reg-fail-read-only-01.s | 10 -- >>> .../gas/riscv/priv-reg-fail-version-1p10.l | 10 -- >>> .../gas/riscv/priv-reg-fail-version-1p11.l | 10 -- >>> .../gas/riscv/priv-reg-version-1p10.d | 10 -- >>> .../gas/riscv/priv-reg-version-1p11.d | 10 -- >>> .../gas/riscv/priv-reg-version-1p9p1.d | 10 -- >>> gas/testsuite/gas/riscv/priv-reg.s | 10 -- >>> gas/testsuite/gas/riscv/svinval-and-h.d | 15 +++ >>> gas/testsuite/gas/riscv/svinval-and-h.s | 5 + >>> include/opcode/riscv-opc.h | 110 ++++++++++++++---- >>> include/opcode/riscv.h | 2 + >>> opcodes/riscv-opc.c | 26 ++++- >>> 22 files changed, 423 insertions(+), 117 deletions(-) >>> create mode 100644 gas/testsuite/gas/riscv/h-ext-32.d >>> create mode 100644 gas/testsuite/gas/riscv/h-ext-32.s >>> create mode 100644 gas/testsuite/gas/riscv/h-ext-64.d >>> create mode 100644 gas/testsuite/gas/riscv/h-ext-64.s >>> create mode 100644 gas/testsuite/gas/riscv/svinval-and-h.d >>> create mode 100644 gas/testsuite/gas/riscv/svinval-and-h.s ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-01-04 18:46 UTC | newest] Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-12-21 2:34 [v1 0/4]riscv/binutils support Hypervisor Extension Vineet Gupta 2021-12-21 2:34 ` [v1 1/4] RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/tests Vineet Gupta 2021-12-24 8:23 ` Nelson Chu 2021-12-21 2:34 ` [v1 2/4] RISC-V: Hypervisor ext: support Privileged Spec 1.12 Vineet Gupta 2021-12-24 8:40 ` Nelson Chu 2022-01-04 8:09 ` Jan Beulich 2022-01-04 18:10 ` Vineet Gupta 2021-12-21 2:34 ` [v1 3/4] RISC-V: Hypervisor Ext: Add tests Vineet Gupta 2022-01-04 8:12 ` Jan Beulich 2022-01-04 18:46 ` Vineet Gupta 2021-12-21 2:34 ` [v1 4/4] RISC-V: fix a comment for adding CSR entry and annotate switch-break Vineet Gupta 2021-12-23 1:35 ` [v1 0/4]riscv/binutils support Hypervisor Extension Palmer Dabbelt 2021-12-24 8:51 ` Nelson Chu 2021-12-28 17:54 ` Vineet Gupta
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