From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by sourceware.org (Postfix) with ESMTPS id 4DF1F3858C83 for ; Mon, 7 Feb 2022 09:34:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4DF1F3858C83 Received: from dggpeml500023.china.huawei.com (unknown [172.30.72.54]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4JsgtC2X6rz9sWH for ; Mon, 7 Feb 2022 17:33:07 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggpeml500023.china.huawei.com (7.185.36.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Mon, 7 Feb 2022 17:34:37 +0800 From: Shaokun Zhang To: CC: Jingtao Cai , Bo Dong , Shaokun Zhang Subject: [PATCH] Fix the disassembly of the AArch64 SVE DECP/INCP/SQDECP/SQINCP instruction. Date: Mon, 7 Feb 2022 17:34:41 +0800 Message-ID: <20220207093441.55725-1-zhangshaokun@hisilicon.com> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To dggpeml500023.china.huawei.com (7.185.36.114) X-CFilter-Loop: Reflected X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Feb 2022 09:34:50 -0000 From: Jingtao Cai This patch fix qualifier for the AArch64 SVE DECP/INCP/SQDECP/SQINCP instruction, which take the predicate size specifier: DECP ., . INCP ., . SQINCP ., . SQDECP ., . Omitted predicate size specifier will be prohibited in a future release of the architecture, please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document[0]. [0]: https://developer.arm.com/documentation/ddi0596/2021-12/SVE-Instructions/DECP--vector---Decrement-vector-by-count-of-true-predicate-elements- E.g. : DECP Z1.H, P0.H This patch adds support for this kind of operand. DECP Z1.H, P0 This instruction leads to messages: Assembler messages: Error: operand mismatch -- `decp Z1.h,P0' did you mean this? decp z1.h, p0.h other valid variant(s): decp z1.s, p0 decp z1.d, p0 opcodes/ * aarch64-tbl.h (aarch64_opcode_table): Replace QUALS's type OP_SVE_VV_HSD with OP_SVE_VU_HSD for decp, incp, sqdecp and sqincp. gas/testsuite/ * gas/aarch64/sve-movprfx_23.d: update movprfx_23 testcase's expected disassembly * gas/aarch64/sve-movprfx_23.l: update movprfx_23 testcase's expected assembler messages * gas/aarch64/sve-movprfx_23.s: update movprfx_23 testcase's test_sametwo macro, where take the predicate size specifier * gas/aarch64/sve.d: update sve testcase's expected disassembly * gas/aarch64/sve.s: update sve testcase's instructions for decp, incp, sqdecp and sqincp, which take the predicate size specifier Cc: Bo Dong Cc: Shaokun Zhang Signed-off-by: Jingtao Cai --- gas/testsuite/gas/aarch64/sve-movprfx_23.d | 24 +-- gas/testsuite/gas/aarch64/sve-movprfx_23.l | 24 +-- gas/testsuite/gas/aarch64/sve-movprfx_23.s | 2 +- gas/testsuite/gas/aarch64/sve.d | 240 ++++++++++----------- gas/testsuite/gas/aarch64/sve.s | 240 ++++++++++----------- opcodes/aarch64-tbl.h | 8 +- 6 files changed, 269 insertions(+), 269 deletions(-) diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_23.d b/gas/testsuite/gas/aarch64/sve-movprfx_23.d index 60448704174a..e1c6c2c2ccef 100644 --- a/gas/testsuite/gas/aarch64/sve-movprfx_23.d +++ b/gas/testsuite/gas/aarch64/sve-movprfx_23.d @@ -9,29 +9,29 @@ Disassembly of section .*: 0+ <.*>: [^:]+: 04512461 movprfx z1.h, p1/m, z3.h -[^:]+: 256c8021 incp z1.h, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 256c8021 incp z1.h, p1.h // note: merging predicate expected due to preceding `movprfx' at operand 2 [^:]+: 04912461 movprfx z1.s, p1/m, z3.s -[^:]+: 25ac8021 incp z1.s, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 25ac8021 incp z1.s, p1.s // note: merging predicate expected due to preceding `movprfx' at operand 2 [^:]+: 04d12461 movprfx z1.d, p1/m, z3.d -[^:]+: 25ec8021 incp z1.d, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 25ec8021 incp z1.d, p1.d // note: merging predicate expected due to preceding `movprfx' at operand 2 [^:]+: 04512461 movprfx z1.h, p1/m, z3.h -[^:]+: 256d8021 decp z1.h, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 256d8021 decp z1.h, p1.h // note: merging predicate expected due to preceding `movprfx' at operand 2 [^:]+: 04912461 movprfx z1.s, p1/m, z3.s -[^:]+: 25ad8021 decp z1.s, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 25ad8021 decp z1.s, p1.s // note: merging predicate expected due to preceding `movprfx' at operand 2 [^:]+: 04d12461 movprfx z1.d, p1/m, z3.d -[^:]+: 25ed8021 decp z1.d, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 25ed8021 decp z1.d, p1.d // note: merging predicate expected due to preceding `movprfx' at operand 2 [^:]+: 04512461 movprfx z1.h, p1/m, z3.h -[^:]+: 25688021 sqincp z1.h, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 25688021 sqincp z1.h, p1.h // note: merging predicate expected due to preceding `movprfx' at operand 2 [^:]+: 04912461 movprfx z1.s, p1/m, z3.s -[^:]+: 25a88021 sqincp z1.s, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 25a88021 sqincp z1.s, p1.s // note: merging predicate expected due to preceding `movprfx' at operand 2 [^:]+: 04d12461 movprfx z1.d, p1/m, z3.d -[^:]+: 25e88021 sqincp z1.d, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 25e88021 sqincp z1.d, p1.d // note: merging predicate expected due to preceding `movprfx' at operand 2 [^:]+: 04512461 movprfx z1.h, p1/m, z3.h -[^:]+: 256a8021 sqdecp z1.h, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 256a8021 sqdecp z1.h, p1.h // note: merging predicate expected due to preceding `movprfx' at operand 2 [^:]+: 04912461 movprfx z1.s, p1/m, z3.s -[^:]+: 25aa8021 sqdecp z1.s, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 25aa8021 sqdecp z1.s, p1.s // note: merging predicate expected due to preceding `movprfx' at operand 2 [^:]+: 04d12461 movprfx z1.d, p1/m, z3.d -[^:]+: 25ea8021 sqdecp z1.d, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 25ea8021 sqdecp z1.d, p1.d // note: merging predicate expected due to preceding `movprfx' at operand 2 [^:]+: 04112461 movprfx z1.b, p1/m, z3.b [^:]+: 05288421 clasta z1.b, p1, z1.b, z1.b // note: merging predicate expected due to preceding `movprfx' at operand 2 [^:]+: 04512461 movprfx z1.h, p1/m, z3.h diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_23.l b/gas/testsuite/gas/aarch64/sve-movprfx_23.l index ff25ee712ed3..ac491df61893 100644 --- a/gas/testsuite/gas/aarch64/sve-movprfx_23.l +++ b/gas/testsuite/gas/aarch64/sve-movprfx_23.l @@ -1,16 +1,16 @@ [^:]*: Assembler messages: -.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.h,p1' -.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.s,p1' -.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.d,p1' -.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.h,p1' -.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.s,p1' -.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.d,p1' -.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.h,p1' -.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.s,p1' -.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.d,p1' -.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.h,p1' -.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.s,p1' -.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.d,p1' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.h,p1.h' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.s,p1.s' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.d,p1.d' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.h,p1.h' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.s,p1.s' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.d,p1.d' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.h,p1.h' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.s,p1.s' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.d,p1.d' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.h,p1.h' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.s,p1.s' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.d,p1.d' .*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.b,p1,z1.b,z1.b' .*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.h,p1,z1.h,z1.h' .*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.s,p1,z1.s,z1.s' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_23.s b/gas/testsuite/gas/aarch64/sve-movprfx_23.s index 709d81aa8a04..22697b37cf5f 100644 --- a/gas/testsuite/gas/aarch64/sve-movprfx_23.s +++ b/gas/testsuite/gas/aarch64/sve-movprfx_23.s @@ -9,7 +9,7 @@ .macro test_sametwo inst .irp sz, h,s,d movprfx z1.\sz, p1/m, z3.\sz - \inst z1.\sz, p1 + \inst z1.\sz, p1.\sz .endr .endm diff --git a/gas/testsuite/gas/aarch64/sve.d b/gas/testsuite/gas/aarch64/sve.d index 5d6d7562646f..dbf06ee70cd9 100644 --- a/gas/testsuite/gas/aarch64/sve.d +++ b/gas/testsuite/gas/aarch64/sve.d @@ -7205,36 +7205,36 @@ Disassembly of section .*: [^:]+: 0479e400 dech x0, pow2, mul #10 [^:]+: 047fe400 dech x0, pow2, mul #16 [^:]+: 047fe400 dech x0, pow2, mul #16 -[^:]+: 256d8000 decp z0.h, p0 -[^:]+: 256d8000 decp z0.h, p0 -[^:]+: 256d8001 decp z1.h, p0 -[^:]+: 256d8001 decp z1.h, p0 -[^:]+: 256d801f decp z31.h, p0 -[^:]+: 256d801f decp z31.h, p0 -[^:]+: 256d8040 decp z0.h, p2 -[^:]+: 256d8040 decp z0.h, p2 -[^:]+: 256d81e0 decp z0.h, p15 -[^:]+: 256d81e0 decp z0.h, p15 -[^:]+: 25ad8000 decp z0.s, p0 -[^:]+: 25ad8000 decp z0.s, p0 -[^:]+: 25ad8001 decp z1.s, p0 -[^:]+: 25ad8001 decp z1.s, p0 -[^:]+: 25ad801f decp z31.s, p0 -[^:]+: 25ad801f decp z31.s, p0 -[^:]+: 25ad8040 decp z0.s, p2 -[^:]+: 25ad8040 decp z0.s, p2 -[^:]+: 25ad81e0 decp z0.s, p15 -[^:]+: 25ad81e0 decp z0.s, p15 -[^:]+: 25ed8000 decp z0.d, p0 -[^:]+: 25ed8000 decp z0.d, p0 -[^:]+: 25ed8001 decp z1.d, p0 -[^:]+: 25ed8001 decp z1.d, p0 -[^:]+: 25ed801f decp z31.d, p0 -[^:]+: 25ed801f decp z31.d, p0 -[^:]+: 25ed8040 decp z0.d, p2 -[^:]+: 25ed8040 decp z0.d, p2 -[^:]+: 25ed81e0 decp z0.d, p15 -[^:]+: 25ed81e0 decp z0.d, p15 +[^:]+: 256d8000 decp z0.h, p0.h +[^:]+: 256d8000 decp z0.h, p0.h +[^:]+: 256d8001 decp z1.h, p0.h +[^:]+: 256d8001 decp z1.h, p0.h +[^:]+: 256d801f decp z31.h, p0.h +[^:]+: 256d801f decp z31.h, p0.h +[^:]+: 256d8040 decp z0.h, p2.h +[^:]+: 256d8040 decp z0.h, p2.h +[^:]+: 256d81e0 decp z0.h, p15.h +[^:]+: 256d81e0 decp z0.h, p15.h +[^:]+: 25ad8000 decp z0.s, p0.s +[^:]+: 25ad8000 decp z0.s, p0.s +[^:]+: 25ad8001 decp z1.s, p0.s +[^:]+: 25ad8001 decp z1.s, p0.s +[^:]+: 25ad801f decp z31.s, p0.s +[^:]+: 25ad801f decp z31.s, p0.s +[^:]+: 25ad8040 decp z0.s, p2.s +[^:]+: 25ad8040 decp z0.s, p2.s +[^:]+: 25ad81e0 decp z0.s, p15.s +[^:]+: 25ad81e0 decp z0.s, p15.s +[^:]+: 25ed8000 decp z0.d, p0.d +[^:]+: 25ed8000 decp z0.d, p0.d +[^:]+: 25ed8001 decp z1.d, p0.d +[^:]+: 25ed8001 decp z1.d, p0.d +[^:]+: 25ed801f decp z31.d, p0.d +[^:]+: 25ed801f decp z31.d, p0.d +[^:]+: 25ed8040 decp z0.d, p2.d +[^:]+: 25ed8040 decp z0.d, p2.d +[^:]+: 25ed81e0 decp z0.d, p15.d +[^:]+: 25ed81e0 decp z0.d, p15.d [^:]+: 252d8800 decp x0, p0.b [^:]+: 252d8800 decp x0, p0.b [^:]+: 252d8801 decp x1, p0.b @@ -13031,36 +13031,36 @@ Disassembly of section .*: [^:]+: 0479e000 inch x0, pow2, mul #10 [^:]+: 047fe000 inch x0, pow2, mul #16 [^:]+: 047fe000 inch x0, pow2, mul #16 -[^:]+: 256c8000 incp z0.h, p0 -[^:]+: 256c8000 incp z0.h, p0 -[^:]+: 256c8001 incp z1.h, p0 -[^:]+: 256c8001 incp z1.h, p0 -[^:]+: 256c801f incp z31.h, p0 -[^:]+: 256c801f incp z31.h, p0 -[^:]+: 256c8040 incp z0.h, p2 -[^:]+: 256c8040 incp z0.h, p2 -[^:]+: 256c81e0 incp z0.h, p15 -[^:]+: 256c81e0 incp z0.h, p15 -[^:]+: 25ac8000 incp z0.s, p0 -[^:]+: 25ac8000 incp z0.s, p0 -[^:]+: 25ac8001 incp z1.s, p0 -[^:]+: 25ac8001 incp z1.s, p0 -[^:]+: 25ac801f incp z31.s, p0 -[^:]+: 25ac801f incp z31.s, p0 -[^:]+: 25ac8040 incp z0.s, p2 -[^:]+: 25ac8040 incp z0.s, p2 -[^:]+: 25ac81e0 incp z0.s, p15 -[^:]+: 25ac81e0 incp z0.s, p15 -[^:]+: 25ec8000 incp z0.d, p0 -[^:]+: 25ec8000 incp z0.d, p0 -[^:]+: 25ec8001 incp z1.d, p0 -[^:]+: 25ec8001 incp z1.d, p0 -[^:]+: 25ec801f incp z31.d, p0 -[^:]+: 25ec801f incp z31.d, p0 -[^:]+: 25ec8040 incp z0.d, p2 -[^:]+: 25ec8040 incp z0.d, p2 -[^:]+: 25ec81e0 incp z0.d, p15 -[^:]+: 25ec81e0 incp z0.d, p15 +[^:]+: 256c8000 incp z0.h, p0.h +[^:]+: 256c8000 incp z0.h, p0.h +[^:]+: 256c8001 incp z1.h, p0.h +[^:]+: 256c8001 incp z1.h, p0.h +[^:]+: 256c801f incp z31.h, p0.h +[^:]+: 256c801f incp z31.h, p0.h +[^:]+: 256c8040 incp z0.h, p2.h +[^:]+: 256c8040 incp z0.h, p2.h +[^:]+: 256c81e0 incp z0.h, p15.h +[^:]+: 256c81e0 incp z0.h, p15.h +[^:]+: 25ac8000 incp z0.s, p0.s +[^:]+: 25ac8000 incp z0.s, p0.s +[^:]+: 25ac8001 incp z1.s, p0.s +[^:]+: 25ac8001 incp z1.s, p0.s +[^:]+: 25ac801f incp z31.s, p0.s +[^:]+: 25ac801f incp z31.s, p0.s +[^:]+: 25ac8040 incp z0.s, p2.s +[^:]+: 25ac8040 incp z0.s, p2.s +[^:]+: 25ac81e0 incp z0.s, p15.s +[^:]+: 25ac81e0 incp z0.s, p15.s +[^:]+: 25ec8000 incp z0.d, p0.d +[^:]+: 25ec8000 incp z0.d, p0.d +[^:]+: 25ec8001 incp z1.d, p0.d +[^:]+: 25ec8001 incp z1.d, p0.d +[^:]+: 25ec801f incp z31.d, p0.d +[^:]+: 25ec801f incp z31.d, p0.d +[^:]+: 25ec8040 incp z0.d, p2.d +[^:]+: 25ec8040 incp z0.d, p2.d +[^:]+: 25ec81e0 incp z0.d, p15.d +[^:]+: 25ec81e0 incp z0.d, p15.d [^:]+: 252c8800 incp x0, p0.b [^:]+: 252c8800 incp x0, p0.b [^:]+: 252c8801 incp x1, p0.b @@ -28800,36 +28800,36 @@ Disassembly of section .*: [^:]+: 0469f800 sqdech x0, w0, pow2, mul #10 [^:]+: 046ff800 sqdech x0, w0, pow2, mul #16 [^:]+: 046ff800 sqdech x0, w0, pow2, mul #16 -[^:]+: 256a8000 sqdecp z0.h, p0 -[^:]+: 256a8000 sqdecp z0.h, p0 -[^:]+: 256a8001 sqdecp z1.h, p0 -[^:]+: 256a8001 sqdecp z1.h, p0 -[^:]+: 256a801f sqdecp z31.h, p0 -[^:]+: 256a801f sqdecp z31.h, p0 -[^:]+: 256a8040 sqdecp z0.h, p2 -[^:]+: 256a8040 sqdecp z0.h, p2 -[^:]+: 256a81e0 sqdecp z0.h, p15 -[^:]+: 256a81e0 sqdecp z0.h, p15 -[^:]+: 25aa8000 sqdecp z0.s, p0 -[^:]+: 25aa8000 sqdecp z0.s, p0 -[^:]+: 25aa8001 sqdecp z1.s, p0 -[^:]+: 25aa8001 sqdecp z1.s, p0 -[^:]+: 25aa801f sqdecp z31.s, p0 -[^:]+: 25aa801f sqdecp z31.s, p0 -[^:]+: 25aa8040 sqdecp z0.s, p2 -[^:]+: 25aa8040 sqdecp z0.s, p2 -[^:]+: 25aa81e0 sqdecp z0.s, p15 -[^:]+: 25aa81e0 sqdecp z0.s, p15 -[^:]+: 25ea8000 sqdecp z0.d, p0 -[^:]+: 25ea8000 sqdecp z0.d, p0 -[^:]+: 25ea8001 sqdecp z1.d, p0 -[^:]+: 25ea8001 sqdecp z1.d, p0 -[^:]+: 25ea801f sqdecp z31.d, p0 -[^:]+: 25ea801f sqdecp z31.d, p0 -[^:]+: 25ea8040 sqdecp z0.d, p2 -[^:]+: 25ea8040 sqdecp z0.d, p2 -[^:]+: 25ea81e0 sqdecp z0.d, p15 -[^:]+: 25ea81e0 sqdecp z0.d, p15 +[^:]+: 256a8000 sqdecp z0.h, p0.h +[^:]+: 256a8000 sqdecp z0.h, p0.h +[^:]+: 256a8001 sqdecp z1.h, p0.h +[^:]+: 256a8001 sqdecp z1.h, p0.h +[^:]+: 256a801f sqdecp z31.h, p0.h +[^:]+: 256a801f sqdecp z31.h, p0.h +[^:]+: 256a8040 sqdecp z0.h, p2.h +[^:]+: 256a8040 sqdecp z0.h, p2.h +[^:]+: 256a81e0 sqdecp z0.h, p15.h +[^:]+: 256a81e0 sqdecp z0.h, p15.h +[^:]+: 25aa8000 sqdecp z0.s, p0.s +[^:]+: 25aa8000 sqdecp z0.s, p0.s +[^:]+: 25aa8001 sqdecp z1.s, p0.s +[^:]+: 25aa8001 sqdecp z1.s, p0.s +[^:]+: 25aa801f sqdecp z31.s, p0.s +[^:]+: 25aa801f sqdecp z31.s, p0.s +[^:]+: 25aa8040 sqdecp z0.s, p2.s +[^:]+: 25aa8040 sqdecp z0.s, p2.s +[^:]+: 25aa81e0 sqdecp z0.s, p15.s +[^:]+: 25aa81e0 sqdecp z0.s, p15.s +[^:]+: 25ea8000 sqdecp z0.d, p0.d +[^:]+: 25ea8000 sqdecp z0.d, p0.d +[^:]+: 25ea8001 sqdecp z1.d, p0.d +[^:]+: 25ea8001 sqdecp z1.d, p0.d +[^:]+: 25ea801f sqdecp z31.d, p0.d +[^:]+: 25ea801f sqdecp z31.d, p0.d +[^:]+: 25ea8040 sqdecp z0.d, p2.d +[^:]+: 25ea8040 sqdecp z0.d, p2.d +[^:]+: 25ea81e0 sqdecp z0.d, p15.d +[^:]+: 25ea81e0 sqdecp z0.d, p15.d [^:]+: 252a8c00 sqdecp x0, p0.b [^:]+: 252a8c00 sqdecp x0, p0.b [^:]+: 252a8c01 sqdecp x1, p0.b @@ -30151,36 +30151,36 @@ Disassembly of section .*: [^:]+: 0469f000 sqinch x0, w0, pow2, mul #10 [^:]+: 046ff000 sqinch x0, w0, pow2, mul #16 [^:]+: 046ff000 sqinch x0, w0, pow2, mul #16 -[^:]+: 25688000 sqincp z0.h, p0 -[^:]+: 25688000 sqincp z0.h, p0 -[^:]+: 25688001 sqincp z1.h, p0 -[^:]+: 25688001 sqincp z1.h, p0 -[^:]+: 2568801f sqincp z31.h, p0 -[^:]+: 2568801f sqincp z31.h, p0 -[^:]+: 25688040 sqincp z0.h, p2 -[^:]+: 25688040 sqincp z0.h, p2 -[^:]+: 256881e0 sqincp z0.h, p15 -[^:]+: 256881e0 sqincp z0.h, p15 -[^:]+: 25a88000 sqincp z0.s, p0 -[^:]+: 25a88000 sqincp z0.s, p0 -[^:]+: 25a88001 sqincp z1.s, p0 -[^:]+: 25a88001 sqincp z1.s, p0 -[^:]+: 25a8801f sqincp z31.s, p0 -[^:]+: 25a8801f sqincp z31.s, p0 -[^:]+: 25a88040 sqincp z0.s, p2 -[^:]+: 25a88040 sqincp z0.s, p2 -[^:]+: 25a881e0 sqincp z0.s, p15 -[^:]+: 25a881e0 sqincp z0.s, p15 -[^:]+: 25e88000 sqincp z0.d, p0 -[^:]+: 25e88000 sqincp z0.d, p0 -[^:]+: 25e88001 sqincp z1.d, p0 -[^:]+: 25e88001 sqincp z1.d, p0 -[^:]+: 25e8801f sqincp z31.d, p0 -[^:]+: 25e8801f sqincp z31.d, p0 -[^:]+: 25e88040 sqincp z0.d, p2 -[^:]+: 25e88040 sqincp z0.d, p2 -[^:]+: 25e881e0 sqincp z0.d, p15 -[^:]+: 25e881e0 sqincp z0.d, p15 +[^:]+: 25688000 sqincp z0.h, p0.h +[^:]+: 25688000 sqincp z0.h, p0.h +[^:]+: 25688001 sqincp z1.h, p0.h +[^:]+: 25688001 sqincp z1.h, p0.h +[^:]+: 2568801f sqincp z31.h, p0.h +[^:]+: 2568801f sqincp z31.h, p0.h +[^:]+: 25688040 sqincp z0.h, p2.h +[^:]+: 25688040 sqincp z0.h, p2.h +[^:]+: 256881e0 sqincp z0.h, p15.h +[^:]+: 256881e0 sqincp z0.h, p15.h +[^:]+: 25a88000 sqincp z0.s, p0.s +[^:]+: 25a88000 sqincp z0.s, p0.s +[^:]+: 25a88001 sqincp z1.s, p0.s +[^:]+: 25a88001 sqincp z1.s, p0.s +[^:]+: 25a8801f sqincp z31.s, p0.s +[^:]+: 25a8801f sqincp z31.s, p0.s +[^:]+: 25a88040 sqincp z0.s, p2.s +[^:]+: 25a88040 sqincp z0.s, p2.s +[^:]+: 25a881e0 sqincp z0.s, p15.s +[^:]+: 25a881e0 sqincp z0.s, p15.s +[^:]+: 25e88000 sqincp z0.d, p0.d +[^:]+: 25e88000 sqincp z0.d, p0.d +[^:]+: 25e88001 sqincp z1.d, p0.d +[^:]+: 25e88001 sqincp z1.d, p0.d +[^:]+: 25e8801f sqincp z31.d, p0.d +[^:]+: 25e8801f sqincp z31.d, p0.d +[^:]+: 25e88040 sqincp z0.d, p2.d +[^:]+: 25e88040 sqincp z0.d, p2.d +[^:]+: 25e881e0 sqincp z0.d, p15.d +[^:]+: 25e881e0 sqincp z0.d, p15.d [^:]+: 25288c00 sqincp x0, p0.b [^:]+: 25288c00 sqincp x0, p0.b [^:]+: 25288c01 sqincp x1, p0.b diff --git a/gas/testsuite/gas/aarch64/sve.s b/gas/testsuite/gas/aarch64/sve.s index f3ca5e886733..4037c57f4f77 100644 --- a/gas/testsuite/gas/aarch64/sve.s +++ b/gas/testsuite/gas/aarch64/sve.s @@ -7214,36 +7214,36 @@ DECH X0, POW2, MUL #10 dech x0, pow2, mul #16 DECH X0, POW2, MUL #16 - decp z0.h, p0 - DECP Z0.H, P0 - decp z1.h, p0 - DECP Z1.H, P0 - decp z31.h, p0 - DECP Z31.H, P0 - decp z0.h, p2 - DECP Z0.H, P2 - decp z0.h, p15 - DECP Z0.H, P15 - decp z0.s, p0 - DECP Z0.S, P0 - decp z1.s, p0 - DECP Z1.S, P0 - decp z31.s, p0 - DECP Z31.S, P0 - decp z0.s, p2 - DECP Z0.S, P2 - decp z0.s, p15 - DECP Z0.S, P15 - decp z0.d, p0 - DECP Z0.D, P0 - decp z1.d, p0 - DECP Z1.D, P0 - decp z31.d, p0 - DECP Z31.D, P0 - decp z0.d, p2 - DECP Z0.D, P2 - decp z0.d, p15 - DECP Z0.D, P15 + decp z0.h, p0.h + DECP Z0.H, P0.H + decp z1.h, p0.h + DECP Z1.H, P0.H + decp z31.h, p0.h + DECP Z31.H, P0.H + decp z0.h, p2.h + DECP Z0.H, P2.H + decp z0.h, p15.h + DECP Z0.H, P15.H + decp z0.s, p0.s + DECP Z0.S, P0.S + decp z1.s, p0.s + DECP Z1.S, P0.S + decp z31.s, p0.s + DECP Z31.S, P0.S + decp z0.s, p2.s + DECP Z0.S, P2.S + decp z0.s, p15.s + DECP Z0.S, P15.S + decp z0.d, p0.d + DECP Z0.D, P0.D + decp z1.d, p0.d + DECP Z1.D, P0.D + decp z31.d, p0.d + DECP Z31.D, P0.D + decp z0.d, p2.d + DECP Z0.D, P2.D + decp z0.d, p15.d + DECP Z0.D, P15.D decp x0, p0.b DECP X0, P0.B decp x1, p0.b @@ -13040,36 +13040,36 @@ INCH X0, POW2, MUL #10 inch x0, pow2, mul #16 INCH X0, POW2, MUL #16 - incp z0.h, p0 - INCP Z0.H, P0 - incp z1.h, p0 - INCP Z1.H, P0 - incp z31.h, p0 - INCP Z31.H, P0 - incp z0.h, p2 - INCP Z0.H, P2 - incp z0.h, p15 - INCP Z0.H, P15 - incp z0.s, p0 - INCP Z0.S, P0 - incp z1.s, p0 - INCP Z1.S, P0 - incp z31.s, p0 - INCP Z31.S, P0 - incp z0.s, p2 - INCP Z0.S, P2 - incp z0.s, p15 - INCP Z0.S, P15 - incp z0.d, p0 - INCP Z0.D, P0 - incp z1.d, p0 - INCP Z1.D, P0 - incp z31.d, p0 - INCP Z31.D, P0 - incp z0.d, p2 - INCP Z0.D, P2 - incp z0.d, p15 - INCP Z0.D, P15 + incp z0.h, p0.h + INCP Z0.H, P0.H + incp z1.h, p0.h + INCP Z1.H, P0.H + incp z31.h, p0.h + INCP Z31.H, P0.H + incp z0.h, p2.h + INCP Z0.H, P2.H + incp z0.h, p15.h + INCP Z0.H, P15.H + incp z0.s, p0.s + INCP Z0.S, P0.S + incp z1.s, p0.s + INCP Z1.S, P0.S + incp z31.s, p0.s + INCP Z31.S, P0.S + incp z0.s, p2.s + INCP Z0.S, P2.S + incp z0.s, p15.s + INCP Z0.S, P15.S + incp z0.d, p0.d + INCP Z0.D, P0.D + incp z1.d, p0.d + INCP Z1.D, P0.D + incp z31.d, p0.d + INCP Z31.D, P0.D + incp z0.d, p2.d + INCP Z0.D, P2.D + incp z0.d, p15.d + INCP Z0.D, P15.D incp x0, p0.b INCP X0, P0.B incp x1, p0.b @@ -28809,36 +28809,36 @@ SQDECH X0, W0, POW2, MUL #10 sqdech x0, w0, pow2, mul #16 SQDECH X0, W0, POW2, MUL #16 - sqdecp z0.h, p0 - SQDECP Z0.H, P0 - sqdecp z1.h, p0 - SQDECP Z1.H, P0 - sqdecp z31.h, p0 - SQDECP Z31.H, P0 - sqdecp z0.h, p2 - SQDECP Z0.H, P2 - sqdecp z0.h, p15 - SQDECP Z0.H, P15 - sqdecp z0.s, p0 - SQDECP Z0.S, P0 - sqdecp z1.s, p0 - SQDECP Z1.S, P0 - sqdecp z31.s, p0 - SQDECP Z31.S, P0 - sqdecp z0.s, p2 - SQDECP Z0.S, P2 - sqdecp z0.s, p15 - SQDECP Z0.S, P15 - sqdecp z0.d, p0 - SQDECP Z0.D, P0 - sqdecp z1.d, p0 - SQDECP Z1.D, P0 - sqdecp z31.d, p0 - SQDECP Z31.D, P0 - sqdecp z0.d, p2 - SQDECP Z0.D, P2 - sqdecp z0.d, p15 - SQDECP Z0.D, P15 + sqdecp z0.h, p0.h + SQDECP Z0.H, P0.H + sqdecp z1.h, p0.h + SQDECP Z1.H, P0.H + sqdecp z31.h, p0.h + SQDECP Z31.H, P0.H + sqdecp z0.h, p2.h + SQDECP Z0.H, P2.H + sqdecp z0.h, p15.h + SQDECP Z0.H, P15.H + sqdecp z0.s, p0.s + SQDECP Z0.S, P0.S + sqdecp z1.s, p0.s + SQDECP Z1.S, P0.S + sqdecp z31.s, p0.s + SQDECP Z31.S, P0.S + sqdecp z0.s, p2.s + SQDECP Z0.S, P2.S + sqdecp z0.s, p15.s + SQDECP Z0.S, P15.S + sqdecp z0.d, p0.d + SQDECP Z0.D, P0.D + sqdecp z1.d, p0.d + SQDECP Z1.D, P0.D + sqdecp z31.d, p0.d + SQDECP Z31.D, P0.D + sqdecp z0.d, p2.d + SQDECP Z0.D, P2.D + sqdecp z0.d, p15.d + SQDECP Z0.D, P15.D sqdecp x0, p0.b SQDECP X0, P0.B sqdecp x1, p0.b @@ -30160,36 +30160,36 @@ SQINCH X0, W0, POW2, MUL #10 sqinch x0, w0, pow2, mul #16 SQINCH X0, W0, POW2, MUL #16 - sqincp z0.h, p0 - SQINCP Z0.H, P0 - sqincp z1.h, p0 - SQINCP Z1.H, P0 - sqincp z31.h, p0 - SQINCP Z31.H, P0 - sqincp z0.h, p2 - SQINCP Z0.H, P2 - sqincp z0.h, p15 - SQINCP Z0.H, P15 - sqincp z0.s, p0 - SQINCP Z0.S, P0 - sqincp z1.s, p0 - SQINCP Z1.S, P0 - sqincp z31.s, p0 - SQINCP Z31.S, P0 - sqincp z0.s, p2 - SQINCP Z0.S, P2 - sqincp z0.s, p15 - SQINCP Z0.S, P15 - sqincp z0.d, p0 - SQINCP Z0.D, P0 - sqincp z1.d, p0 - SQINCP Z1.D, P0 - sqincp z31.d, p0 - SQINCP Z31.D, P0 - sqincp z0.d, p2 - SQINCP Z0.D, P2 - sqincp z0.d, p15 - SQINCP Z0.D, P15 + sqincp z0.h, p0.h + SQINCP Z0.H, P0.H + sqincp z1.h, p0.h + SQINCP Z1.H, P0.H + sqincp z31.h, p0.h + SQINCP Z31.H, P0.H + sqincp z0.h, p2.h + SQINCP Z0.H, P2.H + sqincp z0.h, p15.h + SQINCP Z0.H, P15.H + sqincp z0.s, p0.s + SQINCP Z0.S, P0.S + sqincp z1.s, p0.s + SQINCP Z1.S, P0.S + sqincp z31.s, p0.s + SQINCP Z31.S, P0.S + sqincp z0.s, p2.s + SQINCP Z0.S, P2.S + sqincp z0.s, p15.s + SQINCP Z0.S, P15.S + sqincp z0.d, p0.d + SQINCP Z0.D, P0.D + sqincp z1.d, p0.d + SQINCP Z1.D, P0.D + sqincp z31.d, p0.d + SQINCP Z31.D, P0.D + sqincp z0.d, p2.d + SQINCP Z0.D, P2.D + sqincp z0.d, p15.d + SQINCP Z0.D, P15.D sqincp x0, p0.b SQINCP X0, P0.B sqincp x1, p0.b diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index cb039d63eba3..1b984080aa11 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4200,7 +4200,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = _SVE_INSN ("decd", 0x04f0e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), _SVE_INSNC ("dech", 0x0470c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), _SVE_INSN ("dech", 0x0470e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), - _SVE_INSNC ("decp", 0x252d8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), + _SVE_INSNC ("decp", 0x252d8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VV_HSD, 0, C_SCAN_MOVPRFX, 0), _SVE_INSN ("decp", 0x252d8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), _SVE_INSNC ("decw", 0x04b0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), _SVE_INSN ("decw", 0x04b0e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), @@ -4325,7 +4325,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = _SVE_INSN ("incd", 0x04f0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), _SVE_INSNC ("inch", 0x0470c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), _SVE_INSN ("inch", 0x0470e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), - _SVE_INSNC ("incp", 0x252c8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), + _SVE_INSNC ("incp", 0x252c8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VV_HSD, 0, C_SCAN_MOVPRFX, 0), _SVE_INSN ("incp", 0x252c8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), _SVE_INSNC ("incw", 0x04b0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), _SVE_INSN ("incw", 0x04b0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), @@ -4688,7 +4688,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = _SVE_INSNC ("sqdech", 0x0460c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), _SVE_INSN ("sqdech", 0x0470f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), _SVE_INSN ("sqdech", 0x0460f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), - _SVE_INSNC ("sqdecp", 0x252a8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), + _SVE_INSNC ("sqdecp", 0x252a8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VV_HSD, 0, C_SCAN_MOVPRFX, 0), _SVE_INSN ("sqdecp", 0x252a8c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), _SVE_INSN ("sqdecp", 0x252a8800, 0xff3ffe00, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_5, Rd), OP_SVE_XVW_BHSD, 0, 2), _SVE_INSNC ("sqdecw", 0x04a0c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), @@ -4702,7 +4702,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = _SVE_INSNC ("sqinch", 0x0460c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), _SVE_INSN ("sqinch", 0x0470f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0), _SVE_INSN ("sqinch", 0x0460f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1), - _SVE_INSNC ("sqincp", 0x25288000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0), + _SVE_INSNC ("sqincp", 0x25288000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VV_HSD, 0, C_SCAN_MOVPRFX, 0), _SVE_INSN ("sqincp", 0x25288c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0), _SVE_INSN ("sqincp", 0x25288800, 0xff3ffe00, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_5, Rd), OP_SVE_XVW_BHSD, 0, 2), _SVE_INSNC ("sqincw", 0x04a0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0), -- 2.33.0