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From: Palmer Dabbelt <palmer@rivosinc.com>
To: binutils@sourceware.org
Subject: [PATCH v1] binutils/doc: Document the RISC-V -M options
Date: Thu, 24 Feb 2022 10:30:46 -0800	[thread overview]
Message-ID: <20220224183046.13473-1-palmer@rivosinc.com> (raw)

These have been around for quite a while now, but we forgot to actually
document them.

	* doc/binutils.texi (-M): New section on RISC-V options.

Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 binutils/doc/binutils.texi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi
index 288974be386..bfb5a6199ca 100644
--- a/binutils/doc/binutils.texi
+++ b/binutils/doc/binutils.texi
@@ -2693,6 +2693,19 @@ rather than names, for the selected types of registers.
 You can list the available values of @var{ABI} and @var{ARCH} using
 the @option{--help} option.
 
+For RISC-V, this option controls how instructions are disassembled.  This
+option can be provided multiple times, each time with a comma separated list
+containing one or more of the following entries:
+
+@table @code
+@item no-aliases
+Avoid printing pseudo instruction mnemonics.
+
+@item numeric
+Use numeric register names (ie, x1) instead of ABI register names (ie, ra) when
+printing instructions.
+@end table
+
 For VAX, you can specify function entry addresses with @option{-M
 entry:0xf00ba}.  You can use this multiple times to properly
 disassemble VAX binary files that don't contain symbol tables (like
-- 
2.34.1


             reply	other threads:[~2022-02-24 18:32 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-24 18:30 Palmer Dabbelt [this message]
2022-02-25  0:59 ` Nelson Chu

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