From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTP id 3A3343858C74 for ; Tue, 15 Mar 2022 02:43:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3A3343858C74 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [58.213.0.226]) by APP-05 (Coremail) with SMTP id zQCowABHdUBO_S9iIv99Aw--.38493S2; Tue, 15 Mar 2022 10:43:27 +0800 (CST) From: shihua@iscas.ac.cn To: binutils@sourceware.org Cc: kito.cheng@sifive.com, jim.wilson.gcc@gmail.com, cmuellner@ventanamicro.com, palmer@dabbelt.com, andrew@sifive.com, lazyparser@gmail.com, jiawei@iscas.ac.cn, nelson.chu@sifive.com, LiaoShihua Subject: [PATCH] RISC-V: Support ZTSO extension Date: Tue, 15 Mar 2022 10:43:18 +0800 Message-Id: <20220315024318.297-1-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.31.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: zQCowABHdUBO_S9iIv99Aw--.38493S2 X-Coremail-Antispam: 1UD129KBjvJXoWxuw4rWw43Jr1rWF45AF4rGrg_yoW7XrWrpF s5Gayj9F90yF1xXrs3XF4UKr43Xw4I9FW3Cr1Yk3y5Awn7Jr48Xr97t3WrCFs8JF4kuFW2 9a4rKry5ua1kArUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9C14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr 1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv 7VC0I7IYx2IY67AKxVWUXVWUAwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r 1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02 628vn2kIc2xKxwAKzVCY07xG64k0F24lc2xSY4AK67AK6r4UMxAIw28IcxkI7VAKI48JMx C20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAF wI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20x vE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAIw20EY4v2 0xvaj40_WFyUJVCq3wCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14 v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x0JUHwZcUUUUU= X-Originating-IP: [58.213.0.226] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiBgkGEV0TgDE0EgACsD X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 Mar 2022 02:43:36 -0000 From: LiaoShihua ZTSO is the extension of tatol store order model. This extension adds no new instructions to the ISA, and you can use it with arch "ztso". If you use it, TSO flag will be generate in the ELF header. bfd\ChangeLog: * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data):Add support for ztso extension. * elfxx-riscv.c (riscv_multi_subset_supports):Ditto. binutils\ChangeLog: * readelf.c (get_machine_flags):Ditto. gas\ChangeLog: * config/tc-riscv.c (struct riscv_set_options):Ditto. (riscv_set_tso):Ditto. (riscv_set_arch):Ditto. include\ChangeLog: * elf/riscv.h (EF_RISCV_TSO):Ditto. * opcode/riscv.h (enum riscv_insn_class):Ditto. --- bfd/elfnn-riscv.c | 3 +++ bfd/elfxx-riscv.c | 3 +++ binutils/readelf.c | 3 +++ gas/config/tc-riscv.c | 17 +++++++++++++++++ include/elf/riscv.h | 3 +++ include/opcode/riscv.h | 1 + 6 files changed, 30 insertions(+) diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c index 8f9f0d8a86a..25e8082b957 100644 --- a/bfd/elfnn-riscv.c +++ b/bfd/elfnn-riscv.c @@ -3886,6 +3886,9 @@ _bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info) /* Allow linking RVC and non-RVC, and keep the RVC flag. */ elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_RVC; + /* Allow linking ZTSO and non-ZTSO, and keep the TSO flag. */ + elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_TSO; + return true; fail: diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 2915b74dd0f..a041c89a623 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1215,6 +1215,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zvl16384b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32768b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl65536b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ztso", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2393,6 +2394,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, || riscv_subset_supports (rps, "zve32f")); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); + case INSN_CLASS_ZTSO: + return riscv_subset_supports (rps, "ztso"); default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); diff --git a/binutils/readelf.c b/binutils/readelf.c index 16efe1dfd2d..ba4d6f9db4f 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -3975,6 +3975,9 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine) if (e_flags & EF_RISCV_RVE) strcat (buf, ", RVE"); + + if (e_flags & EF_RISCV_TSO) + strcat (buf, ", TSO"); switch (e_flags & EF_RISCV_FLOAT_ABI) { diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 9cc0abfda88..ed33cfa919a 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -222,6 +222,7 @@ struct riscv_set_options int relax; /* Emit relocs the linker is allowed to relax. */ int arch_attr; /* Emit architecture and privileged elf attributes. */ int csr_check; /* Enable the CSR checking. */ + int tso; /* Use TSO model. */ }; static struct riscv_set_options riscv_opts = @@ -231,6 +232,7 @@ static struct riscv_set_options riscv_opts = 1, /* relax */ DEFAULT_RISCV_ATTR, /* arch_attr */ 0, /* csr_check */ + 0, /* tso */ }; /* Enable or disable the rvc flags for riscv_opts. Turn on the rvc flag @@ -245,6 +247,18 @@ riscv_set_rvc (bool rvc_value) riscv_opts.rvc = rvc_value; } +/* Enable or disable the tso flags for riscv_opts. Turn on the tso flag + for elf_flags once we have enabled ztso extension. */ + +static void +riscv_set_tso (bool tso_value) +{ + if (tso_value) + elf_flags |= EF_RISCV_TSO; + + riscv_opts.tso = tso_value; +} + /* This linked list records all enabled extensions, which are parsed from the architecture string. The architecture string can be set by the -march option, the elf architecture attributes, and the --with-arch @@ -295,6 +309,9 @@ riscv_set_arch (const char *s) riscv_set_rvc (false); if (riscv_subset_supports (&riscv_rps_as, "c")) riscv_set_rvc (true); + + if (riscv_subset_supports (&riscv_rps_as, "ztso")) + riscv_set_tso (true); } /* Indicate -mabi option is explictly set. */ diff --git a/include/elf/riscv.h b/include/elf/riscv.h index d0acf6886d8..eed3ec5f82e 100644 --- a/include/elf/riscv.h +++ b/include/elf/riscv.h @@ -114,6 +114,9 @@ END_RELOC_NUMBERS (R_RISCV_max) /* File uses the 32E base integer instruction. */ #define EF_RISCV_RVE 0x0008 +/* File uses the TSO model. */ +#define EF_RISCV_TSO 0x0010 + /* The name of the global pointer symbol. */ #define RISCV_GP_SYMBOL "__global_pointer$" diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 048ab0a5d68..ed81df271c1 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -388,6 +388,7 @@ enum riscv_insn_class INSN_CLASS_V, INSN_CLASS_ZVEF, INSN_CLASS_SVINVAL, + INSN_CLASS_ZTSO, }; /* This structure holds information for a particular instruction. */ -- 2.31.1.windows.1