From: Alan Modra <amodra@gmail.com>
To: binutils@sourceware.org
Subject: [PATCH 2/5] PowerPC32 extended instructions in powerpc_macros
Date: Wed, 16 Mar 2022 10:10:56 +1030 [thread overview]
Message-ID: <20220315234059.4142748-2-amodra@gmail.com> (raw)
In-Reply-To: <20220315234059.4142748-1-amodra@gmail.com>
As for PowerPC64, move instructions to the main opcode table.
opcodes/
* ppc-opc.c (insert_crwn, extract_crwn, insert_elwn, extract_elwn),
(insert_erwn, extract_erwn, insert_erwb, extract_erwb),
(insert_cslwn, extract_cslwb, insert_ilwb, extract_ilwn),
(insert_irwb, extract_irwn, insert_rrwn, extract_rrwn),
(insert_slwn, extract_slwn, insert_srwn, extract_srwn): New functions.
(CRWn, ELWn, ERWn, ERWb, CSLWb, CSLWn, ILWn, ILWb, IRWn, IRWb),
(RRWn, SLWn, SRWn): Define and add powerpc_operands entries.
(MMB_MASK, MME_MASK, MSHMB_MASK): Define.
(powerpc_opcodes): Add "inslwi", "insrwi", "rotrwi", "clrrwi",
"slwi", "srwi", "extlwi", "extrwi", "sli", "sri" and corresponding
record (ie. dot suffix) forms.
(powerpc_macros): Delete same.
gas/
* testsuite/gas/ppc/476.d: Update.
* testsuite/gas/ppc/simpshft.d: Update.
diff --git a/gas/testsuite/gas/ppc/476.d b/gas/testsuite/gas/ppc/476.d
index 0b75d75ae2d..70ea88d001e 100644
--- a/gas/testsuite/gas/ppc/476.d
+++ b/gas/testsuite/gas/ppc/476.d
@@ -59,7 +59,7 @@ Disassembly of section \.text:
.*: (4c 86 00 21|21 00 86 4c) bnelrl cr1
.*: (48 00 00 00|00 00 00 48) b c8 <ppc476\+0xc8>
.*: (48 00 00 01|01 00 00 48) bl cc <ppc476\+0xcc>
-.*: (54 83 00 36|36 00 83 54) rlwinm r3,r4,0,0,27
+.*: (54 83 00 36|36 00 83 54) clrrwi r3,r4,4
.*: (7c 03 20 00|00 20 03 7c) cmpw r3,r4
.*: (7f 83 20 00|00 20 83 7f) cmpw cr7,r3,r4
.*: (7c 83 2b f8|f8 2b 83 7c) cmpb r3,r4,r5
@@ -401,10 +401,10 @@ Disassembly of section \.text:
.*: (4c 00 00 4c|4c 00 00 4c) rfmci
.*: (50 83 65 36|36 65 83 50) rlwimi r3,r4,12,20,27
.*: (50 83 65 37|37 65 83 50) rlwimi\. r3,r4,12,20,27
-.*: (54 83 00 36|36 00 83 54) rlwinm r3,r4,0,0,27
-.*: (54 83 d1 be|be d1 83 54) rlwinm r3,r4,26,6,31
+.*: (54 83 00 36|36 00 83 54) clrrwi r3,r4,4
+.*: (54 83 d1 be|be d1 83 54) srwi r3,r4,6
.*: (54 83 20 26|26 20 83 54) rlwinm r3,r4,4,0,19
-.*: (54 83 00 37|37 00 83 54) rlwinm\. r3,r4,0,0,27
+.*: (54 83 00 37|37 00 83 54) clrrwi\. r3,r4,4
.*: (5c 83 28 3e|3e 28 83 5c) rotlw r3,r4,r5
.*: (5c 83 28 3f|3f 28 83 5c) rotlw\. r3,r4,r5
.*: (5c 83 28 3e|3e 28 83 5c) rotlw r3,r4,r5
@@ -418,7 +418,7 @@ Disassembly of section \.text:
.*: (7c 83 86 71|71 86 83 7c) srawi\. r3,r4,16
.*: (7c 83 2c 30|30 2c 83 7c) srw r3,r4,r5
.*: (7c 83 2c 31|31 2c 83 7c) srw\. r3,r4,r5
-.*: (54 83 d1 be|be d1 83 54) rlwinm r3,r4,26,6,31
+.*: (54 83 d1 be|be d1 83 54) srwi r3,r4,6
.*: (99 61 00 02|02 00 61 99) stb r11,2\(r1\)
.*: (9d 81 00 03|03 00 81 9d) stbu r12,3\(r1\)
.*: (7d ae 79 ee|ee 79 ae 7d) stbux r13,r14,r15
diff --git a/gas/testsuite/gas/ppc/simpshft.d b/gas/testsuite/gas/ppc/simpshft.d
index b88752c8a38..70b8e02797f 100644
--- a/gas/testsuite/gas/ppc/simpshft.d
+++ b/gas/testsuite/gas/ppc/simpshft.d
@@ -11,9 +11,9 @@ Disassembly of section .text:
4: (0e f8 83 78|78 83 f8 0e) rldimi r3,r4,63,0
8: (e4 45 a5 78|78 a5 45 e4) sldi r5,r5,8
c: (20 00 64 78|78 64 00 20) clrldi r4,r3,32
- 10: (fe 0f 64 54|54 64 0f fe) rlwinm r4,r3,1,31,31
+ 10: (fe 0f 64 54|54 64 0f fe) srwi r4,r3,31
14: (00 f8 83 50|50 83 f8 00) rlwimi r3,r4,31,0,0
- 18: (2e 40 a5 54|54 a5 40 2e) rlwinm r5,r5,8,0,23
+ 18: (2e 40 a5 54|54 a5 40 2e) slwi r5,r5,8
1c: (3e 04 64 54|54 64 04 3e) clrlwi r4,r3,16
20: (04 00 64 78|78 64 00 04) clrrdi r4,r3,63
24: (e4 07 64 78|78 64 07 e4) clrrdi r4,r3,0
@@ -48,11 +48,11 @@ Disassembly of section .text:
98: (e8 07 64 78|78 64 07 e8) rldic r4,r3,0,63
9c: (a8 0f 64 78|78 64 0f a8) rldic r4,r3,1,62
a0: (0a f8 64 78|78 64 f8 0a) rldic r4,r3,63,0
- a4: (00 00 64 54|54 64 00 00) rlwinm r4,r3,0,0,0
+ a4: (00 00 64 54|54 64 00 00) clrrwi r4,r3,31
a8: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
- ac: (00 f8 64 54|54 64 f8 00) rlwinm r4,r3,31,0,0
+ ac: (00 f8 64 54|54 64 f8 00) slwi r4,r3,31
b0: (3e f8 64 54|54 64 f8 3e) rotlwi r4,r3,31
- b4: (7e f8 64 54|54 64 f8 7e) rlwinm r4,r3,31,1,31
+ b4: (7e f8 64 54|54 64 f8 7e) srwi r4,r3,1
b8: (fe ff 64 54|54 64 ff fe) rlwinm r4,r3,31,31,31
bc: (00 00 64 50|50 64 00 00) rlwimi r4,r3,0,0,0
c0: (3e 00 64 50|50 64 00 3e) rlwimi r4,r3,0,0,31
@@ -68,20 +68,20 @@ Disassembly of section .text:
e8: (3e 08 64 54|54 64 08 3e) rotlwi r4,r3,1
ec: (3e 20 65 5c|5c 65 20 3e) rotlw r5,r3,r4
f0: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
- f4: (3c 08 64 54|54 64 08 3c) rlwinm r4,r3,1,0,30
- f8: (00 f8 64 54|54 64 f8 00) rlwinm r4,r3,31,0,0
+ f4: (3c 08 64 54|54 64 08 3c) slwi r4,r3,1
+ f8: (00 f8 64 54|54 64 f8 00) slwi r4,r3,31
fc: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
- 100: (7e f8 64 54|54 64 f8 7e) rlwinm r4,r3,31,1,31
- 104: (fe 0f 64 54|54 64 0f fe) rlwinm r4,r3,1,31,31
+ 100: (7e f8 64 54|54 64 f8 7e) srwi r4,r3,1
+ 104: (fe 0f 64 54|54 64 0f fe) srwi r4,r3,31
108: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
10c: (7e 00 64 54|54 64 00 7e) clrlwi r4,r3,1
110: (fe 07 64 54|54 64 07 fe) clrlwi r4,r3,31
114: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
- 118: (3c 00 64 54|54 64 00 3c) rlwinm r4,r3,0,0,30
- 11c: (00 00 64 54|54 64 00 00) rlwinm r4,r3,0,0,0
+ 118: (3c 00 64 54|54 64 00 3c) clrrwi r4,r3,1
+ 11c: (00 00 64 54|54 64 00 00) clrrwi r4,r3,31
120: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
124: (7e 00 64 54|54 64 00 7e) clrlwi r4,r3,1
128: (fe 07 64 54|54 64 07 fe) clrlwi r4,r3,31
12c: (bc 0f 64 54|54 64 0f bc) rlwinm r4,r3,1,30,30
- 130: (00 f8 64 54|54 64 f8 00) rlwinm r4,r3,31,0,0
+ 130: (00 f8 64 54|54 64 f8 00) slwi r4,r3,31
#pass
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 20844875740..45d07196309 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1058,6 +1058,165 @@ extract_esync (uint64_t insn,
return value;
}
+/* The n operand of clrrwi, which sets the ME field to 31 - n. */
+
+static uint64_t
+insert_crwn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((~value & 0x1f) << 1);
+}
+
+static int64_t
+extract_crwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ~(insn >> 1) & 0x1f;
+}
+
+/* The n operand of extlwi, which sets the ME field to n - 1. */
+
+static uint64_t
+insert_elwn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | (((value - 1) & 0x1f) << 1);
+}
+
+static int64_t
+extract_elwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 1) & 0x1f) + 1;
+}
+
+/* The n operand of extrwi, sets MB = 32 - n. */
+
+static uint64_t
+insert_erwn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((-value & 0x1f) << 6);
+}
+
+static int64_t
+extract_erwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return (~(insn >> 6) & 0x1f) + 1;
+}
+
+/* The b operand of extrwi, sets SH = b + n. */
+
+static uint64_t
+insert_erwb (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ int64_t n = extract_erwn (insn, dialect, NULL);
+ return insn | (((n + value) & 0x1f) << 11);
+}
+
+static int64_t
+extract_erwb (uint64_t insn,
+ ppc_cpu_t dialect,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ int64_t n = extract_erwn (insn, dialect, NULL);
+ return ((insn >> 11) - n) & 0x1f;
+}
+
+/* The n and b operands of clrlslwi. */
+
+static uint64_t
+insert_cslwn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ uint64_t mb = 0x1f << 6;
+ int64_t b = (insn >> 6) & 0x1f;
+ return ((insn & ~mb) | ((value & 0x1f) << 11) | (((b - value) & 0x1f) << 6)
+ | ((~value & 0x1f) << 1));
+}
+
+static int64_t
+extract_cslwb (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ int64_t sh = (insn >> 11) & 0x1f;
+ int64_t mb = (insn >> 6) & 0x1f;
+ int64_t me = (insn >> 1) & 0x1f;
+ if (sh != 31 - me)
+ *invalid = 1;
+ return (mb + sh) & 0x1f;
+}
+
+/* The n and b operands of inslwi. */
+
+static uint64_t
+insert_ilwb (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ uint64_t me = 0x1f << 1;
+ int64_t n = (insn >> 1) & 0x1f;
+ return ((insn & ~me) | ((-value & 0x1f) << 11) | ((value & 0x1f) << 6)
+ | (((value + n - 1) & 0x1f) << 1));
+}
+
+static int64_t
+extract_ilwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ int64_t sh = (insn >> 11) & 0x1f;
+ int64_t mb = (insn >> 6) & 0x1f;
+ int64_t me = (insn >> 1) & 0x1f;
+ if (((sh + mb) & 0x1f) != 0)
+ *invalid = 1;
+ return ((me - mb) & 0x1f) + 1;
+}
+
+/* The n and b operands of insrwi. */
+
+static uint64_t
+insert_irwb (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ uint64_t me = 0x1f << 1;
+ int64_t n = (insn >> 1) & 0x1f;
+ return ((insn & ~me) | ((-(value + n) & 0x1f) << 11) | ((value & 0x1f) << 6)
+ | (((value + n - 1) & 0x1f) << 1));
+}
+
+static int64_t
+extract_irwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ int64_t sh = (insn >> 11) & 0x1f;
+ int64_t mb = (insn >> 6) & 0x1f;
+ int64_t me = (insn >> 1) & 0x1f;
+ if (((sh + me + 1) & 0x1f) != 0)
+ *invalid = 1;
+ return ((me - mb) & 0x1f) + 1;
+}
+
/* The MB and ME fields in an M form instruction expressed as a single
operand which is itself a bitmask. The extraction function always
marks it as invalid, since we never want to recognize an
@@ -1589,6 +1748,71 @@ extract_oimm (uint64_t insn,
return ((insn >> 4) & 0x1f) + 1;
}
+/* The n operand of rotrwi, sets SH = 32 - n. */
+
+static uint64_t
+insert_rrwn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((-value & 0x1f) << 11);
+}
+
+static int64_t
+extract_rrwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return 31 & -(insn >> 11);
+}
+
+/* The n operand of slwi, sets SH = n and ME = 31 - n. */
+
+static uint64_t
+insert_slwn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x1f) << 11) | ((~value & 0x1f) << 1);
+}
+
+static int64_t
+extract_slwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ int64_t sh = (insn >> 11) & 0x1f;
+ int64_t nme = ~(insn >> 1) & 0x1f;
+ if (sh != nme)
+ *invalid = 1;
+ return sh;
+}
+
+/* The n operand of srwi, sets SH = 32 - n and MB = n. */
+
+static uint64_t
+insert_srwn (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((-value & 0x1f) << 11) | ((value & 0x1f) << 6);
+}
+
+static int64_t
+extract_srwn (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ int64_t nsh = -(insn >> 11) & 0x1f;
+ int64_t mb = (insn >> 6) & 0x1f;
+ if (nsh != mb)
+ *invalid = 1;
+ return nsh;
+}
+
/* The SH field in an MD form instruction. This is split. */
static uint64_t
@@ -2933,11 +3157,41 @@ const struct powerpc_operand powerpc_operands[] =
#define ME_MASK (0x1f << 1)
{ 0x1f, 1, NULL, NULL, 0 },
+#define CRWn ME + 1
+ { 0x1f, 1, insert_crwn, extract_crwn, 0 },
+
+#define ELWn CRWn + 1
+ { 0x1f, 1, insert_elwn, extract_elwn, PPC_OPERAND_PLUS1 },
+
+#define ERWn ELWn + 1
+ { 0x1f, 6, insert_erwn, extract_erwn, 0 },
+
+#define ERWb ERWn + 1
+ { 0x1f, 11, insert_erwb, extract_erwb, 0 },
+
+#define CSLWb ERWb + 1
+ { 0x1f, 6, NULL, extract_cslwb, 0 },
+
+#define CSLWn CSLWb + 1
+ { 0x1f, 11, insert_cslwn, NULL, 0 },
+
+#define ILWn CSLWn + 1
+ { 0x1f, 1, NULL, extract_ilwn, PPC_OPERAND_PLUS1 },
+
+#define ILWb ILWn + 1
+ { 0x1f, 6, insert_ilwb, NULL, 0 },
+
+#define IRWn ILWb + 1
+ { 0x1f, 1, NULL, extract_irwn, PPC_OPERAND_PLUS1 },
+
+#define IRWb IRWn + 1
+ { 0x1f, 6, insert_irwb, NULL, 0 },
+
/* The MB and ME fields in an M form instruction expressed a single
operand which is a bitmask indicating which bits to select. This
is a two operand form using PPC_OPERAND_NEXT. See the
description in opcode/ppc.h for what this means. */
-#define MBE ME + 1
+#define MBE IRWb + 1
{ 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
{ -1, 0, insert_mbe, extract_mbe, 0 },
@@ -3130,7 +3384,16 @@ const struct powerpc_operand powerpc_operands[] =
#define UIM5 SH
{ 0x1f, 11, NULL, NULL, 0 },
-#define EVUIMM_LT8 SH + 1
+#define RRWn SH + 1
+ { 0x1f, 11, insert_rrwn, extract_rrwn, 0 },
+
+#define SLWn RRWn + 1
+ { 0x1f, 11, insert_slwn, extract_slwn, 0 },
+
+#define SRWn SLWn + 1
+ { 0x1f, 11, insert_srwn, extract_srwn, 0 },
+
+#define EVUIMM_LT8 SRWn + 1
{ 0x1f, 11, insert_evuimm_lt8, extract_evuimm_lt8, 0 },
#define EVUIMM_LT16 EVUIMM_LT8 + 1
@@ -3823,12 +4086,21 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
(M ((op), (rc)) \
| ((((uint64_t)(me)) & 0x1f) << 1))
+/* An M_MASK with the MB field fixed. */
+#define MMB_MASK (M_MASK | MB_MASK)
+
+/* An M_MASK with the ME field fixed. */
+#define MME_MASK (M_MASK | ME_MASK)
+
/* An M_MASK with the MB and ME fields fixed. */
#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
/* An M_MASK with the SH and ME fields fixed. */
#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
+/* An M_MASK with the SH and MB fields fixed. */
+#define MSHMB_MASK (M_MASK | SH_MASK | MB_MASK)
+
/* An MD form instruction. */
#define MD(op, xop, rc) \
(OP (op) \
@@ -6425,18 +6697,40 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
+{"inslwi", M(20,0), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ILWn, ILWb}},
+{"insrwi", M(20,0), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, IRWn, IRWb}},
{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
+{"inslwi.", M(20,1), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ILWn, ILWb}},
+{"insrwi.", M(20,1), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, IRWn, IRWb}},
{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SH}},
+{"rotrwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RRWn}},
{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, MB}},
+{"clrrwi", M(21,0), MSHMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CRWn}},
+{"slwi", M(21,0), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SLWn}},
+{"srwi", MME(21,31,0), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SRWn}},
{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
+{"extlwi", M(21,0), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ELWn, SH}},
+{"extrwi", MME(21,31,0), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ERWn, ERWb}},
+{"clrlslwi", M(21,0), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CSLWb, CSLWn}},
+{"sli", M(21,0), MMB_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SLWn}},
+{"sri", MME(21,31,0), MME_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SRWn}},
{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SH}},
+{"rotrwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RRWn}},
{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, MB}},
+{"clrrwi.", M(21,1), MSHMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CRWn}},
+{"slwi.", M(21,1), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SLWn}},
+{"srwi.", MME(21,31,1), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SRWn}},
{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
+{"extlwi.", M(21,1), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ELWn, SH}},
+{"extrwi.", MME(21,31,1), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ERWn, ERWb}},
+{"clrlslwi.", M(21,1), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CSLWb, CSLWn}},
+{"sli.", M(21,1), MMB_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SLWn}},
+{"sri.", MME(21,31,1), MME_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SRWn}},
{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
@@ -10192,29 +10486,6 @@ const unsigned int vle_num_opcodes =
support extracting the whole word (32 bits in this case). */
const struct powerpc_macro powerpc_macros[] = {
-{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
-{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
-{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
-{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
-{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
-{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
-{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
-{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
-{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
-{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
-{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
-{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
-{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
-{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
-{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
-{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
-{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
-{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
-{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
-{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
-{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
-{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
-
{"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
{"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
{"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
next prev parent reply other threads:[~2022-03-15 23:41 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-15 23:40 [PATCH 1/5] PowerPC64 " Alan Modra
2022-03-15 23:40 ` Alan Modra [this message]
2022-03-15 23:40 ` [PATCH 3/5] PowerPC VLE " Alan Modra
2022-03-15 23:40 ` [PATCH 4/5] PowerPC SPE/SPE2 aliases " Alan Modra
2022-03-15 23:40 ` [PATCH 5/5] Delete PowerPC macro insn support Alan Modra
2022-03-18 21:40 ` [PATCH 1/5] PowerPC64 extended instructions in powerpc_macros Peter Bergner
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