From: Patrick O'Neill <patrick@rivosinc.com>
To: binutils@sourceware.org
Cc: gnu-toolchain@rivosinc.com, Patrick O'Neill <patrick@rivosinc.com>
Subject: [RFC] RISCV: Align using RVC insns
Date: Fri, 25 Mar 2022 16:15:43 -0700 [thread overview]
Message-ID: <20220325231543.1505904-1-patrick@rivosinc.com> (raw)
Currently, .align and .balign directives only use nops to achieve
alignment. On RVC targets, the linker can selectively compress
instructions to achieve alignment without introducing nops.
This increases the code size of unlinked binaries since instruction
compression is deferred to the linker. Linked binaries with align
directives may be smaller/run faster due to less nops.
Binaries without align directives should be unaffected by this change.
This change requires adding a reloc for compressable instructions. The
addend of that reloc stores the compressed instruction's opcode.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
bfd/bfd-in2.h | 1 +
bfd/elfnn-riscv.c | 151 +++++++++++++++---
bfd/elfxx-riscv.c | 16 ++
gas/config/tc-riscv.c | 56 +++++--
gas/config/tc-riscv.h | 8 +
gas/testsuite/gas/riscv/c-add-addi.d | 6 +-
gas/testsuite/gas/riscv/c-ld.d | 24 ++-
gas/testsuite/gas/riscv/c-lw.d | 24 ++-
gas/testsuite/gas/riscv/c-zero-imm-64.d | 5 +-
gas/testsuite/gas/riscv/c-zero-imm.d | 30 ++--
gas/testsuite/gas/riscv/ext-32.d | 35 ++--
gas/testsuite/gas/riscv/ext-64.d | 51 +++---
gas/testsuite/gas/riscv/li32.d | 15 +-
gas/testsuite/gas/riscv/li64.d | 90 +++++++----
gas/testsuite/gas/riscv/no-relax-align-2.d | 4 +-
gas/testsuite/gas/riscv/option-arch-01a.d | 5 +-
include/elf/riscv.h | 1 +
ld/emultempl/riscvelf.em | 2 +-
ld/testsuite/ld-riscv-elf/align-comp-1.d | 14 ++
ld/testsuite/ld-riscv-elf/align-comp-1.s | 7 +
ld/testsuite/ld-riscv-elf/align-comp-2.d | 14 ++
ld/testsuite/ld-riscv-elf/align-comp-2.s | 7 +
ld/testsuite/ld-riscv-elf/align-comp-3.d | 15 ++
ld/testsuite/ld-riscv-elf/align-comp-3.s | 7 +
ld/testsuite/ld-riscv-elf/align-comp-4.d | 17 ++
ld/testsuite/ld-riscv-elf/align-comp-4.s | 7 +
ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp | 4 +
.../ld-riscv-elf/pcrel-lo-addend-2a.s | 2 +-
.../ld-riscv-elf/pcrel-lo-addend-2b.s | 2 +-
29 files changed, 473 insertions(+), 147 deletions(-)
create mode 100644 ld/testsuite/ld-riscv-elf/align-comp-1.d
create mode 100644 ld/testsuite/ld-riscv-elf/align-comp-1.s
create mode 100644 ld/testsuite/ld-riscv-elf/align-comp-2.d
create mode 100644 ld/testsuite/ld-riscv-elf/align-comp-2.s
create mode 100644 ld/testsuite/ld-riscv-elf/align-comp-3.d
create mode 100644 ld/testsuite/ld-riscv-elf/align-comp-3.s
create mode 100644 ld/testsuite/ld-riscv-elf/align-comp-4.d
create mode 100644 ld/testsuite/ld-riscv-elf/align-comp-4.s
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index c0b563aec02..c8a4f451bf9 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -4418,6 +4418,7 @@ number for the SBIC, SBIS, SBI and CBI instructions */
BFD_RELOC_RISCV_SET16,
BFD_RELOC_RISCV_SET32,
BFD_RELOC_RISCV_32_PCREL,
+ BFD_RELOC_RISCV_RVC_COMP,
/* Renesas RL78 Relocations. */
BFD_RELOC_RL78_NEG8,
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 8f9f0d8a86a..aa59a12f417 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -2327,6 +2327,7 @@ riscv_elf_relocate_section (bfd *output_bfd,
case R_RISCV_COPY:
case R_RISCV_JUMP_SLOT:
case R_RISCV_RELATIVE:
+ case R_RISCV_RVC_COMP:
/* These require nothing of us at all. */
continue;
@@ -4429,6 +4430,38 @@ _bfd_riscv_relax_tls_le (bfd *abfd,
}
}
+
+/* Implement R_RISCV_RVC_COMP by compressing those insns. */
+
+static bool
+_bfd_riscv_rvc_comp (bfd *abfd, asection *sec,
+ asection *sym_sec ATTRIBUTE_UNUSED,
+ struct bfd_link_info *link_info,
+ Elf_Internal_Rela *rel,
+ bfd_vma symval ATTRIBUTE_UNUSED,
+ bfd_vma max_alignment ATTRIBUTE_UNUSED,
+ bfd_vma reserve_size ATTRIBUTE_UNUSED,
+ bool *again ATTRIBUTE_UNUSED,
+ riscv_pcgp_relocs *pcrel_relocs ATTRIBUTE_UNUSED,
+ bool undefined_weak ATTRIBUTE_UNUSED)
+{
+ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
+ /* Delete the reloc. */
+ rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE);
+ /* Only emit compressed insns on RVC targets. */
+ int rvc = elf_elfheader (abfd)->e_flags & EF_RISCV_RVC;
+ if (rvc) {
+ /* Compress the insn (using the compressed variant stored in the addend). */
+ bfd_vma c_variant = rel->r_addend;
+ bfd_putl16 (c_variant, contents + rel->r_offset);
+ /* Delete the excess bytes. */
+ return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + 2,
+ 2, link_info, NULL);
+ } else {
+ return true;
+ }
+}
+
/* Implement R_RISCV_ALIGN by deleting excess alignment NOPs.
Once we've handled an R_RISCV_ALIGN, we can't relax anything else. */
@@ -4445,48 +4478,118 @@ _bfd_riscv_relax_align (bfd *abfd, asection *sec,
bool undefined_weak ATTRIBUTE_UNUSED)
{
bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
+ int rvc = elf_elfheader (abfd)->e_flags & EF_RISCV_RVC;
bfd_vma alignment = 1, pos;
while (alignment <= rel->r_addend)
alignment *= 2;
symval -= rel->r_addend;
bfd_vma aligned_addr = ((symval - 1) & ~(alignment - 1)) + alignment;
+ /* Bytes we would need to add via nops. */
bfd_vma nop_bytes = aligned_addr - symval;
+ /* Bytes we would need to eliminate by compressing. */
+ bfd_vma comp_bytes = alignment - nop_bytes;
/* Once we've handled an R_RISCV_ALIGN, we can't relax anything else. */
sec->sec_flg0 = true;
- /* Make sure there are enough NOPs to actually achieve the alignment. */
- if (rel->r_addend < nop_bytes)
+ /* Count compressable instructions from the start to the align directive. */
+ Elf_Internal_Rela *relocs = elf_section_data (sec)->relocs;
+ bfd_vma compressable_bytes = 0;
+ for (unsigned int i = 0; rvc && i < sec->reloc_count; i++)
{
- _bfd_error_handler
- (_("%pB(%pA+%#" PRIx64 "): %" PRId64 " bytes required for alignment "
- "to %" PRId64 "-byte boundary, but only %" PRId64 " present"),
- abfd, sym_sec, (uint64_t) rel->r_offset,
- (int64_t) nop_bytes, (int64_t) alignment, (int64_t) rel->r_addend);
- bfd_set_error (bfd_error_bad_value);
- return false;
+ Elf_Internal_Rela *reloc = relocs + i;
+ if (reloc == rel)
+ break;
+ else if (ELFNN_R_TYPE (reloc->r_info) == R_RISCV_RVC_COMP)
+ compressable_bytes += 2;
}
- /* Delete the reloc. */
- rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE);
+ /* Prefer achieving alignment without introducing nops. */
+ if (rvc && compressable_bytes >= comp_bytes)
+ {
+ /* Delete the reloc. */
+ rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE);
- /* If the number of NOPs is already correct, there's nothing to do. */
- if (nop_bytes == rel->r_addend)
- return true;
+ /* Delete all nops (including nop the alignment is attached to). */
+ if (!riscv_relax_delete_bytes (abfd, sec, rel->r_offset - nop_bytes,
+ rel->r_addend + nop_bytes, link_info,
+ NULL))
+ return false;
- /* Write as many RISC-V NOPs as we need. */
- for (pos = 0; pos < (nop_bytes & -4); pos += 4)
- bfd_putl32 (RISCV_NOP, contents + rel->r_offset + pos);
+ /* Compress instructions, keeping the required amount uncompressed. */
+ bfd_vma uncompressable_bytes = (comp_bytes + compressable_bytes) % alignment;
- /* Write a final RVC NOP if need be. */
- if (nop_bytes % 4 != 0)
- bfd_putl16 (RVC_NOP, contents + rel->r_offset + pos);
+ for (unsigned int i = 0; i < sec->reloc_count; i++)
+ {
+ Elf_Internal_Rela *reloc = relocs + i;
+ if (uncompressable_bytes > 0) {
+ /* Delete the reloc so the achieved alignment stays valid even
+ after subsequent align directives. */
+ reloc->r_info = ELFNN_R_INFO (0, R_RISCV_NONE);
+ uncompressable_bytes -= 2;
+ } else if (ELFNN_R_TYPE (reloc->r_info) == R_RISCV_RVC_COMP) {
+ /* Compress the insn. */
+ _bfd_riscv_rvc_comp(abfd, sec, sym_sec, link_info, reloc, symval,
+ max_alignment, reserve_size, again,
+ pcgp_relocs, undefined_weak);
+ } else if (reloc == rel) {
+ /* Check that we retained the bytes needed for alignment. */
+ if (uncompressable_bytes != 0) {
+ return false;
+ }
+ break;
+ }
+ }
+ }
+ else
+ {
+ /* Remove compressable annotations from all insns prior to this. */
+ for (unsigned int i = 0; i < sec->reloc_count; i++)
+ {
+ Elf_Internal_Rela *reloc = relocs + i;
+ /* Don't remove annotations after this alignment directive. */
+ if (reloc == rel)
+ break;
+ else if (ELFNN_R_TYPE (reloc->r_info) == R_RISCV_RVC_COMP)
+ reloc->r_info = ELFNN_R_INFO (0, R_RISCV_NONE);
+ }
- /* Delete the excess bytes. */
- return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + nop_bytes,
+ /* Make sure there are enough NOPs to actually achieve the alignment. */
+ if (rel->r_addend < nop_bytes)
+ {
+ _bfd_error_handler
+ (_("%pB(%pA+%#" PRIx64 "): %" PRId64 " bytes required for alignment "
+ "to %" PRId64 "-byte boundary, but only %" PRId64 " present"),
+ abfd, sym_sec, (uint64_t) rel->r_offset,
+ (int64_t) nop_bytes, (int64_t) alignment, (int64_t) rel->r_addend);
+ bfd_set_error (bfd_error_bad_value);
+ return false;
+ }
+
+ /* Delete the reloc. */
+ rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE);
+
+ /* If the number of NOPs is already correct, there's nothing to do. */
+ if (nop_bytes == rel->r_addend)
+ return true;
+
+ /* Write as many RISC-V NOPs as we need. */
+ for (pos = 0; pos < (nop_bytes & -4); pos += 4)
+ bfd_putl32 (RISCV_NOP, contents + rel->r_offset + pos);
+
+ /* Write a final RVC NOP if need be. */
+ if (nop_bytes % 4 != 0)
+ bfd_putl16 (RVC_NOP, contents + rel->r_offset + pos);
+
+ /* Delete the excess nops */
+ if (!riscv_relax_delete_bytes (abfd, sec, rel->r_offset + nop_bytes,
rel->r_addend - nop_bytes, link_info,
- NULL);
+ NULL))
+ return false;
+ }
+
+ return true;
}
/* Relax PC-relative references to GP-relative references. */
@@ -4775,6 +4878,8 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
relax_func = _bfd_riscv_relax_delete;
else if (info->relax_pass == 2 && type == R_RISCV_ALIGN)
relax_func = _bfd_riscv_relax_align;
+ else if (info->relax_pass == 3 && type == R_RISCV_RVC_COMP)
+ relax_func = _bfd_riscv_rvc_comp;
else
continue;
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index cb2cc146c04..34d0d33220b 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -870,6 +870,21 @@ static reloc_howto_type howto_table[] =
0, /* src_mask */
0xffffffff, /* dst_mask */
false), /* pcrel_offset */
+
+ /* Indicates that the instruction can be compressed. */
+ HOWTO (R_RISCV_RVC_COMP, /* type */
+ 0, /* rightshift */
+ 3, /* size */
+ 0, /* bitsize */
+ false, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_RVC_COMP", /* name */
+ false, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ false), /* pcrel_offset */
};
/* A mapping from BFD reloc types to RISC-V ELF reloc types. */
@@ -931,6 +946,7 @@ static const struct elf_reloc_map riscv_reloc_map[] =
{ BFD_RELOC_RISCV_SET16, R_RISCV_SET16 },
{ BFD_RELOC_RISCV_SET32, R_RISCV_SET32 },
{ BFD_RELOC_RISCV_32_PCREL, R_RISCV_32_PCREL },
+ { BFD_RELOC_RISCV_RVC_COMP, R_RISCV_RVC_COMP },
};
/* Given a BFD reloc type, return a howto structure. */
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index bb5f6e4aedd..d0a90cedadd 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1336,14 +1336,17 @@ riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
/* Output an instruction. IP is the instruction information.
ADDRESS_EXPR is an operand of the instruction to be used with
- RELOC_TYPE. */
+ RELOC_TYPE. COMP_INSN is the compressed alternative. */
static void
append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
- bfd_reloc_code_real_type reloc_type)
+ bfd_reloc_code_real_type reloc_type, short comp_insn)
{
dwarf2_emit_insn (0);
+ if (comp_insn != 0 && reloc_type == BFD_RELOC_UNUSED)
+ reloc_type = BFD_RELOC_RISCV_RVC_COMP;
+
if (reloc_type != BFD_RELOC_UNUSED)
{
reloc_howto_type *howto;
@@ -1379,6 +1382,7 @@ append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
bfd_get_reloc_size (howto),
address_expr, false, reloc_type);
+ ip->fixp->tc_fix_data.comp_insn = comp_insn;
ip->fixp->fx_tcbit = riscv_opts.relax;
}
}
@@ -1393,7 +1397,8 @@ append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
if (reloc_type == BFD_RELOC_RISCV_HI20
|| reloc_type == BFD_RELOC_RISCV_PCREL_HI20
|| reloc_type == BFD_RELOC_RISCV_TPREL_HI20
- || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
+ || reloc_type == BFD_RELOC_RISCV_TPREL_ADD
+ || comp_insn != 0)
{
frag_wane (frag_now);
frag_new (0);
@@ -1495,7 +1500,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
va_end (args);
gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
- append_insn (&insn, ep, r);
+ append_insn (&insn, ep, r, 0);
}
/* Build an instruction created by a macro expansion. Like md_assemble but
@@ -2238,7 +2243,7 @@ riscv_is_priv_insn (insn_t insn)
static struct riscv_ip_error
riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
- bfd_reloc_code_real_type *imm_reloc, htab_t hash)
+ bfd_reloc_code_real_type *imm_reloc, htab_t hash, short *comp_insn)
{
/* The operand string defined in the riscv_opcodes. */
const char *oparg, *opargStart;
@@ -2255,6 +2260,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
error.missing_ext = NULL;
/* Indicate we are assembling instruction with CSR. */
bool insn_with_csr = false;
+ bool emit_comp = false;
/* Parse the name of the instruction. Terminate the string if whitespace
is found so that str_hash_find only sees the name part of the string. */
@@ -2268,6 +2274,9 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
insn = (struct riscv_opcode *) str_hash_find (hash, str);
+ /* Must emit compressed variants of insns with annotations. */
+ emit_comp = strncmp (str, "c", 1) == 0;
+
asargStart = asarg;
for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
{
@@ -2306,9 +2315,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
/* For .insn, insn->match and insn->mask are 0. */
if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
? ip->insn_opcode
- : insn->match) == 2
- && !riscv_opts.rvc)
- break;
+ : insn->match) == 2)
+ {
+ if (riscv_opts.rvc && comp_insn != NULL)
+ *comp_insn = ip->insn_opcode;
+
+ if (!riscv_opts.rvc || !emit_comp)
+ break;
+ else
+ *comp_insn = 0;
+ }
if (riscv_is_priv_insn (ip->insn_opcode))
explicit_priv_attr = true;
@@ -3279,6 +3295,7 @@ md_assemble (char *str)
struct riscv_cl_insn insn;
expressionS imm_expr;
bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
+ short comp_insn = 0;
/* The architecture and privileged elf attributes should be set
before assembling. */
@@ -3294,7 +3311,7 @@ md_assemble (char *str)
riscv_mapping_state (MAP_INSN, 0);
const struct riscv_ip_error error = riscv_ip (str, &insn, &imm_expr,
- &imm_reloc, op_hash);
+ &imm_reloc, op_hash, &comp_insn);
if (error.msg)
{
@@ -3309,7 +3326,7 @@ md_assemble (char *str)
if (insn.insn_mo->pinfo == INSN_MACRO)
macro (&insn, &imm_expr, &imm_reloc);
else
- append_insn (&insn, &imm_expr, imm_reloc);
+ append_insn (&insn, &imm_expr, imm_reloc, comp_insn);
}
const char *
@@ -3719,6 +3736,9 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
case BFD_RELOC_RISCV_ALIGN:
break;
+ case BFD_RELOC_RISCV_RVC_COMP:
+ fixP->fx_addnumber = fixP->tc_fix_data.comp_insn;
+ break;
default:
/* We ignore generic BFD relocations we don't know about. */
@@ -3737,6 +3757,17 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
fixP->fx_next->fx_size = 0;
}
+
+ /* Add an R_RISCV_RVC_COMP reloc if the insn is compressable. */
+ if (fixP->tc_fix_data.comp_insn != 0 && fixP->fx_r_type != BFD_RELOC_RISCV_RVC_COMP)
+ {
+ fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
+ fixP->fx_next->fx_addsy = NULL;
+ fixP->fx_next->fx_subsy = NULL;
+ fixP->fx_next->fx_done = false;
+ fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RVC_COMP;
+ fixP->fx_next->fx_size = 0;
+ }
}
/* Because the value of .cfi_remember_state may changed after relaxation,
@@ -4302,6 +4333,7 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED)
expressionS imm_expr;
bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
char save_c;
+ short comp_insn = 0;
while (!is_end_of_line[(unsigned char) *input_line_pointer])
++input_line_pointer;
@@ -4312,7 +4344,7 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED)
riscv_mapping_state (MAP_INSN, 0);
struct riscv_ip_error error = riscv_ip (str, &insn, &imm_expr,
- &imm_reloc, insn_type_hash);
+ &imm_reloc, insn_type_hash, &comp_insn);
if (error.msg)
{
char *save_in = input_line_pointer;
@@ -4331,7 +4363,7 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED)
else
{
gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
- append_insn (&insn, &imm_expr, imm_reloc);
+ append_insn (&insn, &imm_expr, imm_reloc, comp_insn);
}
*input_line_pointer = save_c;
diff --git a/gas/config/tc-riscv.h b/gas/config/tc-riscv.h
index acf8b003860..e82f3bf0d78 100644
--- a/gas/config/tc-riscv.h
+++ b/gas/config/tc-riscv.h
@@ -157,4 +157,12 @@ void riscv_elf_copy_symbol_attributes (symbolS *, symbolS *);
#define OBJ_COPY_SYMBOL_ATTRIBUTES(DEST, SRC) \
riscv_elf_copy_symbol_attributes (DEST, SRC)
+struct riscv_fix
+{
+ short comp_insn;
+};
+
+#define TC_FIX_TYPE struct riscv_fix
+#define TC_INIT_FIX_DATA(FIX) { (FIX)->tc_fix_data.comp_insn = 0; }
+
#endif /* TC_RISCV */
diff --git a/gas/testsuite/gas/riscv/c-add-addi.d b/gas/testsuite/gas/riscv/c-add-addi.d
index 14913dfd7fb..3e431221f8f 100644
--- a/gas/testsuite/gas/riscv/c-add-addi.d
+++ b/gas/testsuite/gas/riscv/c-add-addi.d
@@ -7,5 +7,7 @@
Disassembly of section .text:
0+000 <.text>:
-[ ]+0:[ ]+4605[ ]+li[ ]+a2,1
-[ ]+2:[ ]+852e[ ]+mv[ ]+a0,a1
+[ ]+0:[ ]+00100613[ ]+li[ ]+a2,1
+[ ]+0:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x4605
+[ ]+4:[ ]+00b00533[ ]+add[ ]+a0,zero,a1
+[ ]+4:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x7ad2
diff --git a/gas/testsuite/gas/riscv/c-ld.d b/gas/testsuite/gas/riscv/c-ld.d
index 29315e6b68b..1782a39786a 100644
--- a/gas/testsuite/gas/riscv/c-ld.d
+++ b/gas/testsuite/gas/riscv/c-ld.d
@@ -7,11 +7,19 @@
Disassembly of section .text:
0+000 <target>:
-[ ]+0:[ ]+6108[ ]+ld[ ]+a0,0\(a0\)
-[ ]+2:[ ]+6108[ ]+ld[ ]+a0,0\(a0\)
-[ ]+4:[ ]+e108[ ]+sd[ ]+a0,0\(a0\)
-[ ]+6:[ ]+e108[ ]+sd[ ]+a0,0\(a0\)
-[ ]+8:[ ]+6502[ ]+ld[ ]+a0,0\(sp\)
-[ ]+a:[ ]+6502[ ]+ld[ ]+a0,0\(sp\)
-[ ]+c:[ ]+e02a[ ]+sd[ ]+a0,0\(sp\)
-[ ]+e:[ ]+e02a[ ]+sd[ ]+a0,0\(sp\)
+[ ]+0:[ ]+00053503[ ]+ld[ ]+a0,0\(a0\)
+[ ]+0:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x6108
+[ ]+4:[ ]+00053503[ ]+ld[ ]+a0,0\(a0\)
+[ ]+4:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x6108
+[ ]+8:[ ]+00a53023[ ]+sd[ ]+a0,0\(a0\)
+[ ]+8:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x1ef8
+[ ]+c:[ ]+00a53023[ ]+sd[ ]+a0,0\(a0\)
+[ ]+c:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x1ef8
+[ ]+10:[ ]+00013503[ ]+ld[ ]+a0,0\(sp\)
+[ ]+10:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x6502
+[ ]+14:[ ]+00013503[ ]+ld[ ]+a0,0\(sp\)
+[ ]+14:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x6502
+[ ]+18:[ ]+00a13023[ ]+sd[ ]+a0,0\(sp\)
+[ ]+18:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x1fd6
+[ ]+1c:[ ]+00a13023[ ]+sd[ ]+a0,0\(sp\)
+[ ]+1c:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x1fd6
diff --git a/gas/testsuite/gas/riscv/c-lw.d b/gas/testsuite/gas/riscv/c-lw.d
index f3ea3b2d2db..474acd07aef 100644
--- a/gas/testsuite/gas/riscv/c-lw.d
+++ b/gas/testsuite/gas/riscv/c-lw.d
@@ -7,11 +7,19 @@
Disassembly of section .text:
0+000 <target>:
-[ ]+0:[ ]+4108[ ]+lw[ ]+a0,0\(a0\)
-[ ]+2:[ ]+4108[ ]+lw[ ]+a0,0\(a0\)
-[ ]+4:[ ]+c108[ ]+sw[ ]+a0,0\(a0\)
-[ ]+6:[ ]+c108[ ]+sw[ ]+a0,0\(a0\)
-[ ]+8:[ ]+4502[ ]+lw[ ]+a0,0\(sp\)
-[ ]+a:[ ]+4502[ ]+lw[ ]+a0,0\(sp\)
-[ ]+c:[ ]+c02a[ ]+sw[ ]+a0,0\(sp\)
-[ ]+e:[ ]+c02a[ ]+sw[ ]+a0,0\(sp\)
+[ ]+0:[ ]+00052503[ ]+lw[ ]+a0,0\(a0\)
+[ ]+0:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x4108
+[ ]+4:[ ]+00052503[ ]+lw[ ]+a0,0\(a0\)
+[ ]+4:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x4108
+[ ]+8:[ ]+00a52023[ ]+sw[ ]+a0,0\(a0\)
+[ ]+8:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x3ef8
+[ ]+c:[ ]+00a52023[ ]+sw[ ]+a0,0\(a0\)
+[ ]+c:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x3ef8
+[ ]+10:[ ]+00012503[ ]+lw[ ]+a0,0\(sp\)
+[ ]+10:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x4502
+[ ]+14:[ ]+00012503[ ]+lw[ ]+a0,0\(sp\)
+[ ]+14:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x4502
+[ ]+18:[ ]+00a12023[ ]+sw[ ]+a0,0\(sp\)
+[ ]+18:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x3fd6
+[ ]+1c:[ ]+00a12023[ ]+sw[ ]+a0,0\(sp\)
+[ ]+1c:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x3fd6
diff --git a/gas/testsuite/gas/riscv/c-zero-imm-64.d b/gas/testsuite/gas/riscv/c-zero-imm-64.d
index 9d1e490f859..e72662357c1 100644
--- a/gas/testsuite/gas/riscv/c-zero-imm-64.d
+++ b/gas/testsuite/gas/riscv/c-zero-imm-64.d
@@ -7,5 +7,6 @@
Disassembly of section .text:
0+000 <.text>:
-[ ]+0:[ ]+2801[ ]+sext.w[ ]+a6,a6
-[ ]+2:[ ]+2881[ ]+sext.w[ ]+a7,a7
+[ ]+0:[ ]+0008081b[ ]+sext.w[ ]+a6,a6
+[ ]+0:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x2801
+[ ]+4:[ ]+2881[ ]+sext.w[ ]+a7,a7
diff --git a/gas/testsuite/gas/riscv/c-zero-imm.d b/gas/testsuite/gas/riscv/c-zero-imm.d
index 1f3e4851446..3df70433723 100644
--- a/gas/testsuite/gas/riscv/c-zero-imm.d
+++ b/gas/testsuite/gas/riscv/c-zero-imm.d
@@ -7,17 +7,21 @@
Disassembly of section .text:
0+000 <.text>:
-[ ]+0:[ ]+4501[ ]+li[ ]+a0,0
-[ ]+2:[ ]+4581[ ]+li[ ]+a1,0
-[ ]+4:[ ]+8a01[ ]+andi[ ]+a2,a2,0
-[ ]+6:[ ]+8a81[ ]+andi[ ]+a3,a3,0
-[ ]+8:[ ]+0001[ ]+nop
-[ ]+a:[ ]+873a[ ]+mv[ ]+a4,a4
-[ ]+c:[ ]+0781[ ]+addi[ ]+a5,a5,0
-[ ]+e:[ ]+00051513[ ]+slli[ ]+a0,a0,0x0
-[ ]+12:[ ]+0005d593[ ]+srli[ ]+a1,a1,0x0
-[ ]+16:[ ]+40065613[ ]+srai[ ]+a2,a2,0x0
-[ ]+1a:[ ]+0682[ ]+c.slli64[ ]+a3
-[ ]+1c:[ ]+8301[ ]+c.srli64[ ]+a4
-[ ]+1e:[ ]+8781[ ]+c.srai64[ ]+a5
+[ ]+0:[ ]+00000513[ ]+li[ ]+a0,0
+[ ]+0:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x4501
+[ ]+4:[ ]+4581[ ]+li[ ]+a1,0
+[ ]+6:[ ]+00067613[ ]+andi[ ]+a2,a2,0
+[ ]+6:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x75ff
+[ ]+a:[ ]+8a81[ ]+andi[ ]+a3,a3,0
+[ ]+c:[ ]+00000013[ ]+nop
+[ ]+c:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x1
+[ ]+10:[ ]+00070713[ ]+mv[ ]+a4,a4
+[ ]+10:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x78c6
+[ ]+14:[ ]+0781[ ]+addi[ ]+a5,a5,0
+[ ]+16:[ ]+00051513[ ]+slli[ ]+a0,a0,0x0
+[ ]+1a:[ ]+0005d593[ ]+srli[ ]+a1,a1,0x0
+[ ]+1e:[ ]+40065613[ ]+srai[ ]+a2,a2,0x0
+[ ]+22:[ ]+0682[ ]+c.slli64[ ]+a3
+[ ]+24:[ ]+8301[ ]+c.srli64[ ]+a4
+[ ]+26:[ ]+8781[ ]+c.srai64[ ]+a5
#...
diff --git a/gas/testsuite/gas/riscv/ext-32.d b/gas/testsuite/gas/riscv/ext-32.d
index 918c9c8a163..0a41ecb50c3 100644
--- a/gas/testsuite/gas/riscv/ext-32.d
+++ b/gas/testsuite/gas/riscv/ext-32.d
@@ -1,6 +1,6 @@
#as: -march=rv32i
#source: ext.s
-#objdump: -d
+#objdump: -dr
.*:[ ]+file format .*
@@ -23,17 +23,26 @@ Disassembly of section .text:
[ ]+30:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
[ ]+34:[ ]+4105d593[ ]+srai[ ]+a1,a1,0x10
[ ]+38:[ ]+0ff57513[ ]+zext.b[ ]+a0,a0
-[ ]+3c:[ ]+0542[ ]+slli[ ]+a0,a0,0x10
-[ ]+3e:[ ]+8141[ ]+srli[ ]+a0,a0,0x10
-[ ]+40:[ ]+0562[ ]+slli[ ]+a0,a0,0x18
-[ ]+42:[ ]+8561[ ]+srai[ ]+a0,a0,0x18
-[ ]+44:[ ]+0542[ ]+slli[ ]+a0,a0,0x10
-[ ]+46:[ ]+8541[ ]+srai[ ]+a0,a0,0x10
-[ ]+48:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
-[ ]+4c:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
-[ ]+50:[ ]+81c1[ ]+srli[ ]+a1,a1,0x10
-[ ]+52:[ ]+01861593[ ]+slli[ ]+a1,a2,0x18
-[ ]+56:[ ]+85e1[ ]+srai[ ]+a1,a1,0x18
+[ ]+3c:[ ]+01051513[ ]+slli[ ]+a0,a0,0x10
+[ ]+3c:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x542
+[ ]+40:[ ]+01055513[ ]+srli[ ]+a0,a0,0x10
+[ ]+40:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x7ebf
+[ ]+44:[ ]+01851513[ ]+slli[ ]+a0,a0,0x18
+[ ]+44:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x562
+[ ]+48:[ ]+41855513[ ]+srai[ ]+a0,a0,0x18
+[ ]+48:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x7a9f
+[ ]+4c:[ ]+01051513[ ]+slli[ ]+a0,a0,0x10
+[ ]+4c:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x542
+[ ]+50:[ ]+41055513[ ]+srai[ ]+a0,a0,0x10
+[ ]+50:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x7abf
+[ ]+54:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
[ ]+58:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
-[ ]+5c:[ ]+85c1[ ]+srai[ ]+a1,a1,0x10
+[ ]+5c:[ ]+0105d593[ ]+srli[ ]+a1,a1,0x10
+[ ]+5c:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x7e3f
+[ ]+60:[ ]+01861593[ ]+slli[ ]+a1,a2,0x18
+[ ]+64:[ ]+4185d593[ ]+srai[ ]+a1,a1,0x18
+[ ]+64:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x7a1f
+[ ]+68:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
+[ ]+6c:[ ]+4105d593[ ]+srai[ ]+a1,a1,0x10
+[ ]+6c:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x7a3f
#...
diff --git a/gas/testsuite/gas/riscv/ext-64.d b/gas/testsuite/gas/riscv/ext-64.d
index 49d109b1db3..f0d31490cb6 100644
--- a/gas/testsuite/gas/riscv/ext-64.d
+++ b/gas/testsuite/gas/riscv/ext-64.d
@@ -1,6 +1,6 @@
#as: -march=rv64i -defsym __64_bit__=1
#source: ext.s
-#objdump: -d
+#objdump: -dr
.*:[ ]+file format .*
@@ -29,23 +29,36 @@ Disassembly of section .text:
[ ]+48:[ ]+0205d593[ ]+srli[ ]+a1,a1,0x20
[ ]+4c:[ ]+0006059b[ ]+sext.w[ ]+a1,a2
[ ]+50:[ ]+0ff57513[ ]+zext.b[ ]+a0,a0
-[ ]+54:[ ]+1542[ ]+slli[ ]+a0,a0,0x30
-[ ]+56:[ ]+9141[ ]+srli[ ]+a0,a0,0x30
-[ ]+58:[ ]+1562[ ]+slli[ ]+a0,a0,0x38
-[ ]+5a:[ ]+9561[ ]+srai[ ]+a0,a0,0x38
-[ ]+5c:[ ]+1542[ ]+slli[ ]+a0,a0,0x30
-[ ]+5e:[ ]+9541[ ]+srai[ ]+a0,a0,0x30
-[ ]+60:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
-[ ]+64:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
-[ ]+68:[ ]+91c1[ ]+srli[ ]+a1,a1,0x30
-[ ]+6a:[ ]+03861593[ ]+slli[ ]+a1,a2,0x38
-[ ]+6e:[ ]+95e1[ ]+srai[ ]+a1,a1,0x38
+[ ]+54:[ ]+03051513[ ]+slli[ ]+a0,a0,0x30
+[ ]+54:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x1542
+[ ]+58:[ ]+03055513[ ]+srli[ ]+a0,a0,0x30
+[ ]+58:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x6ebf
+[ ]+5c:[ ]+03851513[ ]+slli[ ]+a0,a0,0x38
+[ ]+5c:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x1562
+[ ]+60:[ ]+43855513[ ]+srai[ ]+a0,a0,0x38
+[ ]+60:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x6a9f
+[ ]+64:[ ]+03051513[ ]+slli[ ]+a0,a0,0x30
+[ ]+64:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x1542
+[ ]+68:[ ]+43055513[ ]+srai[ ]+a0,a0,0x30
+[ ]+68:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x6abf
+[ ]+6c:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
[ ]+70:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
-[ ]+74:[ ]+95c1[ ]+srai[ ]+a1,a1,0x30
-[ ]+76:[ ]+1502[ ]+slli[ ]+a0,a0,0x20
-[ ]+78:[ ]+9101[ ]+srli[ ]+a0,a0,0x20
-[ ]+7a:[ ]+2501[ ]+sext.w[ ]+a0,a0
-[ ]+7c:[ ]+02061593[ ]+slli[ ]+a1,a2,0x20
-[ ]+80:[ ]+9181[ ]+srli[ ]+a1,a1,0x20
-[ ]+82:[ ]+0006059b[ ]+sext.w[ ]+a1,a2
+[ ]+74:[ ]+0305d593[ ]+srli[ ]+a1,a1,0x30
+[ ]+74:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x6e3f
+[ ]+78:[ ]+03861593[ ]+slli[ ]+a1,a2,0x38
+[ ]+7c:[ ]+4385d593[ ]+srai[ ]+a1,a1,0x38
+[ ]+7c:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x6a1f
+[ ]+80:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
+[ ]+84:[ ]+4305d593[ ]+srai[ ]+a1,a1,0x30
+[ ]+84:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x6a3f
+[ ]+88:[ ]+02051513[ ]+slli[ ]+a0,a0,0x20
+[ ]+88:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x1502
+[ ]+8c:[ ]+02055513[ ]+srli[ ]+a0,a0,0x20
+[ ]+8c:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x6eff
+[ ]+90:[ ]+0005051b[ ]+sext.w[ ]+a0,a0
+[ ]+90:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x2501
+[ ]+94:[ ]+02061593[ ]+slli[ ]+a1,a2,0x20
+[ ]+98:[ ]+0205d593[ ]+srli[ ]+a1,a1,0x20
+[ ]+98:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x6e7f
+[ ]+9c:[ ]+0006059b[ ]+sext.w[ ]+a1,a2
#...
diff --git a/gas/testsuite/gas/riscv/li32.d b/gas/testsuite/gas/riscv/li32.d
index 3496384a68e..7bb350884ce 100644
--- a/gas/testsuite/gas/riscv/li32.d
+++ b/gas/testsuite/gas/riscv/li32.d
@@ -7,11 +7,16 @@
Disassembly of section .text:
0+000 <target>:
-[^:]+:[ ]+6521[ ]+lui[ ]+a0,0x8
-[^:]+:[ ]+0505[ ]+addi[ ]+a0,a0,1 # .*
-[^:]+:[ ]+6509[ ]+lui[ ]+a0,0x2
+[^:]+:[ ]+00008537[ ]+lui[ ]+a0,0x8
+[ ]+[^:]+:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x6521
+[^:]+:[ ]+00150513[ ]+addi[ ]+a0,a0,1 # .*
+[ ]+[^:]+:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x505
+[^:]+:[ ]+00002537[ ]+lui[ ]+a0,0x2
+[ ]+[^:]+:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x6509
[^:]+:[ ]+f0150513[ ]+addi[ ]+a0,a0,-255 # .*
[^:]+:[ ]+12345537[ ]+lui[ ]+a0,0x12345
-[^:]+:[ ]+0505[ ]+addi[ ]+a0,a0,1 # .*
+[^:]+:[ ]+00150513[ ]+addi[ ]+a0,a0,1 # .*
+[ ]+[^:]+:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x505
[^:]+:[ ]+f2345537[ ]+lui[ ]+a0,0xf2345
-[^:]+:[ ]+0505[ ]+addi[ ]+a0,a0,1 # .*
+[^:]+:[ ]+00150513[ ]+addi[ ]+a0,a0,1 # .*
+[ ]+[^:]+:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x505
diff --git a/gas/testsuite/gas/riscv/li64.d b/gas/testsuite/gas/riscv/li64.d
index 047985708ad..5f8d0f37e84 100644
--- a/gas/testsuite/gas/riscv/li64.d
+++ b/gas/testsuite/gas/riscv/li64.d
@@ -7,38 +7,58 @@
Disassembly of section .text:
0000000000000000 <target>:
-[^:]+:[ ]+6521[ ]+lui[ ]+a0,0x8
-[^:]+:[ ]+2505[ ]+addiw[ ]+a0,a0,1 # .*
-[^:]+:[ ]+6509[ ]+lui[ ]+a0,0x2
-[^:]+:[ ]+f015051b[ ]+addiw[ ]+a0,a0,-255 # .*
-[^:]+:[ ]+12345537[ ]+lui[ ]+a0,0x12345
-[^:]+:[ ]+2505[ ]+addiw[ ]+a0,a0,1 # .*
-[^:]+:[ ]+000f2537[ ]+lui[ ]+a0,0xf2
-[^:]+:[ ]+3455051b[ ]+addiw[ ]+a0,a0,837 # .*
-[^:]+:[ ]+0532[ ]+slli[ ]+a0,a0,0xc
-[^:]+:[ ]+0505[ ]+addi[ ]+a0,a0,1
-[^:]+:[ ]+00f12537[ ]+lui[ ]+a0,0xf12
-[^:]+:[ ]+3455051b[ ]+addiw[ ]+a0,a0,837 # .*
-[^:]+:[ ]+0532[ ]+slli[ ]+a0,a0,0xc
-[^:]+:[ ]+0505[ ]+addi[ ]+a0,a0,1
-[^:]+:[ ]+ff010537[ ]+lui[ ]+a0,0xff010
-[^:]+:[ ]+f015051b[ ]+addiw[ ]+a0,a0,-255 # .*
-[^:]+:[ ]+054e[ ]+slli[ ]+a0,a0,0x13
-[^:]+:[ ]+80150513[ ]+addi[ ]+a0,a0,-2047
-[^:]+:[ ]+0536[ ]+slli[ ]+a0,a0,0xd
-[^:]+:[ ]+f0150513[ ]+addi[ ]+a0,a0,-255
-[^:]+:[ ]+0010051b[ ]+addiw[ ]+a0,zero,1
-[^:]+:[ ]+151a[ ]+slli[ ]+a0,a0,0x26
-[^:]+:[ ]+1565[ ]+addi[ ]+a0,a0,-7
-[^:]+:[ ]+0536[ ]+slli[ ]+a0,a0,0xd
-[^:]+:[ ]+34550513[ ]+addi[ ]+a0,a0,837
-[^:]+:[ ]+0532[ ]+slli[ ]+a0,a0,0xc
-[^:]+:[ ]+0505[ ]+addi[ ]+a0,a0,1
-[^:]+:[ ]+01fc4537[ ]+lui[ ]+a0,0x1fc4
-[^:]+:[ ]+c915051b[ ]+addiw[ ]+a0,a0,-879 # .*
-[^:]+:[ ]+0536[ ]+slli[ ]+a0,a0,0xd
-[^:]+:[ ]+1565[ ]+addi[ ]+a0,a0,-7
-[^:]+:[ ]+0536[ ]+slli[ ]+a0,a0,0xd
-[^:]+:[ ]+34550513[ ]+addi[ ]+a0,a0,837
-[^:]+:[ ]+0532[ ]+slli[ ]+a0,a0,0xc
-[^:]+:[ ]+0505[ ]+addi[ ]+a0,a0,1
+[ ]+0:[ ]+00008537[ ]+lui[ ]+a0,0x8
+[ ]+0:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x6521
+[ ]+4:[ ]+0015051b[ ]+addiw[ ]+a0,a0,1 # .*
+[ ]+4:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x2505
+[ ]+8:[ ]+00002537[ ]+lui[ ]+a0,0x2
+[ ]+8:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x6509
+[ ]+c:[ ]+f015051b[ ]+addiw[ ]+a0,a0,-255 # .*
+[ ]+10:[ ]+12345537[ ]+lui[ ]+a0,0x12345
+[ ]+14:[ ]+0015051b[ ]+addiw[ ]+a0,a0,1 # .*
+[ ]+14:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x2505
+[ ]+18:[ ]+000f2537[ ]+lui[ ]+a0,0xf2
+[ ]+1c:[ ]+3455051b[ ]+addiw[ ]+a0,a0,837 # .*
+[ ]+20:[ ]+00c51513[ ]+slli[ ]+a0,a0,0xc
+[ ]+20:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x532
+[ ]+24:[ ]+00150513[ ]+addi[ ]+a0,a0,1
+[ ]+24:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x505
+[ ]+28:[ ]+00f12537[ ]+lui[ ]+a0,0xf12
+[ ]+2c:[ ]+3455051b[ ]+addiw[ ]+a0,a0,837 # .*
+[ ]+30:[ ]+00c51513[ ]+slli[ ]+a0,a0,0xc
+[ ]+30:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x532
+[ ]+34:[ ]+00150513[ ]+addi[ ]+a0,a0,1
+[ ]+34:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x505
+[ ]+38:[ ]+ff010537[ ]+lui[ ]+a0,0xff010
+[ ]+3c:[ ]+f015051b[ ]+addiw[ ]+a0,a0,-255 # .*
+[ ]+40:[ ]+01351513[ ]+slli[ ]+a0,a0,0x13
+[ ]+40:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x54e
+[ ]+44:[ ]+80150513[ ]+addi[ ]+a0,a0,-2047
+[ ]+48:[ ]+00d51513[ ]+slli[ ]+a0,a0,0xd
+[ ]+48:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x536
+[ ]+4c:[ ]+f0150513[ ]+addi[ ]+a0,a0,-255
+[ ]+50:[ ]+0010051b[ ]+addiw[ ]+a0,zero,1
+[ ]+54:[ ]+02651513[ ]+slli[ ]+a0,a0,0x26
+[ ]+54:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x151a
+[ ]+58:[ ]+ff950513[ ]+addi[ ]+a0,a0,-7
+[ ]+58:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x1565
+[ ]+5c:[ ]+00d51513[ ]+slli[ ]+a0,a0,0xd
+[ ]+5c:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x536
+[ ]+60:[ ]+34550513[ ]+addi[ ]+a0,a0,837
+[ ]+64:[ ]+00c51513[ ]+slli[ ]+a0,a0,0xc
+[ ]+64:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x532
+[ ]+68:[ ]+00150513[ ]+addi[ ]+a0,a0,1
+[ ]+68:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x505
+[ ]+6c:[ ]+01fc4537[ ]+lui[ ]+a0,0x1fc4
+[ ]+70:[ ]+c915051b[ ]+addiw[ ]+a0,a0,-879 # .*
+[ ]+74:[ ]+00d51513[ ]+slli[ ]+a0,a0,0xd
+[ ]+74:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x536
+[ ]+78:[ ]+ff950513[ ]+addi[ ]+a0,a0,-7
+[ ]+78:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x1565
+[ ]+7c:[ ]+00d51513[ ]+slli[ ]+a0,a0,0xd
+[ ]+7c:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x536
+[ ]+80:[ ]+34550513[ ]+addi[ ]+a0,a0,837
+[ ]+84:[ ]+00c51513[ ]+slli[ ]+a0,a0,0xc
+[ ]+84:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x532
+[ ]+88:[ ]+00150513[ ]+addi[ ]+a0,a0,1
+[ ]+88:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x505
diff --git a/gas/testsuite/gas/riscv/no-relax-align-2.d b/gas/testsuite/gas/riscv/no-relax-align-2.d
index 19edf137ba8..833af805259 100644
--- a/gas/testsuite/gas/riscv/no-relax-align-2.d
+++ b/gas/testsuite/gas/riscv/no-relax-align-2.d
@@ -13,8 +13,8 @@ Disassembly of section .text:
[ ]+4:[ ]+00000013[ ]+nop
[ ]+8:[ ]+00000013[ ]+nop
[ ]+c:[ ]+00000013[ ]+nop
-[ ]+10:[ ]+0001[ ]+nop
-[ ]+12:[ ]+0001[ ]+nop
+[ ]+10:[ ]+00000013[ ]+nop
+[ ]+10:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\+0x1
[ ]+14:[ ]+00000013[ ]+nop
[ ]+18:[ ]+00000013[ ]+nop
[ ]+1c:[ ]+00000013[ ]+nop
diff --git a/gas/testsuite/gas/riscv/option-arch-01a.d b/gas/testsuite/gas/riscv/option-arch-01a.d
index aed4ca8e4d9..9b312a4b6fe 100644
--- a/gas/testsuite/gas/riscv/option-arch-01a.d
+++ b/gas/testsuite/gas/riscv/option-arch-01a.d
@@ -1,6 +1,6 @@
#as: -misa-spec=2.2
#source: option-arch-01.s
-#objdump: -d
+#objdump: -dr
.*:[ ]+file format .*
@@ -8,7 +8,8 @@
Disassembly of section .text:
0+000 <.text>:
-[ ]+[0-9a-f]+:[ ]+952e[ ]+add[ ]+a0,a0,a1
+[ ]+[0-9a-f]+:[ ]+00b50533[ ]+add[ ]+a0,a0,a1
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RVC_COMP[ ]+\*ABS\*\-0x6ad2
[ ]+[0-9a-f]+:[ ]+00b50533[ ]+add[ ]+a0,a0,a1
[ ]+[0-9a-f]+:[ ]+00302573[ ]+csrr[ ]+a0,fcsr
#...
diff --git a/include/elf/riscv.h b/include/elf/riscv.h
index d0acf6886d8..7005c0d33b2 100644
--- a/include/elf/riscv.h
+++ b/include/elf/riscv.h
@@ -89,6 +89,7 @@ START_RELOC_NUMBERS (elf_riscv_reloc_type)
RELOC_NUMBER (R_RISCV_SET32, 56)
RELOC_NUMBER (R_RISCV_32_PCREL, 57)
RELOC_NUMBER (R_RISCV_IRELATIVE, 58)
+ RELOC_NUMBER (R_RISCV_RVC_COMP, 59)
END_RELOC_NUMBERS (R_RISCV_max)
/* Processor specific flags for the ELF header e_flags field. */
diff --git a/ld/emultempl/riscvelf.em b/ld/emultempl/riscvelf.em
index 645a807f239..d45ee71e8e7 100644
--- a/ld/emultempl/riscvelf.em
+++ b/ld/emultempl/riscvelf.em
@@ -42,7 +42,7 @@ riscv_elf_before_allocation (void)
ENABLE_RELAXATION;
}
- link_info.relax_pass = 3;
+ link_info.relax_pass = 4;
}
static void
diff --git a/ld/testsuite/ld-riscv-elf/align-comp-1.d b/ld/testsuite/ld-riscv-elf/align-comp-1.d
new file mode 100644
index 00000000000..48a78dda67a
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/align-comp-1.d
@@ -0,0 +1,14 @@
+#source: align-comp-1.s
+#as:
+#ld:
+#objdump: -d
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+.* <_start>:
+.*: 0001 nop
+.*: 8082 ret
+#pass
\ No newline at end of file
diff --git a/ld/testsuite/ld-riscv-elf/align-comp-1.s b/ld/testsuite/ld-riscv-elf/align-comp-1.s
new file mode 100644
index 00000000000..ccda06b98e6
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/align-comp-1.s
@@ -0,0 +1,7 @@
+ .attribute arch, "rv64ic"
+ .text
+ .globl _start
+_start:
+ nop
+ ret
+ .balign 2
diff --git a/ld/testsuite/ld-riscv-elf/align-comp-2.d b/ld/testsuite/ld-riscv-elf/align-comp-2.d
new file mode 100644
index 00000000000..d8c44336df4
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/align-comp-2.d
@@ -0,0 +1,14 @@
+#source: align-comp-2.s
+#as:
+#ld:
+#objdump: -d
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+.* <_start>:
+.*: 0001 nop
+.*: 8082 ret
+#pass
\ No newline at end of file
diff --git a/ld/testsuite/ld-riscv-elf/align-comp-2.s b/ld/testsuite/ld-riscv-elf/align-comp-2.s
new file mode 100644
index 00000000000..e9ac4938298
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/align-comp-2.s
@@ -0,0 +1,7 @@
+ .attribute arch, "rv64ic"
+ .text
+ .globl _start
+_start:
+ nop
+ ret
+ .balign 4
diff --git a/ld/testsuite/ld-riscv-elf/align-comp-3.d b/ld/testsuite/ld-riscv-elf/align-comp-3.d
new file mode 100644
index 00000000000..f640cd60b2b
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/align-comp-3.d
@@ -0,0 +1,15 @@
+#source: align-comp-3.s
+#as:
+#ld:
+#objdump: -d
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+.* <_start>:
+.*: 00000013 nop
+.*: 00008067 ret
+.*\.\.\.
+#pass
\ No newline at end of file
diff --git a/ld/testsuite/ld-riscv-elf/align-comp-3.s b/ld/testsuite/ld-riscv-elf/align-comp-3.s
new file mode 100644
index 00000000000..aff868439b5
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/align-comp-3.s
@@ -0,0 +1,7 @@
+ .attribute arch, "rv64ic"
+ .text
+ .globl _start
+_start:
+ nop
+ ret
+ .balign 8
diff --git a/ld/testsuite/ld-riscv-elf/align-comp-4.d b/ld/testsuite/ld-riscv-elf/align-comp-4.d
new file mode 100644
index 00000000000..515e036c449
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/align-comp-4.d
@@ -0,0 +1,17 @@
+#source: align-comp-4.s
+#as:
+#ld:
+#objdump: -d
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+.* <_start>:
+.*: 00000013 nop
+.*: 00008067 ret
+.*: 00000013 nop
+.*: 00000013 nop
+.*\.\.\.
+#pass
\ No newline at end of file
diff --git a/ld/testsuite/ld-riscv-elf/align-comp-4.s b/ld/testsuite/ld-riscv-elf/align-comp-4.s
new file mode 100644
index 00000000000..bc959ceeb08
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/align-comp-4.s
@@ -0,0 +1,7 @@
+ .attribute arch, "rv64ic"
+ .text
+ .globl _start
+_start:
+ nop
+ ret
+ .balign 16
diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index 272424b33e3..ff467846dba 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -119,6 +119,10 @@ proc run_relax_twice_test {} {
}
if [istarget "riscv*-*-*"] {
+ run_dump_test "align-comp-1"
+ run_dump_test "align-comp-2"
+ run_dump_test "align-comp-3"
+ run_dump_test "align-comp-4"
run_dump_test "align-small-region"
run_dump_test "call-relax"
run_dump_test "pcgp-relax-01"
diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.s b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.s
index 1e367741d54..c9db8c5b531 100644
--- a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.s
+++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.s
@@ -10,7 +10,7 @@ _start:
.globl ll
.data
.align 3
- .zero 2024
+ .zero 2016
ll:
.word 0
.word 0
diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2b.s b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2b.s
index 9fd063f93e5..4fc41c4f731 100644
--- a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2b.s
+++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2b.s
@@ -10,7 +10,7 @@ _start:
.globl ll
.data
.align 3
- .zero 2024
+ .zero 2016
ll:
.word 0
.word 0
--
2.25.1
next reply other threads:[~2022-03-25 23:16 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-25 23:15 Patrick O'Neill [this message]
2022-03-28 7:54 ` Jan Beulich
2022-03-28 16:08 ` Patrick O'Neill
2022-03-28 22:19 ` Patrick O'Neill
2022-03-29 0:17 ` Palmer Dabbelt
2022-03-29 0:45 ` Patrick O'Neill
2022-03-29 6:11 ` Andrew Waterman
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