From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by sourceware.org (Postfix) with ESMTPS id 407F53857372 for ; Thu, 12 May 2022 07:32:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 407F53857372 Received: by mail-lf1-x12c.google.com with SMTP id t25so7488987lfg.7 for ; Thu, 12 May 2022 00:32:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3mhBuJdK6Fe0vHbNReeFt7W2ih/JHOM5+s6Hn/fNcAE=; b=2IXBqoi3g+CJTE/O9oJBSl1yESV1sF0SwsqqRtiXRpjMhpfdO9xcceF4Shcy1YoZmO eTVG3gh6riKgdIokpMf1BtuEW/t3qsWhxhKxaCtDCUD3NouK+44553nSpGGA6sXz39cU mNYnZJo9nKb9yiYzzh4ghlVUr2/fHApnXjVuOamXfxRjWCgzoOzGIC4Vhz1uyzwCQ+Ls v+k+RWPgz+AekH+v6H8wvmdlghPmkc7Rq2kXfInnJPLYq9oSECpGUWtvEnG4kiY4Swt+ 1XPM54RsJ5xOK3zocecH4tgTgurH08q8u8VGFSLe/N+FtyEf9BLWn55wkjeQpIgBKK5O AuEA== X-Gm-Message-State: AOAM532kshlbCXBp5KfE1vy/7xvLbfGnkv8o7KKsnPdpXJ5Vv8GApnyQ ediw1hnKkrG/PXeSuov0VzBcGr9Ans9C1A== X-Google-Smtp-Source: ABdhPJwEACMrJIKcdsmvq22DQQ1I5H78zo5wFGhqoCIs1trIMKYFZvTSkYT++xhxpjPBk/f5TamlEw== X-Received: by 2002:a05:6512:3b99:b0:473:a2da:e303 with SMTP id g25-20020a0565123b9900b00473a2dae303mr23578671lfv.151.1652340734932; Thu, 12 May 2022 00:32:14 -0700 (PDT) Received: from localhost.localdomain (broadband-188-32-220-29.ip.moscow.rt.ru. [188.32.220.29]) by smtp.gmail.com with ESMTPSA id m14-20020a19434e000000b0047255d21192sm649413lfj.193.2022.05.12.00.32.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 00:32:14 -0700 (PDT) Sender: Dmitry Selyutin From: Dmitry Selyutin To: binutils@sourceware.org Subject: [PATCH v2 1/2] ppc: extend opindex to 16 bits Date: Thu, 12 May 2022 10:32:11 +0300 Message-Id: <20220512073212.64309-1-ghostmansd@gmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 May 2022 07:32:19 -0000 With the upcoming SVP64 extension[0] to PowerPC architecture, it became evident that PowerPC operand indices no longer fit 8 bits. This patch switches the underlying type to uint16_t, also introducing a special typedef so that any future extension goes even smoother. [0] https://libre-soc.org --- gas/config/tc-ppc.c | 12 ++++++------ include/opcode/ppc.h | 5 ++++- opcodes/ppc-dis.c | 12 ++++++------ 3 files changed, 16 insertions(+), 13 deletions(-) diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c index 72128af501..9b29b6e15e 100644 --- a/gas/config/tc-ppc.c +++ b/gas/config/tc-ppc.c @@ -1553,7 +1553,7 @@ ppc_target_format (void) static bool insn_validate (const struct powerpc_opcode *op) { - const unsigned char *o; + const ppc_opindex_t *o; uint64_t omask = op->mask; /* The mask had better not trim off opcode bits. */ @@ -1634,8 +1634,8 @@ ppc_setup_opcodes (void) unsigned int i; /* An index into powerpc_operands is stored in struct fix - fx_pcrel_adjust which is 8 bits wide. */ - gas_assert (num_powerpc_operands < 256); + fx_pcrel_adjust which is a 16-bit signed integer. */ + gas_assert (num_powerpc_operands < PPC_OPINDEX_MAX); /* Check operand masks. Code here and in the disassembler assumes all the 1's in the mask are contiguous. */ @@ -3251,7 +3251,7 @@ md_assemble (char *str) char *s; const struct powerpc_opcode *opcode; uint64_t insn; - const unsigned char *opindex_ptr; + const ppc_opindex_t *opindex_ptr; int need_paren; int next_opindex; struct ppc_fixup fixups[MAX_INSN_FIXUPS]; @@ -3348,7 +3348,7 @@ md_assemble (char *str) { if (num_optional_operands == 0) { - const unsigned char *optr; + const ppc_opindex_t *optr; int total = 0; int provided = 0; int omitted; @@ -7011,7 +7011,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg) if (fixP->fx_pcrel_adjust != 0) { /* This is a fixup on an instruction. */ - int opindex = fixP->fx_pcrel_adjust & 0xff; + ppc_opindex_t opindex = (ppc_opindex_t)fixP->fx_pcrel_adjust; operand = &powerpc_operands[opindex]; #ifdef OBJ_XCOFF diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index a9c2529831..e4af2a9089 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -29,6 +29,9 @@ extern "C" { #endif typedef uint64_t ppc_cpu_t; +typedef uint16_t ppc_opindex_t; + +#define PPC_OPINDEX_MAX INT16_MAX /* The opcode table is an array of struct powerpc_opcode. */ @@ -60,7 +63,7 @@ struct powerpc_opcode /* An array of operand codes. Each code is an index into the operand table. They appear in the order which the operands must appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; + ppc_opindex_t operands[8]; }; /* The table itself is sorted by major opcode number, and is otherwise diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index 38ddeca262..45e8faeef5 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -546,7 +546,7 @@ operand_value_powerpc (const struct powerpc_operand *operand, /* Determine whether the optional operand(s) should be printed. */ static bool -skip_optional_operands (const unsigned char *opindex, +skip_optional_operands (const ppc_opindex_t *opindex, uint64_t insn, ppc_cpu_t dialect, bool *is_pcrel) { const struct powerpc_operand *operand; @@ -592,7 +592,7 @@ lookup_powerpc (uint64_t insn, ppc_cpu_t dialect) opcode < opcode_end; ++opcode) { - const unsigned char *opindex; + const ppc_opindex_t *opindex; const struct powerpc_operand *operand; int invalid; @@ -637,7 +637,7 @@ lookup_prefix (uint64_t insn, ppc_cpu_t dialect) opcode < opcode_end; ++opcode) { - const unsigned char *opindex; + const ppc_opindex_t *opindex; const struct powerpc_operand *operand; int invalid; @@ -691,7 +691,7 @@ lookup_vle (uint64_t insn, ppc_cpu_t dialect) uint64_t table_mask = opcode->mask; bool table_op_is_short = PPC_OP_SE_VLE(table_mask); uint64_t insn2; - const unsigned char *opindex; + const ppc_opindex_t *opindex; const struct powerpc_operand *operand; int invalid; @@ -746,7 +746,7 @@ lookup_spe2 (uint64_t insn, ppc_cpu_t dialect) uint64_t table_opcd = opcode->opcode; uint64_t table_mask = opcode->mask; uint64_t insn2; - const unsigned char *opindex; + const ppc_opindex_t *opindex; const struct powerpc_operand *operand; int invalid; @@ -925,7 +925,7 @@ print_insn_powerpc (bfd_vma memaddr, if (opcode != NULL) { - const unsigned char *opindex; + const ppc_opindex_t *opindex; const struct powerpc_operand *operand; enum { need_comma = 0, -- 2.36.0