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[188.32.220.156]) by smtp.gmail.com with ESMTPSA id a8-20020ac25208000000b0047f74ee6a1fsm9737lfl.63.2022.06.23.12.37.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 12:37:50 -0700 (PDT) Sender: Dmitry Selyutin From: Dmitry Selyutin To: binutils@sourceware.org Cc: Alan Modra , Luke Kenneth Casson Leighton , Dmitry Selyutin Subject: [PATCH v3 1/6] ppc/svp64: support LibreSOC architecture Date: Thu, 23 Jun 2022 22:37:29 +0300 Message-Id: <20220623193734.1245650-2-ghostmansd@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220623193734.1245650-1-ghostmansd@gmail.com> References: <20220621115115.1068453-1-ghostmansd@gmail.com> <20220623193734.1245650-1-ghostmansd@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Jun 2022 19:37:54 -0000 This patch adds support for LibreSOC machine and SVP64 extension flag for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit Prefixed instruction format implementing SV. Funded by NLnet through EU Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly submitted via the OpenPOWER Foundation ISA Working Group via the newly-created External RFC Process. For more details, visit https://libre-soc.org. --- gas/config/tc-ppc.c | 2 ++ include/opcode/ppc.h | 3 +++ opcodes/ppc-dis.c | 5 +++++ opcodes/ppc-opc.c | 1 + 4 files changed, 11 insertions(+) diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c index 4d789fd16a..76bdfb2e35 100644 --- a/gas/config/tc-ppc.c +++ b/gas/config/tc-ppc.c @@ -1384,6 +1384,8 @@ PowerPC options:\n")); fprintf (stream, _("\ -mpower10, -mpwr10 generate code for Power10 architecture\n")); fprintf (stream, _("\ +-mlibresoc generate code for Libre-SOC architecture\n")); + fprintf (stream, _("\ -mcell generate code for Cell Broadband Engine architecture\n")); fprintf (stream, _("\ -mcom generate code for Power/PowerPC common instructions\n")); diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index 7bc6ee216e..d5752a42e6 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -237,6 +237,9 @@ extern const unsigned int spe2_num_opcodes; /* Opcode is only supported by power10 architecture. */ #define PPC_OPCODE_POWER10 0x400000000000ull +/* Opcode is only supported by SVP64 extensions (LibreSOC architecture). */ +#define PPC_OPCODE_SVP64 0x800000000000ull + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index 45e8faeef5..f61e6518f1 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -200,6 +200,11 @@ struct ppc_mopt ppc_opts[] = { | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), 0 }, + { "libresoc", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 + | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 + | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 + | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64), + 0 }, { "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index f5bd6dac50..fe2fcaeb1d 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4826,6 +4826,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) #define PPCHTM PPC_OPCODE_POWER8 #define E200Z4 PPC_OPCODE_E200Z4 #define PPCLSP PPC_OPCODE_LSP +#define SVP64 PPC_OPCODE_SVP64 /* Used to mark extended mnemonic in deprecated field so that -Mraw won't use this variant in disassembly. */ #define EXT PPC_OPCODE_RAW -- 2.36.1