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[188.32.220.156]) by smtp.gmail.com with ESMTPSA id d17-20020ac25ed1000000b0047f666011e4sm20483lfq.26.2022.06.23.13.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 13:08:49 -0700 (PDT) Sender: Dmitry Selyutin From: Dmitry Selyutin To: binutils@sourceware.org Cc: Alan Modra , Luke Kenneth Casson Leighton , Dmitry Selyutin Subject: [PATCH v4 5/6] ppc/svp64: support svshape instruction Date: Thu, 23 Jun 2022 23:08:37 +0300 Message-Id: <20220623200838.1247734-6-ghostmansd@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220623200838.1247734-1-ghostmansd@gmail.com> References: <20220623193734.1245650-1-ghostmansd@gmail.com> <20220623200838.1247734-1-ghostmansd@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Jun 2022 20:08:59 -0000 https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/remap/ https://libre-soc.org/openpower/isa/simplev/ --- gas/testsuite/gas/ppc/ppc.exp | 1 + gas/testsuite/gas/ppc/svshape.d | 13 +++++++++++++ gas/testsuite/gas/ppc/svshape.s | 5 +++++ opcodes/ppc-opc.c | 22 ++++++++++++++++++++++ 4 files changed, 41 insertions(+) create mode 100644 gas/testsuite/gas/ppc/svshape.d create mode 100644 gas/testsuite/gas/ppc/svshape.s diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index d4d06d587e..04082439bb 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -156,3 +156,4 @@ run_dump_test "raw" run_dump_test "setvl" run_dump_test "svstep" +run_dump_test "svshape" diff --git a/gas/testsuite/gas/ppc/svshape.d b/gas/testsuite/gas/ppc/svshape.d new file mode 100644 index 0000000000..8244741ed3 --- /dev/null +++ b/gas/testsuite/gas/ppc/svshape.d @@ -0,0 +1,13 @@ +#as: -mlibresoc +#objdump: -dr -Mlibresoc + +.*: file format .* + + +Disassembly of section \.text: +0+ <\.text>: +.*: (19 00 e0 5b|5b e0 00 19) svshape 32,1,1,0,0 +.*: (19 00 1f 58|58 1f 00 19) svshape 1,32,1,0,0 +.*: (19 f8 00 58|58 00 f8 19) svshape 1,1,32,0,0 +.*: (99 07 00 58|58 00 07 99) svshape 1,1,1,15,0 +.*: (59 00 00 58|58 00 00 59) svshape 1,1,1,0,1 diff --git a/gas/testsuite/gas/ppc/svshape.s b/gas/testsuite/gas/ppc/svshape.s new file mode 100644 index 0000000000..c83373ba37 --- /dev/null +++ b/gas/testsuite/gas/ppc/svshape.s @@ -0,0 +1,5 @@ +svshape 32,1,1,0,0 +svshape 1,32,1,0,0 +svshape 1,1,32,0,0 +svshape 1,1,1,15,0 +svshape 1,1,1,0,1 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 60a038aa40..fe42c23eab 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -3838,6 +3838,21 @@ const struct powerpc_operand powerpc_operands[] = #define ms vs + 1 { 0x1, 8, NULL, NULL, 0 }, + +#define SVLcr ms + 1 + { 0x1, 5, NULL, NULL, 0 }, + +#define SVxd SVLcr + 1 + { 0x1f, 21, NULL, NULL, PPC_OPERAND_NONZERO }, + +#define SVyd SVxd + 1 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_NONZERO }, + +#define SVzd SVyd + 1 + { 0x1f, 11, NULL, NULL, PPC_OPERAND_NONZERO }, + +#define SVRMf SVzd + 1 + { 0xf, 7, NULL, NULL, 0 }, }; const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) @@ -4714,6 +4729,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) | (((uint64_t)(rc)) & 1)) #define SVL_MASK SVL (0x3f, 0x1f, 1) +/* An SVM form instruction. */ +#define SVM(op, xop) \ + (OP (op) \ + | (((uint64_t)(xop)) & 0x3f)) +#define SVM_MASK SVM (0x3f, 0x3f) + /* The BO encodings used in extended conditional branch mnemonics. */ #define BODNZF (0x0) #define BODNZFP (0x1) @@ -6785,6 +6806,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"svstep", SVL(22,19,0), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}}, {"svstep.", SVL(22,19,1), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}}, +{"svshape", SVM(22,25), SVM_MASK, SVP64, PPCVLE, {SVxd, SVyd, SVzd, SVRMf, vf}}, {"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}}, {"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}}, -- 2.36.1