From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by sourceware.org (Postfix) with ESMTPS id 40B9E3858297 for ; Sun, 26 Jun 2022 19:00:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 40B9E3858297 Received: by mail-lf1-x12c.google.com with SMTP id j21so13140920lfe.1 for ; Sun, 26 Jun 2022 12:00:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=a2JIEi40abZKD+KLjbF0eyiKxtQQbtHUycpH1d7EYxc=; b=iYQkDrMKh1bAHB5vzcZ7RuXyva8bVUpqGktCj1L548MKoV4RLU6SUU5OYlAmqp5rWa 7kIzPLXrCK7tlEXY2OfDQvc5IvAerBsg6/YZA7ptO0UNbotShRNpqdlTF5vB+Grefjl7 5bL8vcIxG3P1t7dkdzN+yrpNmbGRGp47jg7tblkwaGFzJAwE0U7lp4vI8V7TVZ+ouX2E rBXyXX+KSAvdfwnFcZRwDaV5rXeImb52N66mOJSPcCaL5xjxLQx3LFA/P+28bp1pnAKs TqliTJQVuAbBG06IieX9g+sBtC/wu8ySERXGeL4xFdxXMlTp8WWRM+BMv7sufoSJQvQh lPmw== X-Gm-Message-State: AJIora+nnczQOB68CSEl1fmxJ8S3/yIe4nakm9OE+0t5F0qlWQL/A0pP IVh9Mfs7QIgybfMZgEUJ3fn9D8AUELw= X-Google-Smtp-Source: AGRyM1vzwFGvw+o9YF6MmroCMKKaOhd/axom5sF4Gt9orrNARqDGONsVEE0R+2in0azD20gaB3Sy3Q== X-Received: by 2002:a05:6512:b9b:b0:47f:6aae:ecc5 with SMTP id b27-20020a0565120b9b00b0047f6aaeecc5mr6010931lfv.412.1656270032725; Sun, 26 Jun 2022 12:00:32 -0700 (PDT) Received: from localhost.localdomain (broadband-188-32-220-156.ip.moscow.rt.ru. [188.32.220.156]) by smtp.gmail.com with ESMTPSA id g1-20020a0565123b8100b0047255d21179sm1453952lfv.168.2022.06.26.12.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Jun 2022 12:00:32 -0700 (PDT) Sender: Dmitry Selyutin From: Dmitry Selyutin To: binutils@sourceware.org Cc: Alan Modra , Luke Leighton , Jan Beulich , Nick Alcock , Richard Earnshaw , Andreas Schwab , Dmitry Selyutin Subject: [PATCH v5 6/7] ppc/svp64: support svremap instruction Date: Sun, 26 Jun 2022 22:00:04 +0300 Message-Id: <20220626190005.7727-7-ghostmansd@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220626190005.7727-1-ghostmansd@gmail.com> References: <20220623200838.1247734-1-ghostmansd@gmail.com> <20220626190005.7727-1-ghostmansd@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 26 Jun 2022 19:00:36 -0000 https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/remap/#svremap https://libre-soc.org/openpower/isa/simplev/ --- gas/testsuite/gas/ppc/ppc.exp | 1 + gas/testsuite/gas/ppc/svremap.d | 16 ++++++++++++++++ gas/testsuite/gas/ppc/svremap.s | 8 ++++++++ opcodes/ppc-opc.c | 20 ++++++++++++++++++++ 4 files changed, 45 insertions(+) create mode 100644 gas/testsuite/gas/ppc/svremap.d create mode 100644 gas/testsuite/gas/ppc/svremap.s diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index 04082439bb..a182cc81d7 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -157,3 +157,4 @@ run_dump_test "raw" run_dump_test "setvl" run_dump_test "svstep" run_dump_test "svshape" +run_dump_test "svremap" diff --git a/gas/testsuite/gas/ppc/svremap.d b/gas/testsuite/gas/ppc/svremap.d new file mode 100644 index 0000000000..18646ec37d --- /dev/null +++ b/gas/testsuite/gas/ppc/svremap.d @@ -0,0 +1,16 @@ +#as: -mlibresoc +#objdump: -dr -Mlibresoc + +.*: file format .* + + +Disassembly of section \.text: +0+ <\.text>: +.*: (39 00 00 58|58 00 00 39) svremap 0,0,0,0,0,0,0 +.*: (39 00 e0 5b|5b e0 00 39) svremap 31,0,0,0,0,0,0 +.*: (39 00 18 58|58 18 00 39) svremap 0,3,0,0,0,0,0 +.*: (39 00 06 58|58 06 00 39) svremap 0,0,3,0,0,0,0 +.*: (39 80 01 58|58 01 80 39) svremap 0,0,0,3,0,0,0 +.*: (39 60 00 58|58 00 60 39) svremap 0,0,0,0,3,0,0 +.*: (39 18 00 58|58 00 18 39) svremap 0,0,0,0,0,3,0 +.*: (39 04 18 58|58 18 04 39) svremap 0,3,0,0,0,0,1 diff --git a/gas/testsuite/gas/ppc/svremap.s b/gas/testsuite/gas/ppc/svremap.s new file mode 100644 index 0000000000..860040afc5 --- /dev/null +++ b/gas/testsuite/gas/ppc/svremap.s @@ -0,0 +1,8 @@ +svremap 0,0,0,0,0,0,0 +svremap 31,0,0,0,0,0,0 +svremap 0,3,0,0,0,0,0 +svremap 0,0,3,0,0,0,0 +svremap 0,0,0,3,0,0,0 +svremap 0,0,0,0,3,0,0 +svremap 0,0,0,0,0,3,0 +svremap 0,3,0,0,0,0,1 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index f95bbf9402..8e56f88a6c 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -2850,6 +2850,7 @@ const struct powerpc_operand powerpc_operands[] = /* The RM field in an X form instruction. */ #define RM BOP + 1 #define DD RM +#define mo1 RM { 0x3, 11, NULL, NULL, 0 }, #define BH RM + 1 @@ -3508,6 +3509,7 @@ const struct powerpc_operand powerpc_operands[] = /* The TO field in a D or X form instruction. */ #define TO TBR + 1 #define DUI TO +#define SVme TO #define TO_MASK (0x1f << 21) { 0x1f, 21, NULL, NULL, 0 }, @@ -3621,6 +3623,8 @@ const struct powerpc_operand powerpc_operands[] = #define PSWM WS + 1 /* The BO16 field in a BD8 form instruction. */ #define BO16 PSWM + /* The pst field in a SVRM form instruction. */ +#define pst PSWM { 0x1, 10, 0, 0, 0 }, /* IDX bits for quantization in the pair singles instructions. */ @@ -3658,6 +3662,7 @@ const struct powerpc_operand powerpc_operands[] = { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL }, #define SP PRS + 1 +#define mi0 SP { 0x3, 19, NULL, NULL, 0 }, #define S SP + 1 @@ -3825,6 +3830,7 @@ const struct powerpc_operand powerpc_operands[] = { 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 }, #define HH DDD + 1 +#define mo0 HH { 0x3, 13, NULL, NULL, 0 }, #define SVi HH + 1 @@ -3853,6 +3859,12 @@ const struct powerpc_operand powerpc_operands[] = #define SVrm SVzd + 1 { 0xf, 7, NULL, NULL, 0 }, + +#define mi1 SVrm + 1 + { 0x3, 17, NULL, NULL, 0 }, + +#define mi2 mi1 + 1 + { 0x3, 15, NULL, NULL, 0 }, }; const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) @@ -4735,6 +4747,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) | (((uint64_t)(xop)) & 0x3f)) #define SVM_MASK SVM (0x3f, 0x3f) +/* An SVRM form instruction. */ +#define SVRM(op, xop) \ + (OP (op) \ + | (((uint64_t)(xop)) & 0x3f)) +#define SVRM_MASK SVRM (0x3f, 0x3f) + /* The BO encodings used in extended conditional branch mnemonics. */ #define BODNZF (0x0) #define BODNZFP (0x1) @@ -6812,6 +6830,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}}, {"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}}, +{"svremap", SVRM(22,57), SVRM_MASK, SVP64, PPCVLE, {SVme, mi0, mi1, mi2, mo0, mo1, pst}}, + {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}}, {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, -- 2.36.1