From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 0AE18385734B for ; Mon, 27 Jun 2022 02:03:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0AE18385734B Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 030F4300089; Mon, 27 Jun 2022 02:03:56 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI , Weiwei Li , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 0/8] RISC-V: Combined floating point enhancements Date: Mon, 27 Jun 2022 11:03:40 +0900 Message-Id: <20220627020348.11920-1-research_trasio@irq.a4lg.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Jun 2022 02:04:01 -0000 Before combining patchsets: (Zfh/Zfhmin v2) (Zfinx v2) Combined v1: Combined CURRENT (GitHub): [Combined Enhancements / Fixes] 1. Zfh/Zhinx refactoring / new Zfhmin/Zhinxmin support 2. Zfinx fixes / test enhancements They are supposed to be separate but involves similar/same locations that need to be modified. To ease testing and integration to upstream, I decided to merge those fixes in a single patchset. Of course, I can split it if requested. Also in general, I squashed some of fixes/enhancements (spanned in multiple patches) for simplicity. As a result, it halved the number of patches. Zfh/Zfhmin: 5 -> 3 Zfinx/Zdinx/Zqinx: 11 -> 5 Note that, this is a long-term fix to Zfinx/Zfhmin/Zhinxmin implementation. As a result, this is incompatible with my quicker patchset: ... which I consider quicker one a backup plan when this patchset will not make it into the GNU Binutils 2.39. [Changed: v1 -> v2] 1. i18n enablement (wrap some strings with the _() gettext macro) 2. Removed original PATCH 01 (as it was merged independently) [Details of Changes (mostly duplicate of v1 but some are fixed)] 1.1. Zfhmin/Zhinxmin subset extension support (PATCH 03) This patch implements Zfhmin/Zhinxmin extension, conversion-only subset of Zfh/Zhinx instruction set extensions, respectively. 1.2. [minor] Refactoring for better integration (PATCH 01) In particular, better integration with F, D and Q. To do that, it required moving certain macros and constants. But there are no functional changes. The whole patchset would (and should) work without this patch. 1.3. [minor] DECLARE_INSN declarations (PATCH 02) Zfh instructions did not have their own DECLARE_INSN declarations. PATCH 02 resolves this problem (although not having those is harmless on current design). 2.1. Disassembler output with Zfinx + -M numeric option (PATCH 04) Disassembling Zhinx/Zhinxmin/Zfinx/Zdinx/Zqinx instructions with -M numeric option has an issue. It used ABI names instead of numeric one. This commit fixes that. 2.2. Enhanced Zfinx/Zdinx/Zqinx testcases (PATCH 05) I enhanced Zfinx/Zdinx/Zqinx testcases based on Jiawei's Zhinx support patch. I also... - Made indentation / coding style consistent and clean - Started to use valid register number (on Zqinx) - Started to use different register per operand 2.3. Relaxed requirements to fmv.[sdq] instructions (PATCH 06) On Zfinx/Zdinx/Zqinx, fmv instructions seem redundant but actually not. On RV32_Z[dq]inx and RV64_Zqinx, it requires register pair. That means, single... fmv.d x10, x12 is equivalent to 2 regular instructions on RV32_Zdinx (with 32b GPRs): mv x10, x12 mv x11, x13 Since fsgnj.[sdq] (base instruction of fmv.[sdq]) are a part of Z[fdq]inx extensions, it's safe to implement this pseudoinstructions. PATCH 06 makes fmv.[sdq] available to Zfinx/Zdinx/Zqinx environments. 2.4. Validate register pairs on Zdinx/Zqinx (PATCH 07, 08) For RV32_Zdinx and RV64_Zqinx, all registers holding a FP64 value must be even (x0, x2, x4... are valid, x1, x3, x5... are invalid). For RV32_Zqinx, it would be all registers holding a FP128 value must be a multiple of 4 (x0, x4, x8... are valid, x1, x2, x3, x5... are not). On the other hand, current Binutils can generate invalid instructions with odd register numbers (or register number x % 4 != 0). PATCH 07 makes those invalid and PATCH 08 adds tests. Due to complexity, this patch is relatively large. Tsukasa OI (8): RISC-V: Refactor Zfh/Zhinx-related constants RISC-V: Add instruction declaration for Zfh/Zhinx RISC-V: Add Zfhmin/Zhinxmin (with refactoring) RISC-V: Fix disassembling Zfinx with -M numeric RISC-V: Reorganize and enhance Zfinx tests RISC-V: Relax `fmv.[sdq]' requirements RISC-V: Validate Zdinx/Zqinx register pairs RISC-V: Add testcases for Z[dq]inx register pairs bfd/elfxx-riscv.c | 87 ++- gas/config/tc-riscv.c | 40 +- .../gas/riscv/zdinx-32-regpair-dis.d | 11 + .../gas/riscv/zdinx-32-regpair-dis.s | 5 + .../gas/riscv/zdinx-32-regpair-fail.d | 3 + .../gas/riscv/zdinx-32-regpair-fail.l | 111 +++ .../gas/riscv/zdinx-32-regpair-fail.s | 116 +++ gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 ++ gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++ gas/testsuite/gas/riscv/zdinx.d | 27 +- gas/testsuite/gas/riscv/zdinx.s | 46 +- .../gas/riscv/zfhmin-d-insn-class-fail-1.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-1.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-2.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-2.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-3.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-3.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-4.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-4.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-5.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-5.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail.s | 4 + gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 + gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 + gas/testsuite/gas/riscv/zfinx.d | 24 +- gas/testsuite/gas/riscv/zfinx.s | 42 +- .../gas/riscv/{fp-zhinx-insns.d => zhinx.d} | 37 +- .../gas/riscv/{fp-zhinx-insns.s => zhinx.s} | 32 +- .../gas/riscv/zqinx-32-regpair-dis.d | 12 + .../gas/riscv/zqinx-32-regpair-dis.s | 7 + .../gas/riscv/zqinx-32-regpair-fail.d | 3 + .../gas/riscv/zqinx-32-regpair-fail.l | 212 ++++++ .../gas/riscv/zqinx-32-regpair-fail.s | 218 ++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 ++ gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 ++ .../gas/riscv/zqinx-64-regpair-dis.d | 11 + .../gas/riscv/zqinx-64-regpair-dis.s | 5 + .../gas/riscv/zqinx-64-regpair-fail.d | 3 + .../gas/riscv/zqinx-64-regpair-fail.l | 133 ++++ .../gas/riscv/zqinx-64-regpair-fail.s | 138 ++++ gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++ gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++ gas/testsuite/gas/riscv/zqinx.d | 86 ++- gas/testsuite/gas/riscv/zqinx.s | 89 ++- include/opcode/riscv-opc.h | 180 +++-- include/opcode/riscv.h | 21 +- opcodes/riscv-dis.c | 2 +- opcodes/riscv-opc.c | 667 +++++++++++++----- 48 files changed, 2419 insertions(+), 418 deletions(-) create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s rename gas/testsuite/gas/riscv/{fp-zhinx-insns.d => zhinx.d} (81%) rename gas/testsuite/gas/riscv/{fp-zhinx-insns.s => zhinx.s} (85%) create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s base-commit: b4eb841afe9306fd7a6df95efcde120bfaa71e32 -- 2.25.1