From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTP id 9174C3858292 for ; Mon, 11 Jul 2022 07:31:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9174C3858292 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [180.102.239.252]) by APP-05 (Coremail) with SMTP id zQCowAC3vbGv0ctiP_B_DA--.31419S2; Mon, 11 Jul 2022 15:30:56 +0800 (CST) From: shihua@iscas.ac.cn To: binutils@sourceware.org Cc: kito.cheng@sifive.com, jim.wilson.gcc@gmail.com, shiyulong@iscas.ac.cn, cmuellner@ventanamicro.com, palmer@dabbelt.com, andrew@sifive.com, lazyparser@gmail.com, jiawei@iscas.ac.cn, anku.anand@gmail.com, LiaoShihua Subject: [PATCH] RISC-V: Support Zmmul extension Date: Mon, 11 Jul 2022 15:30:42 +0800 Message-Id: <20220711073042.2009-1-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.31.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: zQCowAC3vbGv0ctiP_B_DA--.31419S2 X-Coremail-Antispam: 1UD129KBjvJXoWxJw1xXr17tw47WrWftr1kKrg_yoWrAF1DpF s5Ga1jvF9Iy3Z2qr97ZFyY9r13Za90qF43KF4Y93Z8Aw4jqr48Jryktw1DZFykXFs0gF1I ga15Kr45Z3yUu3JanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9Y14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxV W0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv 7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r 1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02 628vn2kIc2xKxwAKzVCY07xG64k0F24l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7 v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF 1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIx AIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWrJr0_WFyU JwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCT nIWIevJa73UjIFyTuYvjfUOxhLUUUUU X-Originating-IP: [180.102.239.252] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiCgwEEWKY1hO2KQABsy X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jul 2022 07:31:04 -0000 From: LiaoShihua Zmmul extension is Multiply only extension for RISC-V.It implements the multiplication subset of the M extension. The encodings are identical to those of the corresponding M-extension instructions. bfd\ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports):Add support for Zmmul extension (riscv_multi_subset_supports_ext):Ditto. include\ChangeLog: * opcode/riscv.h (enum riscv_insn_class):Ditto. opcodes\ChangeLog: * riscv-opc.c:Ditto. --- bfd/elfxx-riscv.c | 6 ++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 10 +++++----- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index bf7dc20e892..3c9c961352a 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1226,6 +1226,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zvl16384b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32768b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl65536b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2395,6 +2396,9 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: return riscv_subset_supports (rps, "h"); + case INSN_CLASS_M_OR_ZMMUL: + return (riscv_subset_supports (rps, "m") + || riscv_subset_supports (rps, "zmmul")); default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); @@ -2500,6 +2504,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("('q' and 'zfh') or 'zhinx"); case INSN_CLASS_H: return _("h"); + case INSN_CLASS_M_OR_ZMMUL: + return _("m' or `zmmul"); default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 808f05f3d7a..0021b7434ea 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -396,6 +396,7 @@ enum riscv_insn_class INSN_CLASS_ZICBOP, INSN_CLASS_ZICBOZ, INSN_CLASS_H, + INSN_CLASS_M_OR_ZMMUL, }; /* This structure holds information for a particular instruction. */ diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index d5cedbe176c..958364fd5c0 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -558,15 +558,15 @@ const struct riscv_opcode riscv_opcodes[] = {"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, /* Multiply/Divide instruction subset. */ -{"mul", 0, INSN_CLASS_M, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, -{"mulh", 0, INSN_CLASS_M, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 }, -{"mulhu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 }, -{"mulhsu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 }, +{"mul", 0, INSN_CLASS_M_OR_ZMMUL, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, +{"mulh", 0, INSN_CLASS_M_OR_ZMMUL, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 }, +{"mulhu", 0, INSN_CLASS_M_OR_ZMMUL, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 }, +{"mulhsu", 0, INSN_CLASS_M_OR_ZMMUL, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 }, {"div", 0, INSN_CLASS_M, "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, 0 }, {"divu", 0, INSN_CLASS_M, "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, 0 }, {"rem", 0, INSN_CLASS_M, "d,s,t", MATCH_REM, MASK_REM, match_opcode, 0 }, {"remu", 0, INSN_CLASS_M, "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, 0 }, -{"mulw", 64, INSN_CLASS_M, "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 }, +{"mulw", 64, INSN_CLASS_M_OR_ZMMUL, "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 }, {"divw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 }, {"divuw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 }, {"remw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 }, -- 2.31.1.windows.1