From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mailbox.box.xen0n.name (mail.xen0n.name [115.28.160.31]) by sourceware.org (Postfix) with ESMTPS id 9B45D3857005 for ; Wed, 27 Jul 2022 11:08:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9B45D3857005 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xen0n.name DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xen0n.name; s=mail; t=1658920086; bh=co7UUOOgIn7ZNdWV1pGpnYY+ntmsXeMzGpqOwp/Rnfo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WiQ/wZFcmcllnmPNaMrLeNeZ8kz3Gr5voqSXBevBGaeRzmBQzWocFsyyKOstVL82O P/t7Tlb6b18xPXbSz5JGXuuoikivYABHA34fPRS51QobZDiJX3cBJiyQAN5qY/1r7M k3oIUN1moZyPrjyhJVm91mS9mV0WO3EAJ86GKNuc= Received: from ld50.lan (unknown [101.228.137.40]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 90ED060680; Wed, 27 Jul 2022 19:08:06 +0800 (CST) From: WANG Xuerui To: binutils@sourceware.org Cc: Chenghua Xu , Zhensong Liu , Xi Ruoyao , WANG Xuerui Subject: [PATCH 2/2] opcodes: LoongArch: add "ret" instruction to reduce typing Date: Wed, 27 Jul 2022 19:07:57 +0800 Message-Id: <20220727110757.2520234-3-i.swmail@xen0n.name> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220727110757.2520234-1-i.swmail@xen0n.name> References: <20220727110757.2520234-1-i.swmail@xen0n.name> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jul 2022 11:08:13 -0000 From: WANG Xuerui This syntactic sugar is present in both classical and emerging architectures, like Alpha, SPARC and RISC-V, and assembler macros doing the same thing can already be found in the wild e.g. [1], proving the feature's popularity. It's better to provide support directly in the assembler so downstream users wouldn't have to re-invent this over and over again. [1]: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/unix/sysv/linux/loongarch/sysdep.h;h=c586df819cd90;hb=HEAD#l28 --- opcodes/loongarch-opc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c index 6f5e42d57e5..e4e3a512f03 100644 --- a/opcodes/loongarch-opc.c +++ b/opcodes/loongarch-opc.c @@ -841,6 +841,7 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] = { 0x0, 0x0, "bgtu", "r,r,la", "bltu %2,%1,%%b16(%3)", 0, 0, 0 }, { 0x0, 0x0, "bleu", "r,r,la", "bgeu %2,%1,%%b16(%3)", 0, 0, 0 }, { 0x0, 0x0, "jr", "r", "jirl $r0,%1,0", 0, 0, 0 }, + { 0x0, 0x0, "ret", "", "jirl $r0,$r1,0", 0, 0, 0 }, { 0 } /* Terminate the list. */ }; -- 2.35.1