From: Christoph Muellner <christoph.muellner@vrull.eu>
To: binutils@sourceware.org, Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Cooper Qu <cooper.qu@linux.alibaba.com>,
Lifang Xia <lifang_xia@linux.alibaba.com>,
Yunhai Shang <yunhai@linux.alibaba.com>,
Zhiwei Liu <zhiwei_liu@linux.alibaba.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH 10/13] RISC-V: Add support for literal instruction arguments
Date: Tue, 6 Sep 2022 14:22:10 +0200 [thread overview]
Message-ID: <20220906122213.1243129-11-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20220906122213.1243129-1-christoph.muellner@vrull.eu>
From: Christoph Müllner <christoph.muellner@vrull.eu>
This patch introduces support for arbitrary literal instruction
arguments, that are not encoded in the opcode.
A typical use case for this feature would be an instruction that
applies an implicit shift by a constant value on an immediate
(that is a real operand). With this patch it is possible to make
this shift visible in the dissasembly and support such artificial
parameter as part of the asssembly code.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
gas/config/tc-riscv.c | 14 ++++++++++++++
opcodes/riscv-dis.c | 10 ++++++++++
2 files changed, 24 insertions(+)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 7f0db9fdb80..e89e9f492d9 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1258,6 +1258,10 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
goto unknown_validate_operand;
}
break;
+ case 'L': /* Literal. */
+ oparg += strcspn(oparg, ",") - 1;
+ break;
+
case 'X': /* Integer immediate. */
{
size_t n;
@@ -3295,6 +3299,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
asarg = expr_end;
continue;
+ case 'L': /* Literal. */
+ {
+ size_t n = strcspn (++oparg, ",");
+ if (strncmp (oparg, asarg, n))
+ as_bad (_("unexpected literal (%s)"), asarg);
+ oparg += n - 1;
+ asarg += n;
+ }
+ continue;
+
case 'X': /* Integer immediate. */
{
size_t n;
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index c6ddea16dda..a4b030aa415 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -563,6 +563,16 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, dis_style_text, "%d", rs1);
break;
+ case 'L': /* Literal. */
+ oparg++;
+ while (*oparg && *oparg != ',')
+ {
+ print (info->stream, dis_style_text, "%c", *oparg);
+ oparg++;
+ }
+ oparg--;
+ break;
+
case 'X': /* Integer immediate. */
{
size_t n;
--
2.37.2
next prev parent reply other threads:[~2022-09-06 12:22 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-06 12:22 [PATCH 00/13] Add support for the T-Head vendor extensions Christoph Muellner
2022-09-06 12:22 ` [PATCH 01/13] RISC-V: Add generic support for " Christoph Muellner
2022-09-06 12:22 ` [PATCH 02/13] RISC-V: Add T-Head CMO vendor extension Christoph Muellner
2022-09-06 12:22 ` [PATCH 03/13] RISC-V: Add T-Head SYNC " Christoph Muellner
2022-09-06 12:22 ` [PATCH 04/13] RISC-V: Add support for arbitrary immediate encoding formats Christoph Muellner
2022-09-06 12:22 ` [PATCH 05/13] RISC-V: Add T-Head Bitmanip vendor extension Christoph Muellner
2022-09-06 12:22 ` [PATCH 06/13] RISC-V: Add T-Head CondMov " Christoph Muellner
2022-09-06 12:22 ` [PATCH 07/13] RISC-V: Add T-Head MAC " Christoph Muellner
2022-09-06 12:22 ` [PATCH 08/13] RISC-V: Add T-Head FMemIdx " Christoph Muellner
2022-09-06 12:22 ` [PATCH 09/13] RISC-V: Add T-Head MemIdx " Christoph Muellner
2022-09-06 12:22 ` Christoph Muellner [this message]
2022-09-06 12:22 ` [PATCH 11/13] RISC-V: Add T-Head MemPair " Christoph Muellner
2022-09-06 12:22 ` [PATCH 12/13] riscv: gas: Add command line option '-mcpu=' to specify the CPU Christoph Muellner
2022-09-06 12:22 ` [PATCH 13/13] riscv: Add T-Head entries for the -mcpu= flag Christoph Muellner
2022-09-16 9:36 ` [PATCH 00/13] Add support for the T-Head vendor extensions Nelson Chu
2022-09-16 9:58 ` Palmer Dabbelt
2022-09-18 6:51 ` Christoph Müllner
2022-09-18 6:50 ` Christoph Müllner
2022-09-22 11:08 ` Philipp Tomsich
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