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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id y21-20020a170906525500b0073d7e58b1bcsm6571632ejm.157.2022.09.06.05.22.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:31 -0700 (PDT) From: Christoph Muellner To: binutils@sourceware.org, Nelson Chu , Kito Cheng , Jim Wilson , Philipp Tomsich , Palmer Dabbelt , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 10/13] RISC-V: Add support for literal instruction arguments Date: Tue, 6 Sep 2022 14:22:10 +0200 Message-Id: <20220906122213.1243129-11-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122213.1243129-1-christoph.muellner@vrull.eu> References: <20220906122213.1243129-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_MANYTO,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph Müllner This patch introduces support for arbitrary literal instruction arguments, that are not encoded in the opcode. A typical use case for this feature would be an instruction that applies an implicit shift by a constant value on an immediate (that is a real operand). With this patch it is possible to make this shift visible in the dissasembly and support such artificial parameter as part of the asssembly code. Signed-off-by: Christoph Müllner --- gas/config/tc-riscv.c | 14 ++++++++++++++ opcodes/riscv-dis.c | 10 ++++++++++ 2 files changed, 24 insertions(+) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 7f0db9fdb80..e89e9f492d9 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1258,6 +1258,10 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) goto unknown_validate_operand; } break; + case 'L': /* Literal. */ + oparg += strcspn(oparg, ",") - 1; + break; + case 'X': /* Integer immediate. */ { size_t n; @@ -3295,6 +3299,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, asarg = expr_end; continue; + case 'L': /* Literal. */ + { + size_t n = strcspn (++oparg, ","); + if (strncmp (oparg, asarg, n)) + as_bad (_("unexpected literal (%s)"), asarg); + oparg += n - 1; + asarg += n; + } + continue; + case 'X': /* Integer immediate. */ { size_t n; diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index c6ddea16dda..a4b030aa415 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -563,6 +563,16 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info print (info->stream, dis_style_text, "%d", rs1); break; + case 'L': /* Literal. */ + oparg++; + while (*oparg && *oparg != ',') + { + print (info->stream, dis_style_text, "%c", *oparg); + oparg++; + } + oparg--; + break; + case 'X': /* Integer immediate. */ { size_t n; -- 2.37.2