From: Christoph Muellner <christoph.muellner@vrull.eu>
To: binutils@sourceware.org, Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Cooper Qu <cooper.qu@linux.alibaba.com>,
Lifang Xia <lifang_xia@linux.alibaba.com>,
Yunhai Shang <yunhai@linux.alibaba.com>,
Zhiwei Liu <zhiwei_liu@linux.alibaba.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH 12/13] riscv: gas: Add command line option '-mcpu=' to specify the CPU
Date: Tue, 6 Sep 2022 14:22:12 +0200 [thread overview]
Message-ID: <20220906122213.1243129-13-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20220906122213.1243129-1-christoph.muellner@vrull.eu>
From: Christoph Müllner <christoph.muellner@vrull.eu>
There are devices in the field, that need a quite long
"-march="-argument to specify the available ISA extensions.
Let's introduce a pretty-name mechanism for them, so they have
a more user-friendly way to enable their ISA extensions.
Restrictions for this new -mcpu= flag are:
* the provided CPU name must be known (otherwise we bail out)
* mixing with -march is possible, but the last cmdln argument wins
(i.e. no merging)
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
gas/config/tc-riscv.c | 33 +++++++++++++++++++++
gas/doc/c-riscv.texi | 6 ++++
gas/testsuite/gas/riscv/mcpu-fail-unknown.d | 3 ++
gas/testsuite/gas/riscv/mcpu-fail-unknown.l | 2 ++
4 files changed, 44 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/mcpu-fail-unknown.d
create mode 100644 gas/testsuite/gas/riscv/mcpu-fail-unknown.l
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index e89e9f492d9..22109e5912f 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -3476,6 +3476,7 @@ const char *md_shortopts = "O::g::G:";
enum options
{
OPTION_MARCH = OPTION_MD_BASE,
+ OPTION_MCPU,
OPTION_PIC,
OPTION_NO_PIC,
OPTION_MABI,
@@ -3495,6 +3496,7 @@ enum options
struct option md_longopts[] =
{
{"march", required_argument, NULL, OPTION_MARCH},
+ {"mcpu", required_argument, NULL, OPTION_MCPU},
{"fPIC", no_argument, NULL, OPTION_PIC},
{"fpic", no_argument, NULL, OPTION_PIC},
{"fno-pic", no_argument, NULL, OPTION_NO_PIC},
@@ -3514,6 +3516,33 @@ struct option md_longopts[] =
};
size_t md_longopts_size = sizeof (md_longopts);
+struct riscv_cpu_option_table
+{
+ const char *name;
+ const char *arch;
+};
+
+/* This table maps a CPU name (for -mcpu=$name) to the corresponding
+ arch string. */
+static const struct riscv_cpu_option_table riscv_cpus[] = {
+ { NULL, NULL }
+};
+
+/* Returns the arch for the provided CPU name, or NULL if not known. */
+static const char*
+get_riscv_arch_for_cpu(const char* mcpu)
+{
+ const struct riscv_cpu_option_table *cpu;
+
+ for (cpu = &riscv_cpus[0]; cpu->name; cpu++)
+ {
+ if (!strcmp(cpu->name, mcpu))
+ return cpu->arch;
+ }
+ as_bad (_("unknown CPU `%s'"), mcpu);
+ return NULL;
+}
+
int
md_parse_option (int c, const char *arg)
{
@@ -3523,6 +3552,10 @@ md_parse_option (int c, const char *arg)
default_arch_with_ext = arg;
break;
+ case OPTION_MCPU:
+ default_arch_with_ext = get_riscv_arch_for_cpu(arg);
+ break;
+
case OPTION_NO_PIC:
riscv_opts.pic = false;
break;
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index cc63760cb80..488f88791d1 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -46,6 +46,12 @@ Select the base isa, as specified by ISA. For example -march=rv32ima.
If this option and the architecture attributes aren't set, then assembler
will check the default configure setting --with-arch=ISA.
+@cindex @samp{-mcpu=CPU} option, RISC-V
+@item -mcpu=CPU
+This option specifies the target processor. The assembler will issue an error
+message if an attempt is made to assemble an instruction which will not execute
+on the target processor.
+
@cindex @samp{-misa-spec=ISAspec} option, RISC-V
@item -misa-spec=ISAspec
Select the default isa spec version. If the version of ISA isn't set
diff --git a/gas/testsuite/gas/riscv/mcpu-fail-unknown.d b/gas/testsuite/gas/riscv/mcpu-fail-unknown.d
new file mode 100644
index 00000000000..8afe43632d8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/mcpu-fail-unknown.d
@@ -0,0 +1,3 @@
+#as: -mcpu=foo
+#source: empty.s
+#error_output: mcpu-fail-unknown.l
diff --git a/gas/testsuite/gas/riscv/mcpu-fail-unknown.l b/gas/testsuite/gas/riscv/mcpu-fail-unknown.l
new file mode 100644
index 00000000000..dccca4fb42d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/mcpu-fail-unknown.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*Error: .*unknown CPU `foo'
--
2.37.2
next prev parent reply other threads:[~2022-09-06 12:22 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-06 12:22 [PATCH 00/13] Add support for the T-Head vendor extensions Christoph Muellner
2022-09-06 12:22 ` [PATCH 01/13] RISC-V: Add generic support for " Christoph Muellner
2022-09-06 12:22 ` [PATCH 02/13] RISC-V: Add T-Head CMO vendor extension Christoph Muellner
2022-09-06 12:22 ` [PATCH 03/13] RISC-V: Add T-Head SYNC " Christoph Muellner
2022-09-06 12:22 ` [PATCH 04/13] RISC-V: Add support for arbitrary immediate encoding formats Christoph Muellner
2022-09-06 12:22 ` [PATCH 05/13] RISC-V: Add T-Head Bitmanip vendor extension Christoph Muellner
2022-09-06 12:22 ` [PATCH 06/13] RISC-V: Add T-Head CondMov " Christoph Muellner
2022-09-06 12:22 ` [PATCH 07/13] RISC-V: Add T-Head MAC " Christoph Muellner
2022-09-06 12:22 ` [PATCH 08/13] RISC-V: Add T-Head FMemIdx " Christoph Muellner
2022-09-06 12:22 ` [PATCH 09/13] RISC-V: Add T-Head MemIdx " Christoph Muellner
2022-09-06 12:22 ` [PATCH 10/13] RISC-V: Add support for literal instruction arguments Christoph Muellner
2022-09-06 12:22 ` [PATCH 11/13] RISC-V: Add T-Head MemPair vendor extension Christoph Muellner
2022-09-06 12:22 ` Christoph Muellner [this message]
2022-09-06 12:22 ` [PATCH 13/13] riscv: Add T-Head entries for the -mcpu= flag Christoph Muellner
2022-09-16 9:36 ` [PATCH 00/13] Add support for the T-Head vendor extensions Nelson Chu
2022-09-16 9:58 ` Palmer Dabbelt
2022-09-18 6:51 ` Christoph Müllner
2022-09-18 6:50 ` Christoph Müllner
2022-09-22 11:08 ` Philipp Tomsich
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