From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by sourceware.org (Postfix) with ESMTPS id 0BAD8384D17C for ; Tue, 6 Sep 2022 12:22:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0BAD8384D17C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x631.google.com with SMTP id qh18so22797007ejb.7 for ; Tue, 06 Sep 2022 05:22:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=5NgIpNckXlbYxjqug/Tgq0aAgEhI8jKGLfg6pQlJiOM=; b=OwU6j29br4KzYjUbCa+LzgKOCrt2wOxvMGuL052QXc/P00b5+w/jI/zXjOqfb/CcVX kijxfGuaGShVBa8p1dUfqUy6iHadNgXtJCjJnlL1bTIcRQWj/BFSkxqYArW+TIWjpqmg ipERZ+JFmbMy36VVP+GEcbM3zCrfafFtsfc5iAAGxK7czYYfUbnrJ+64gQeeaQRQXFrd ddBsoNpd/U83ejEzsogJl5clVf4r63NpKsnKN8N02eY1/XwGcqvJPU+2WyH8UCcry1ny 9KVEWEgPla6egJzq/11rhU0Pq9vzNUiAMq9uAnwZPPOMHSbW7xLpFlhGOF7g4Bd/Mdgr k2mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=5NgIpNckXlbYxjqug/Tgq0aAgEhI8jKGLfg6pQlJiOM=; b=srvI3NUNAu5jz37LtgP2TXVw6qo/LYYLuYhD/TJKkC9rRRFVC0WdyXflLXYj+j/2oO XgZ+4pPupRQVHzz7jYCQ4zmpR9WMPRRINihVYLqOQkaMmltWAntp97Jh0QC2kUtFiCbp 1Z15RfZyOgobEYIMnn/q8hrM3vrnb94nWM02gzuELjwEpRZWLr/OEGGTvgk9mbIUbBaS ifwYEWNA2wiUL2rigfOk4iMOTc56leprjhlZCPK3QtpCXR8cy9V4/oBwxp72DObolhjR Hfhq9TUY+6Az4nVIuCnK8jwH/bwMsqgWoSbWR1hEt8e+3dNxWpBZR0nw3GFDzzDuxqoZ 4Ptg== X-Gm-Message-State: ACgBeo3jnQgfAX5mg5yGcci1HoHbYr5Rc+DxNutZfjLX0FfGi4puL1rZ heBrhXEmz3xODvTIUNtiCbFe6O9NR3cnmg== X-Google-Smtp-Source: AA6agR4gSaNsivdn6SC6XWFZa949/sz8P6/ujPRwybTOB7TQ5EnpcNHHuiB5vmkN6pt2f9hx1dzalg== X-Received: by 2002:a17:907:c28:b0:73d:beb7:b9c2 with SMTP id ga40-20020a1709070c2800b0073dbeb7b9c2mr39093412ejc.336.1662466955475; Tue, 06 Sep 2022 05:22:35 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id y21-20020a170906525500b0073d7e58b1bcsm6571632ejm.157.2022.09.06.05.22.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:34 -0700 (PDT) From: Christoph Muellner To: binutils@sourceware.org, Nelson Chu , Kito Cheng , Jim Wilson , Philipp Tomsich , Palmer Dabbelt , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 12/13] riscv: gas: Add command line option '-mcpu=' to specify the CPU Date: Tue, 6 Sep 2022 14:22:12 +0200 Message-Id: <20220906122213.1243129-13-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122213.1243129-1-christoph.muellner@vrull.eu> References: <20220906122213.1243129-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_MANYTO,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph Müllner There are devices in the field, that need a quite long "-march="-argument to specify the available ISA extensions. Let's introduce a pretty-name mechanism for them, so they have a more user-friendly way to enable their ISA extensions. Restrictions for this new -mcpu= flag are: * the provided CPU name must be known (otherwise we bail out) * mixing with -march is possible, but the last cmdln argument wins (i.e. no merging) Signed-off-by: Christoph Müllner --- gas/config/tc-riscv.c | 33 +++++++++++++++++++++ gas/doc/c-riscv.texi | 6 ++++ gas/testsuite/gas/riscv/mcpu-fail-unknown.d | 3 ++ gas/testsuite/gas/riscv/mcpu-fail-unknown.l | 2 ++ 4 files changed, 44 insertions(+) create mode 100644 gas/testsuite/gas/riscv/mcpu-fail-unknown.d create mode 100644 gas/testsuite/gas/riscv/mcpu-fail-unknown.l diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index e89e9f492d9..22109e5912f 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -3476,6 +3476,7 @@ const char *md_shortopts = "O::g::G:"; enum options { OPTION_MARCH = OPTION_MD_BASE, + OPTION_MCPU, OPTION_PIC, OPTION_NO_PIC, OPTION_MABI, @@ -3495,6 +3496,7 @@ enum options struct option md_longopts[] = { {"march", required_argument, NULL, OPTION_MARCH}, + {"mcpu", required_argument, NULL, OPTION_MCPU}, {"fPIC", no_argument, NULL, OPTION_PIC}, {"fpic", no_argument, NULL, OPTION_PIC}, {"fno-pic", no_argument, NULL, OPTION_NO_PIC}, @@ -3514,6 +3516,33 @@ struct option md_longopts[] = }; size_t md_longopts_size = sizeof (md_longopts); +struct riscv_cpu_option_table +{ + const char *name; + const char *arch; +}; + +/* This table maps a CPU name (for -mcpu=$name) to the corresponding + arch string. */ +static const struct riscv_cpu_option_table riscv_cpus[] = { + { NULL, NULL } +}; + +/* Returns the arch for the provided CPU name, or NULL if not known. */ +static const char* +get_riscv_arch_for_cpu(const char* mcpu) +{ + const struct riscv_cpu_option_table *cpu; + + for (cpu = &riscv_cpus[0]; cpu->name; cpu++) + { + if (!strcmp(cpu->name, mcpu)) + return cpu->arch; + } + as_bad (_("unknown CPU `%s'"), mcpu); + return NULL; +} + int md_parse_option (int c, const char *arg) { @@ -3523,6 +3552,10 @@ md_parse_option (int c, const char *arg) default_arch_with_ext = arg; break; + case OPTION_MCPU: + default_arch_with_ext = get_riscv_arch_for_cpu(arg); + break; + case OPTION_NO_PIC: riscv_opts.pic = false; break; diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index cc63760cb80..488f88791d1 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -46,6 +46,12 @@ Select the base isa, as specified by ISA. For example -march=rv32ima. If this option and the architecture attributes aren't set, then assembler will check the default configure setting --with-arch=ISA. +@cindex @samp{-mcpu=CPU} option, RISC-V +@item -mcpu=CPU +This option specifies the target processor. The assembler will issue an error +message if an attempt is made to assemble an instruction which will not execute +on the target processor. + @cindex @samp{-misa-spec=ISAspec} option, RISC-V @item -misa-spec=ISAspec Select the default isa spec version. If the version of ISA isn't set diff --git a/gas/testsuite/gas/riscv/mcpu-fail-unknown.d b/gas/testsuite/gas/riscv/mcpu-fail-unknown.d new file mode 100644 index 00000000000..8afe43632d8 --- /dev/null +++ b/gas/testsuite/gas/riscv/mcpu-fail-unknown.d @@ -0,0 +1,3 @@ +#as: -mcpu=foo +#source: empty.s +#error_output: mcpu-fail-unknown.l diff --git a/gas/testsuite/gas/riscv/mcpu-fail-unknown.l b/gas/testsuite/gas/riscv/mcpu-fail-unknown.l new file mode 100644 index 00000000000..dccca4fb42d --- /dev/null +++ b/gas/testsuite/gas/riscv/mcpu-fail-unknown.l @@ -0,0 +1,2 @@ +.*Assembler messages: +.*Error: .*unknown CPU `foo' -- 2.37.2