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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id y21-20020a170906525500b0073d7e58b1bcsm6571632ejm.157.2022.09.06.05.22.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:36 -0700 (PDT) From: Christoph Muellner To: binutils@sourceware.org, Nelson Chu , Kito Cheng , Jim Wilson , Philipp Tomsich , Palmer Dabbelt , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 13/13] riscv: Add T-Head entries for the -mcpu= flag Date: Tue, 6 Sep 2022 14:22:13 +0200 Message-Id: <20220906122213.1243129-14-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122213.1243129-1-christoph.muellner@vrull.eu> References: <20220906122213.1243129-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_MANYTO,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph Müllner This patch adds the following T-Head CPUs to the list of known CPUs: * C906 * C910 Signed-off-by: Christoph Müllner --- gas/config/tc-riscv.c | 6 ++++++ gas/doc/c-riscv.texi | 3 ++- gas/testsuite/gas/riscv/mcpu-ok-c906.d | 6 ++++++ gas/testsuite/gas/riscv/mcpu-ok-c910.d | 6 ++++++ 4 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/riscv/mcpu-ok-c906.d create mode 100644 gas/testsuite/gas/riscv/mcpu-ok-c910.d diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 22109e5912f..1d606b60ce9 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -3525,6 +3525,12 @@ struct riscv_cpu_option_table /* This table maps a CPU name (for -mcpu=$name) to the corresponding arch string. */ static const struct riscv_cpu_option_table riscv_cpus[] = { + { "thead-c906", "rv64gc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov" + "_xtheadfmemidx_xtheadmac_xtheadmemidx_xtheadmempair" + "_xtheadsync" }, + { "thead-c910", "rv64gc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov" + "_xtheadfmemidx_xtheadmac_xtheadmemidx_xtheadmempair" + "_xtheadsync" }, { NULL, NULL } }; diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 488f88791d1..68705ed89c9 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -50,7 +50,8 @@ will check the default configure setting --with-arch=ISA. @item -mcpu=CPU This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute -on the target processor. +on the target processor. The following processor names are recognized: +@code{thead-c906}, and @code{thead-c910}. @cindex @samp{-misa-spec=ISAspec} option, RISC-V @item -misa-spec=ISAspec diff --git a/gas/testsuite/gas/riscv/mcpu-ok-c906.d b/gas/testsuite/gas/riscv/mcpu-ok-c906.d new file mode 100644 index 00000000000..ce06f3e323b --- /dev/null +++ b/gas/testsuite/gas/riscv/mcpu-ok-c906.d @@ -0,0 +1,6 @@ +#as: -mcpu=thead-c906 +#readelf: -A +#source: empty.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_xtheadba1p0_xtheadbb1p0_xtheadbs1p0_xtheadcmo1p0_xtheadcondmov1p0_xtheadfmemidx1p0_xtheadmac1p0_xtheadmemidx1p0_xtheadmempair1p0_xtheadsync1p0" diff --git a/gas/testsuite/gas/riscv/mcpu-ok-c910.d b/gas/testsuite/gas/riscv/mcpu-ok-c910.d new file mode 100644 index 00000000000..0e660c10a81 --- /dev/null +++ b/gas/testsuite/gas/riscv/mcpu-ok-c910.d @@ -0,0 +1,6 @@ +#as: -mcpu=thead-c910 +#readelf: -A +#source: empty.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_xtheadba1p0_xtheadbb1p0_xtheadbs1p0_xtheadcmo1p0_xtheadcondmov1p0_xtheadfmemidx1p0_xtheadmac1p0_xtheadmemidx1p0_xtheadmempair1p0_xtheadsync1p0" -- 2.37.2