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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id y21-20020a170906525500b0073d7e58b1bcsm6571632ejm.157.2022.09.06.05.22.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:26 -0700 (PDT) From: Christoph Muellner To: binutils@sourceware.org, Nelson Chu , Kito Cheng , Jim Wilson , Philipp Tomsich , Palmer Dabbelt , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 07/13] RISC-V: Add T-Head MAC vendor extension Date: Tue, 6 Sep 2022 14:22:07 +0200 Message-Id: <20220906122213.1243129-8-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122213.1243129-1-christoph.muellner@vrull.eu> References: <20220906122213.1243129-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_MANYTO,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph Müllner T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadMac extension, a collection of T-Head-specific multiply-accumulate instructions. The 'th' prefix and the "XTheadMac" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Signed-off-by: Christoph Müllner --- bfd/elfxx-riscv.c | 3 +++ gas/doc/c-riscv.texi | 5 +++++ gas/testsuite/gas/riscv/x-thead-mac.d | 15 +++++++++++++++ gas/testsuite/gas/riscv/x-thead-mac.s | 7 +++++++ include/opcode/riscv-opc.h | 20 ++++++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 8 ++++++++ 7 files changed, 59 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.d create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index d5e8a40a751..57414450d69 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1228,6 +1228,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadcondmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2401,6 +2402,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadcmo"); case INSN_CLASS_XTHEADCONDMOV: return riscv_subset_supports (rps, "xtheadcondmov"); + case INSN_CLASS_XTHEADMAC: + return riscv_subset_supports (rps, "xtheadmac"); case INSN_CLASS_XTHEADSYNC: return riscv_subset_supports (rps, "xtheadsync"); default: diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index b1462ce213b..401f7e443c2 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -729,6 +729,11 @@ The XTheadCondMov extension provides instructions for conditional moves. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XTheadMac +The XTheadMac extension provides multiply-accumulate instructions. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. + @item XTheadSync The XTheadSync extension provides instructions for multi-processor synchronization. diff --git a/gas/testsuite/gas/riscv/x-thead-mac.d b/gas/testsuite/gas/riscv/x-thead-mac.d new file mode 100644 index 00000000000..3f8e654797b --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-mac.d @@ -0,0 +1,15 @@ +#as: -march=rv64i_xtheadmac +#source: x-thead-mac.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+20c5950b[ ]+th.mula[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+28c5950b[ ]+th.mulah[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+24c5950b[ ]+th.mulaw[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+22c5950b[ ]+th.muls[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+2ac5950b[ ]+th.mulsh[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+26c5950b[ ]+th.mulsw[ ]+a0,a1,a2 diff --git a/gas/testsuite/gas/riscv/x-thead-mac.s b/gas/testsuite/gas/riscv/x-thead-mac.s new file mode 100644 index 00000000000..986b96f79e3 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-mac.s @@ -0,0 +1,7 @@ +target: + th.mula a0, a1, a2 + th.mulah a0, a1, a2 + th.mulaw a0, a1, a2 + th.muls a0, a1, a2 + th.mulsh a0, a1, a2 + th.mulsw a0, a1, a2 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 5c0f6100e29..b504ce019b6 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2186,6 +2186,19 @@ #define MASK_TH_MVEQZ 0xfe00707f #define MATCH_TH_MVNEZ 0x4200100b #define MASK_TH_MVNEZ 0xfe00707f +/* Vendor-specific (T-Head) XTheadMac instructions. */ +#define MATCH_TH_MULA 0x2000100b +#define MASK_TH_MULA 0xfe00707f +#define MATCH_TH_MULAH 0x2800100b +#define MASK_TH_MULAH 0xfe00707f +#define MATCH_TH_MULAW 0x2400100b +#define MASK_TH_MULAW 0xfe00707f +#define MATCH_TH_MULS 0x2200100b +#define MASK_TH_MULS 0xfe00707f +#define MATCH_TH_MULSH 0x2a00100b +#define MASK_TH_MULSH 0xfe00707f +#define MATCH_TH_MULSW 0x2600100b +#define MASK_TH_MULSW 0xfe00707f /* Vendor-specific (T-Head) XTheadSync instructions. */ #define MATCH_TH_SFENCE_VMAS 0x0400000b #define MASK_TH_SFENCE_VMAS 0xfe007fff @@ -2975,6 +2988,13 @@ DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL) /* Vendor-specific (T-Head) XTheadCondMov instructions. */ DECLARE_INSN(th_mveqz, MATCH_TH_MVEQZ, MASK_TH_MVEQZ) DECLARE_INSN(th_mvnez, MATCH_TH_MVNEZ, MASK_TH_MVNEZ) +/* Vendor-specific (T-Head) XTheadMac instructions. */ +DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA) +DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH) +DECLARE_INSN(th_mulaw, MATCH_TH_MULAW, MASK_TH_MULAW) +DECLARE_INSN(th_muls, MATCH_TH_MULS, MASK_TH_MULS) +DECLARE_INSN(th_mulsh, MATCH_TH_MULSH, MASK_TH_MULSH) +DECLARE_INSN(th_mulsw, MATCH_TH_MULSW, MASK_TH_MULSW) /* Vendor-specific (T-Head) XTheadSync instructions. */ DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS) DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index d0ff929f84b..854269a9d98 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -420,6 +420,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADBS, INSN_CLASS_XTHEADCMO, INSN_CLASS_XTHEADCONDMOV, + INSN_CLASS_XTHEADMAC, INSN_CLASS_XTHEADSYNC, }; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 111308686fc..5d5298923c8 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1871,6 +1871,14 @@ const struct riscv_opcode riscv_opcodes[] = {"th.mveqz", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVEQZ, MASK_TH_MVEQZ, match_opcode, 0}, {"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadMac instructions. */ +{"th.mula", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA, MASK_TH_MULA, match_opcode, 0}, +{"th.mulah", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAH, MASK_TH_MULAH, match_opcode, 0}, +{"th.mulaw", 64, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAW, MASK_TH_MULAW, match_opcode, 0}, +{"th.muls", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULS, MASK_TH_MULS, match_opcode, 0}, +{"th.mulsh", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULSH, MASK_TH_MULSH, match_opcode, 0}, +{"th.mulsw", 64, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULSW, MASK_TH_MULSW, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadSync instructions. */ {"th.sfence.vmas", 0, INSN_CLASS_XTHEADSYNC, "s,t",MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS, match_opcode, 0}, {"th.sync", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC, MASK_TH_SYNC, match_opcode, 0}, -- 2.37.2