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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id y21-20020a170906525500b0073d7e58b1bcsm6571632ejm.157.2022.09.06.05.22.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:28 -0700 (PDT) From: Christoph Muellner To: binutils@sourceware.org, Nelson Chu , Kito Cheng , Jim Wilson , Philipp Tomsich , Palmer Dabbelt , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 08/13] RISC-V: Add T-Head FMemIdx vendor extension Date: Tue, 6 Sep 2022 14:22:08 +0200 Message-Id: <20220906122213.1243129-9-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122213.1243129-1-christoph.muellner@vrull.eu> References: <20220906122213.1243129-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_MANYTO,RCVD_IN_DNSWL_NONE,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph Müllner T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadFMemIdx extension, a collection of T-Head-specific floating-point memory access instructions. The 'th' prefix and the "XTheadFMemIdx" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Signed-off-by: Christoph Müllner --- bfd/elfxx-riscv.c | 3 +++ gas/doc/c-riscv.texi | 5 ++++ .../gas/riscv/x-thead-fmemidx-fail.d | 3 +++ .../gas/riscv/x-thead-fmemidx-fail.l | 18 +++++++++++++ .../gas/riscv/x-thead-fmemidx-fail.s | 17 ++++++++++++ gas/testsuite/gas/riscv/x-thead-fmemidx.d | 25 ++++++++++++++++++ gas/testsuite/gas/riscv/x-thead-fmemidx.s | 17 ++++++++++++ include/opcode/riscv-opc.h | 26 +++++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 10 +++++++ 10 files changed, 125 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.d create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 57414450d69..922507b7fac 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1228,6 +1228,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadcondmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadfmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} @@ -2402,6 +2403,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadcmo"); case INSN_CLASS_XTHEADCONDMOV: return riscv_subset_supports (rps, "xtheadcondmov"); + case INSN_CLASS_XTHEADFMEMIDX: + return riscv_subset_supports (rps, "xtheadfmemidx"); case INSN_CLASS_XTHEADMAC: return riscv_subset_supports (rps, "xtheadmac"); case INSN_CLASS_XTHEADSYNC: diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 401f7e443c2..392be0e7e21 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -729,6 +729,11 @@ The XTheadCondMov extension provides instructions for conditional moves. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XTheadFMemIdx +The XTheadFMemIdx extension provides floating-point memory operations. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. + @item XTheadMac The XTheadMac extension provides multiply-accumulate instructions. diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d new file mode 100644 index 00000000000..a32e81eec46 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64i_xtheadfmemidx +#source: x-thead-fmemidx-fail.s +#error_output: x-thead-fmemidx-fail.l diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l new file mode 100644 index 00000000000..ef28f047b41 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l @@ -0,0 +1,18 @@ +.*: Assembler messages: +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) + diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s new file mode 100644 index 00000000000..e486c6a1423 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s @@ -0,0 +1,17 @@ +target: + th.flrd a0, a1, a2, -1 + th.flrd a0, a1, a2, 4 + th.flrw a0, a1, a2, -1 + th.flrw a0, a1, a2, 4 + th.flurd a0, a1, a2, -1 + th.flurd a0, a1, a2, 4 + th.flurw a0, a1, a2, -1 + th.flurw a0, a1, a2, 4 + th.fsrd a0, a1, a2, -1 + th.fsrd a0, a1, a2, 4 + th.fsrw a0, a1, a2, -1 + th.fsrw a0, a1, a2, 4 + th.fsurd a0, a1, a2, -1 + th.fsurd a0, a1, a2, 4 + th.fsurw a0, a1, a2, -1 + th.fsurw a0, a1, a2, 4 diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx.d b/gas/testsuite/gas/riscv/x-thead-fmemidx.d new file mode 100644 index 00000000000..dfa477c8fc4 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx.d @@ -0,0 +1,25 @@ +#as: -march=rv64i_xtheadfmemidx +#source: x-thead-fmemidx.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+60c5e50b[ ]+th.flrd[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+66c5e50b[ ]+th.flrd[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+40c5e50b[ ]+th.flrw[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+46c5e50b[ ]+th.flrw[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+70c5e50b[ ]+th.flurd[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+76c5e50b[ ]+th.flurd[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+50c5e50b[ ]+th.flurw[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+56c5e50b[ ]+th.flurw[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+60c5f50b[ ]+th.fsrd[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+66c5f50b[ ]+th.fsrd[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+40c5f50b[ ]+th.fsrw[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+46c5f50b[ ]+th.fsrw[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+70c5f50b[ ]+th.fsurd[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+76c5f50b[ ]+th.fsurd[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+50c5f50b[ ]+th.fsurw[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+56c5f50b[ ]+th.fsurw[ ]+a0,a1,a2,3 diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx.s b/gas/testsuite/gas/riscv/x-thead-fmemidx.s new file mode 100644 index 00000000000..0d70bb7e799 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx.s @@ -0,0 +1,17 @@ +target: + th.flrd a0, a1, a2, 0 + th.flrd a0, a1, a2, 3 + th.flrw a0, a1, a2, 0 + th.flrw a0, a1, a2, 3 + th.flurd a0, a1, a2, 0 + th.flurd a0, a1, a2, 3 + th.flurw a0, a1, a2, 0 + th.flurw a0, a1, a2, 3 + th.fsrd a0, a1, a2, 0 + th.fsrd a0, a1, a2, 3 + th.fsrw a0, a1, a2, 0 + th.fsrw a0, a1, a2, 3 + th.fsurd a0, a1, a2, 0 + th.fsurd a0, a1, a2, 3 + th.fsurw a0, a1, a2, 0 + th.fsurw a0, a1, a2, 3 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index b504ce019b6..ecba9f51c84 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2186,6 +2186,23 @@ #define MASK_TH_MVEQZ 0xfe00707f #define MATCH_TH_MVNEZ 0x4200100b #define MASK_TH_MVNEZ 0xfe00707f +/* Vendor-specific (T-Head) XTheadFMemIdx instructions. */ +#define MATCH_TH_FLRD 0x6000600b +#define MASK_TH_FLRD 0xf800707f +#define MATCH_TH_FLRW 0x4000600b +#define MASK_TH_FLRW 0xf800707f +#define MATCH_TH_FLURD 0x7000600b +#define MASK_TH_FLURD 0xf800707f +#define MATCH_TH_FLURW 0x5000600b +#define MASK_TH_FLURW 0xf800707f +#define MATCH_TH_FSRD 0x6000700b +#define MASK_TH_FSRD 0xf800707f +#define MATCH_TH_FSRW 0x4000700b +#define MASK_TH_FSRW 0xf800707f +#define MATCH_TH_FSURD 0x7000700b +#define MASK_TH_FSURD 0xf800707f +#define MATCH_TH_FSURW 0x5000700b +#define MASK_TH_FSURW 0xf800707f /* Vendor-specific (T-Head) XTheadMac instructions. */ #define MATCH_TH_MULA 0x2000100b #define MASK_TH_MULA 0xfe00707f @@ -2988,6 +3005,15 @@ DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL) /* Vendor-specific (T-Head) XTheadCondMov instructions. */ DECLARE_INSN(th_mveqz, MATCH_TH_MVEQZ, MASK_TH_MVEQZ) DECLARE_INSN(th_mvnez, MATCH_TH_MVNEZ, MASK_TH_MVNEZ) +/* Vendor-specific (T-Head) XTheadFMemIdx instructions. */ +DECLARE_INSN(th_flrd, MATCH_TH_FLRD, MASK_TH_FLRD) +DECLARE_INSN(th_flrw, MATCH_TH_FLRW, MASK_TH_FLRW) +DECLARE_INSN(th_flurd, MATCH_TH_FLURD, MASK_TH_FLURD) +DECLARE_INSN(th_flurw, MATCH_TH_FLURW, MASK_TH_FLURW) +DECLARE_INSN(th_fsrd, MATCH_TH_FSRD, MASK_TH_FSRD) +DECLARE_INSN(th_fsrw, MATCH_TH_FSRW, MASK_TH_FSRW) +DECLARE_INSN(th_fsurd, MATCH_TH_FSURD, MASK_TH_FSURD) +DECLARE_INSN(th_fsurw, MATCH_TH_FSURW, MASK_TH_FSURW) /* Vendor-specific (T-Head) XTheadMac instructions. */ DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA) DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 854269a9d98..1b7de3cb142 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -420,6 +420,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADBS, INSN_CLASS_XTHEADCMO, INSN_CLASS_XTHEADCONDMOV, + INSN_CLASS_XTHEADFMEMIDX, INSN_CLASS_XTHEADMAC, INSN_CLASS_XTHEADSYNC, }; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 5d5298923c8..6c1c4c9a1ad 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1871,6 +1871,16 @@ const struct riscv_opcode riscv_opcodes[] = {"th.mveqz", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVEQZ, MASK_TH_MVEQZ, match_opcode, 0}, {"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadFMemIdx instructions. */ +{"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLRD, MASK_TH_FLRD, match_opcode, 0}, +{"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLRW, MASK_TH_FLRW, match_opcode, 0}, +{"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, 0}, +{"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, 0}, +{"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSRD, MASK_TH_FSRD, match_opcode, 0}, +{"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSRW, MASK_TH_FSRW, match_opcode, 0}, +{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0}, +{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadMac instructions. */ {"th.mula", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA, MASK_TH_MULA, match_opcode, 0}, {"th.mulah", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAH, MASK_TH_MULAH, match_opcode, 0}, -- 2.37.2