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* [PATCH] opcodes: SH fix bank register disassemble.
@ 2022-09-14  2:44 Yoshinori Sato
  2022-09-22 11:41 ` Nick Clifton
  0 siblings, 1 reply; 2+ messages in thread
From: Yoshinori Sato @ 2022-09-14  2:44 UTC (permalink / raw)
  To: binutils; +Cc: Yoshinori Sato

Bit7 of LDC Rm,Rn_BANK and STC Rm_BANK,Rn is always 1.
Since it is not confirmed that this is 1 now,
it was outputting incorrect code as a correct instruction.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
 opcodes/sh-dis.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c
index 0e46cb6f4d9..6c8bd7b1cd7 100644
--- a/opcodes/sh-dis.c
+++ b/opcodes/sh-dis.c
@@ -645,6 +645,8 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
 	      rm = (nibs[n] & 0x3);
 	      break;
 	    case REG_B:
+	      if (!(nibs[n] & 0x08)) /* always 1*/
+		goto fail;
 	      rb = nibs[n] & 0x07;
 	      break;
 	    case SDT_REG_N:
-- 
2.30.2


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH] opcodes: SH fix bank register disassemble.
  2022-09-14  2:44 [PATCH] opcodes: SH fix bank register disassemble Yoshinori Sato
@ 2022-09-22 11:41 ` Nick Clifton
  0 siblings, 0 replies; 2+ messages in thread
From: Nick Clifton @ 2022-09-22 11:41 UTC (permalink / raw)
  To: Yoshinori Sato, binutils

Hi Yoshinori-san,

> Bit7 of LDC Rm,Rn_BANK and STC Rm_BANK,Rn is always 1.
> Since it is not confirmed that this is 1 now,
> it was outputting incorrect code as a correct instruction.

Thank you for bringing this to our attention.

I have gone ahead and applied your patch.

Cheers
   Nick


^ permalink raw reply	[flat|nested] 2+ messages in thread

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2022-09-14  2:44 [PATCH] opcodes: SH fix bank register disassemble Yoshinori Sato
2022-09-22 11:41 ` Nick Clifton

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