From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id C1B3A3835889 for ; Sat, 17 Sep 2022 10:03:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C1B3A3835889 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [49.77.98.63]) by APP-01 (Coremail) with SMTP id qwCowACHj49fmyVjSBQ_AA--.6872S2; Sat, 17 Sep 2022 18:03:13 +0800 (CST) From: shihua@iscas.ac.cn To: binutils@sourceware.org Cc: kito.cheng@sifive.com, vineetg@rivosinc.com, research_trasio@irq.a4lg.com, christoph.muellner@vrull.eu, nelson@rivosinc.com, palmer@dabbelt.com, jiawei@iscas.ac.cn, Liao Shihua Subject: [PATCH V2] RISC-V Implement Ztso extension Date: Sat, 17 Sep 2022 18:03:00 +0800 Message-Id: <20220917100300.1041-1-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.37.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:qwCowACHj49fmyVjSBQ_AA--.6872S2 X-Coremail-Antispam: 1UD129KBjvJXoWxtr4rJw43AF4Uur13WFyUWrg_yoWxXrW8pF s5CFWFkF95JF1xXFs3Xw4jgr43Jw4I9rWayry2k3y5A3s7X3yUXrykt3W5CFsxJF4kua4a 9ayrKry5u3yrAr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkS14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lw4CEc2x0rVAKj4xx MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr 0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0E wIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJV W8JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAI cVC2z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUOxhLUUUUU X-Originating-IP: [49.77.98.63] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiCgMMEWMlL-C2qgAAsR X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Liao Shihua This patch support ZTSO extension. It will turn on the tso flag for elf_flags once we have enabled Ztso extension. This is intended to implement v0.1 of the proposed specification which can be found in Chapter 25 of https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf. bfd\ChangeLog: * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data):Set TSO flag. * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for new instruction class. binutils\ChangeLog: * readelf.c (get_machine_flags):Set TSO flag. gas\ChangeLog: * config/tc-riscv.c (struct riscv_set_options):Set TSO flag. (riscv_set_tso):Set TSO flag. (riscv_set_arch):Set TSO flag. * testsuite/gas/riscv/attribute-015.d: New test. include\ChangeLog: * elf/riscv.h (EF_RISCV_TSO):Define TSO bit. * opcode/riscv.h (enum riscv_insn_class):Add Ztso's INSN CLASS. --- bfd/elfnn-riscv.c | 3 +++ bfd/elfxx-riscv.c | 5 +++++ binutils/readelf.c | 3 +++ gas/config/tc-riscv.c | 18 ++++++++++++++++++ gas/testsuite/gas/riscv/attribute-015.d | 6 ++++++ include/elf/riscv.h | 3 +++ include/opcode/riscv.h | 1 + 7 files changed, 39 insertions(+) create mode 100644 gas/testsuite/gas/riscv/attribute-015.d diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c index 0e0a0b09e24..3d2ddf4e651 100644 --- a/bfd/elfnn-riscv.c +++ b/bfd/elfnn-riscv.c @@ -3872,6 +3872,9 @@ _bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info) /* Allow linking RVC and non-RVC, and keep the RVC flag. */ elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_RVC; + /* Allow linking TSO and non-TSO, and keep the TSO flag. */ + elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_TSO; + return true; fail: diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index e03b312a381..a0630d4c183 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1204,6 +1204,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zvl16384b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32768b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl65536b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ztso", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2376,6 +2377,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, || riscv_subset_supports (rps, "zve64d") || riscv_subset_supports (rps, "zve64f") || riscv_subset_supports (rps, "zve32f")); + case INSN_CLASS_ZTSO: + return riscv_subset_supports (rps, "ztso"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2503,6 +2506,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("v' or `zve64x' or `zve32x"); case INSN_CLASS_ZVEF: return _("v' or `zve64d' or `zve64f' or `zve32f"); + case INSN_CLASS_ZTSO: + return "ztso"; case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/binutils/readelf.c b/binutils/readelf.c index cafba9a4f56..b1dbcad06f5 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -4079,6 +4079,9 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine) if (e_flags & EF_RISCV_RVE) strcat (buf, ", RVE"); + if (e_flags & EF_RISCV_TSO) + strcat (buf, ", TSO"); + switch (e_flags & EF_RISCV_FLOAT_ABI) { case EF_RISCV_FLOAT_ABI_SOFT: diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 2f5ee18e451..8806b455d1b 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -234,6 +234,7 @@ struct riscv_set_options int relax; /* Emit relocs the linker is allowed to relax. */ int arch_attr; /* Emit architecture and privileged elf attributes. */ int csr_check; /* Enable the CSR checking. */ + int tso; /* Use tso model. */ }; static struct riscv_set_options riscv_opts = @@ -243,6 +244,7 @@ static struct riscv_set_options riscv_opts = 1, /* relax */ DEFAULT_RISCV_ATTR, /* arch_attr */ 0, /* csr_check */ + 0, /* tso */ }; /* Enable or disable the rvc flags for riscv_opts. Turn on the rvc flag @@ -257,6 +259,18 @@ riscv_set_rvc (bool rvc_value) riscv_opts.rvc = rvc_value; } +/* Enable or disable the tso flags for riscv_opts. Turn on the tso flag + for elf_flags once we have enabled ztso extension. */ + +static void +riscv_set_tso (bool tso_value) +{ + if (tso_value) + elf_flags |= EF_RISCV_TSO; + + riscv_opts.tso = tso_value; +} + /* This linked list records all enabled extensions, which are parsed from the architecture string. The architecture string can be set by the -march option, the elf architecture attributes, and the --with-arch @@ -307,6 +321,10 @@ riscv_set_arch (const char *s) riscv_set_rvc (false); if (riscv_subset_supports (&riscv_rps_as, "c")) riscv_set_rvc (true); + + riscv_set_tso (false); + if (riscv_subset_supports (&riscv_rps_as, "ztso")) + riscv_set_tso (true); } /* Indicate -mabi option is explictly set. */ diff --git a/gas/testsuite/gas/riscv/attribute-015.d b/gas/testsuite/gas/riscv/attribute-015.d new file mode 100644 index 00000000000..73fc85b97ab --- /dev/null +++ b/gas/testsuite/gas/riscv/attribute-015.d @@ -0,0 +1,6 @@ +#as: -march=rv32i_ztso -march-attr +#readelf: -A +#source: empty.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv32i2p0_ztso0p1" diff --git a/include/elf/riscv.h b/include/elf/riscv.h index 9b3ea376ff3..d7b5c09d5c3 100644 --- a/include/elf/riscv.h +++ b/include/elf/riscv.h @@ -121,6 +121,9 @@ END_RELOC_NUMBERS (R_RISCV_max) /* RISC-V specific values for st_other. */ #define STO_RISCV_VARIANT_CC 0x80 +/* File uses the TSO model. */ +#define EF_RISCV_TSO 0x0010 + /* Additional section types. */ #define SHT_RISCV_ATTRIBUTES 0x70000003 /* Section holds attributes. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f1dabeaab8e..173b98d98be 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -398,6 +398,7 @@ enum riscv_insn_class INSN_CLASS_ZICBOP, INSN_CLASS_ZICBOZ, INSN_CLASS_H, + INSN_CLASS_ZTSO, }; /* This structure holds information for a particular instruction. */ -- 2.17.1