From: Christoph Muellner <christoph.muellner@vrull.eu>
To: binutils@sourceware.org, Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Cooper Qu <cooper.qu@linux.alibaba.com>,
Lifang Xia <lifang_xia@linux.alibaba.com>,
Yunhai Shang <yunhai@linux.alibaba.com>,
Zhiwei Liu <zhiwei_liu@linux.alibaba.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH v2 00/11] Add support for the T-Head vendor extensions
Date: Sun, 18 Sep 2022 09:23:45 +0200 [thread overview]
Message-ID: <20220918072356.2496130-1-christoph.muellner@vrull.eu> (raw)
From: Christoph Müllner <christoph.muellner@vrull.eu>
This series introduces support for the T-Head vendor extensions,
which are implemented e.g. in the XuanTie C906 and XuanTie C910
processors:
* XTheadBa
* XTheadBb
* XTheadBs
* XTheadCmo
* XTheadCondMov
* XTheadFMemIdx
* XTheadMac
* XTheadMemIdx
* XTheadMemPair
* XTheadSync
The xthead* extensions are documented here:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf
The "th." instruction prefix prevents future conflicts with standard
extensions and has been documentented in the RISC-V toolchain conventions:
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
The goal of this patchset is to provide access to these instructions
so that compilers/users can optimize SW accordingly.
Note, that the T-Head vendor extensions do not contain all
vendor-specific functionality of the T-Head SoCs (e.g. no vendor-specific
CSRs are included). Instead the extensions cover coherent functionality,
that is exposed to S and U mode.
The patchset attempts to minimize code changes in generic/infrastructure code.
All patches in this series come with tests to avoid future regressions.
v2:
* Drop -mcpu= support patches
* Add extensions to riscv_multi_subset_supports_ext
* Rename operand 'L' to 'Xl'
Christoph Müllner (11):
RISC-V: Add generic support for vendor extensions
RISC-V: Add T-Head CMO vendor extension
RISC-V: Add T-Head SYNC vendor extension
RISC-V: Add support for arbitrary immediate encoding formats
RISC-V: Add T-Head Bitmanip vendor extension
RISC-V: Add T-Head CondMov vendor extension
RISC-V: Add T-Head MAC vendor extension
RISC-V: Add T-Head FMemIdx vendor extension
RISC-V: Add T-Head MemIdx vendor extension
RISC-V: Add support for literal instruction arguments
RISC-V: Add T-Head MemPair vendor extension
bfd/elfxx-riscv.c | 59 +++-
gas/config/tc-riscv.c | 84 +++++
gas/doc/c-riscv.texi | 63 ++++
gas/testsuite/gas/riscv/x-thead-ba-fail.d | 3 +
gas/testsuite/gas/riscv/x-thead-ba-fail.l | 3 +
gas/testsuite/gas/riscv/x-thead-ba-fail.s | 3 +
gas/testsuite/gas/riscv/x-thead-ba.d | 13 +
gas/testsuite/gas/riscv/x-thead-ba.s | 6 +
gas/testsuite/gas/riscv/x-thead-bb-fail.d | 3 +
gas/testsuite/gas/riscv/x-thead-bb-fail.l | 7 +
gas/testsuite/gas/riscv/x-thead-bb-fail.s | 7 +
gas/testsuite/gas/riscv/x-thead-bb.d | 30 ++
gas/testsuite/gas/riscv/x-thead-bb.s | 22 ++
gas/testsuite/gas/riscv/x-thead-bs-fail.d | 3 +
gas/testsuite/gas/riscv/x-thead-bs-fail.l | 3 +
gas/testsuite/gas/riscv/x-thead-bs-fail.s | 3 +
gas/testsuite/gas/riscv/x-thead-bs.d | 14 +
gas/testsuite/gas/riscv/x-thead-bs.s | 6 +
gas/testsuite/gas/riscv/x-thead-cmo-fail.d | 3 +
gas/testsuite/gas/riscv/x-thead-cmo-fail.l | 22 ++
gas/testsuite/gas/riscv/x-thead-cmo-fail.s | 22 ++
gas/testsuite/gas/riscv/x-thead-cmo.d | 30 ++
gas/testsuite/gas/riscv/x-thead-cmo.s | 22 ++
gas/testsuite/gas/riscv/x-thead-condmov.d | 11 +
gas/testsuite/gas/riscv/x-thead-condmov.s | 3 +
.../gas/riscv/x-thead-fmemidx-fail.d | 3 +
.../gas/riscv/x-thead-fmemidx-fail.l | 18 +
.../gas/riscv/x-thead-fmemidx-fail.s | 17 +
gas/testsuite/gas/riscv/x-thead-fmemidx.d | 25 ++
gas/testsuite/gas/riscv/x-thead-fmemidx.s | 17 +
gas/testsuite/gas/riscv/x-thead-mac.d | 15 +
gas/testsuite/gas/riscv/x-thead-mac.s | 7 +
gas/testsuite/gas/riscv/x-thead-memidx-fail.d | 3 +
gas/testsuite/gas/riscv/x-thead-memidx-fail.l | 14 +
gas/testsuite/gas/riscv/x-thead-memidx-fail.s | 14 +
gas/testsuite/gas/riscv/x-thead-memidx.d | 53 +++
gas/testsuite/gas/riscv/x-thead-memidx.s | 48 +++
.../gas/riscv/x-thead-mempair-fail.d | 3 +
.../gas/riscv/x-thead-mempair-fail.l | 30 ++
.../gas/riscv/x-thead-mempair-fail.s | 30 ++
gas/testsuite/gas/riscv/x-thead-mempair.d | 14 +
gas/testsuite/gas/riscv/x-thead-mempair.s | 6 +
gas/testsuite/gas/riscv/x-thead-sync-fail.d | 3 +
gas/testsuite/gas/riscv/x-thead-sync-fail.l | 6 +
gas/testsuite/gas/riscv/x-thead-sync-fail.s | 6 +
gas/testsuite/gas/riscv/x-thead-sync.d | 14 +
gas/testsuite/gas/riscv/x-thead-sync.s | 6 +
include/opcode/riscv-opc.h | 326 ++++++++++++++++++
include/opcode/riscv.h | 27 ++
opcodes/riscv-dis.c | 43 +++
opcodes/riscv-opc.c | 155 +++++++++
51 files changed, 1346 insertions(+), 2 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.l
create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.l
create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.l
create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.l
create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l
create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.l
create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.l
create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.l
create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.s
create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.d
create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.s
--
2.37.2
next reply other threads:[~2022-09-18 7:24 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-18 7:23 Christoph Muellner [this message]
2022-09-18 7:23 ` [PATCH v2 01/11] RISC-V: Add generic support for " Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 02/11] RISC-V: Add T-Head CMO vendor extension Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 03/11] RISC-V: Add T-Head SYNC " Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 04/11] RISC-V: Add support for arbitrary immediate encoding formats Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 05/11] RISC-V: Add T-Head Bitmanip vendor extension Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 06/11] RISC-V: Add T-Head CondMov " Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 07/11] RISC-V: Add T-Head MAC " Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 08/11] RISC-V: Add T-Head FMemIdx " Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 09/11] RISC-V: Add T-Head MemIdx " Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 10/11] RISC-V: Add support for literal instruction arguments Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 11/11] RISC-V: Add T-Head MemPair vendor extension Christoph Muellner
2022-09-22 13:55 ` [PATCH v2 00/11] Add support for the T-Head vendor extensions Nelson Chu
2022-09-22 14:06 ` Christoph Müllner
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