From: Christoph Müllner <christoph.muellner@vrull.eu> This series introduces support for the T-Head vendor extensions, which are implemented e.g. in the XuanTie C906 and XuanTie C910 processors: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSync The xthead* extensions are documented here: https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf The "th." instruction prefix prevents future conflicts with standard extensions and has been documentented in the RISC-V toolchain conventions: https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 The goal of this patchset is to provide access to these instructions so that compilers/users can optimize SW accordingly. Note, that the T-Head vendor extensions do not contain all vendor-specific functionality of the T-Head SoCs (e.g. no vendor-specific CSRs are included). Instead the extensions cover coherent functionality, that is exposed to S and U mode. The patchset attempts to minimize code changes in generic/infrastructure code. All patches in this series come with tests to avoid future regressions. v2: * Drop -mcpu= support patches * Add extensions to riscv_multi_subset_supports_ext * Rename operand 'L' to 'Xl' Christoph Müllner (11): RISC-V: Add generic support for vendor extensions RISC-V: Add T-Head CMO vendor extension RISC-V: Add T-Head SYNC vendor extension RISC-V: Add support for arbitrary immediate encoding formats RISC-V: Add T-Head Bitmanip vendor extension RISC-V: Add T-Head CondMov vendor extension RISC-V: Add T-Head MAC vendor extension RISC-V: Add T-Head FMemIdx vendor extension RISC-V: Add T-Head MemIdx vendor extension RISC-V: Add support for literal instruction arguments RISC-V: Add T-Head MemPair vendor extension bfd/elfxx-riscv.c | 59 +++- gas/config/tc-riscv.c | 84 +++++ gas/doc/c-riscv.texi | 63 ++++ gas/testsuite/gas/riscv/x-thead-ba-fail.d | 3 + gas/testsuite/gas/riscv/x-thead-ba-fail.l | 3 + gas/testsuite/gas/riscv/x-thead-ba-fail.s | 3 + gas/testsuite/gas/riscv/x-thead-ba.d | 13 + gas/testsuite/gas/riscv/x-thead-ba.s | 6 + gas/testsuite/gas/riscv/x-thead-bb-fail.d | 3 + gas/testsuite/gas/riscv/x-thead-bb-fail.l | 7 + gas/testsuite/gas/riscv/x-thead-bb-fail.s | 7 + gas/testsuite/gas/riscv/x-thead-bb.d | 30 ++ gas/testsuite/gas/riscv/x-thead-bb.s | 22 ++ gas/testsuite/gas/riscv/x-thead-bs-fail.d | 3 + gas/testsuite/gas/riscv/x-thead-bs-fail.l | 3 + gas/testsuite/gas/riscv/x-thead-bs-fail.s | 3 + gas/testsuite/gas/riscv/x-thead-bs.d | 14 + gas/testsuite/gas/riscv/x-thead-bs.s | 6 + gas/testsuite/gas/riscv/x-thead-cmo-fail.d | 3 + gas/testsuite/gas/riscv/x-thead-cmo-fail.l | 22 ++ gas/testsuite/gas/riscv/x-thead-cmo-fail.s | 22 ++ gas/testsuite/gas/riscv/x-thead-cmo.d | 30 ++ gas/testsuite/gas/riscv/x-thead-cmo.s | 22 ++ gas/testsuite/gas/riscv/x-thead-condmov.d | 11 + gas/testsuite/gas/riscv/x-thead-condmov.s | 3 + .../gas/riscv/x-thead-fmemidx-fail.d | 3 + .../gas/riscv/x-thead-fmemidx-fail.l | 18 + .../gas/riscv/x-thead-fmemidx-fail.s | 17 + gas/testsuite/gas/riscv/x-thead-fmemidx.d | 25 ++ gas/testsuite/gas/riscv/x-thead-fmemidx.s | 17 + gas/testsuite/gas/riscv/x-thead-mac.d | 15 + gas/testsuite/gas/riscv/x-thead-mac.s | 7 + gas/testsuite/gas/riscv/x-thead-memidx-fail.d | 3 + gas/testsuite/gas/riscv/x-thead-memidx-fail.l | 14 + gas/testsuite/gas/riscv/x-thead-memidx-fail.s | 14 + gas/testsuite/gas/riscv/x-thead-memidx.d | 53 +++ gas/testsuite/gas/riscv/x-thead-memidx.s | 48 +++ .../gas/riscv/x-thead-mempair-fail.d | 3 + .../gas/riscv/x-thead-mempair-fail.l | 30 ++ .../gas/riscv/x-thead-mempair-fail.s | 30 ++ gas/testsuite/gas/riscv/x-thead-mempair.d | 14 + gas/testsuite/gas/riscv/x-thead-mempair.s | 6 + gas/testsuite/gas/riscv/x-thead-sync-fail.d | 3 + gas/testsuite/gas/riscv/x-thead-sync-fail.l | 6 + gas/testsuite/gas/riscv/x-thead-sync-fail.s | 6 + gas/testsuite/gas/riscv/x-thead-sync.d | 14 + gas/testsuite/gas/riscv/x-thead-sync.s | 6 + include/opcode/riscv-opc.h | 326 ++++++++++++++++++ include/opcode/riscv.h | 27 ++ opcodes/riscv-dis.c | 43 +++ opcodes/riscv-opc.c | 155 +++++++++ 51 files changed, 1346 insertions(+), 2 deletions(-) create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.d create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.s create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.d create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.s create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.d create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.s create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.d create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.s create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.d create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.s create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.d create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.s create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.d create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.s create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.d create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.s create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.d create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.s create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.d create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.s -- 2.37.2
From: Christoph Müllner <christoph.muellner@vrull.eu> This patch introduces changes that allow the integration of vendor ISA extensions: * Define a list of vendor extensions (riscv_supported_vendor_x_ext) where vendor extensions can be added * Introduce a section with a table in the documentation where vendor extensions can be added To add a vendor extension that consists of instructions only, the following things need to be done: * Add the extension to the riscv_supported_vendor_x_ext list * Add lookup entry in riscv_multi_subset_supports * Documenting the extension in c-riscv.texti * Add test cases for all instructions * Add MATCH*/MASK* constants and DECLARE_INSN() for all instructions * Add new instruction class to enum riscv_insn_class * Define the instructions in riscv_opcodes * Additional changes if necessary (depending on the instructions) Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- bfd/elfxx-riscv.c | 9 +++++++-- gas/doc/c-riscv.texi | 14 ++++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index e03b312a381..1d891dee610 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1221,12 +1221,18 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] = {NULL, 0, 0, 0, 0} }; +static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = +{ + {NULL, 0, 0, 0, 0} +}; + const struct riscv_supported_ext *riscv_all_supported_ext[] = { riscv_supported_std_ext, riscv_supported_std_z_ext, riscv_supported_std_s_ext, riscv_supported_std_zxm_ext, + riscv_supported_vendor_x_ext, NULL }; @@ -1482,8 +1488,7 @@ riscv_get_default_ext_version (enum riscv_spec_class *default_isa_spec, case RV_ISA_CLASS_ZXM: table = riscv_supported_std_zxm_ext; break; case RV_ISA_CLASS_Z: table = riscv_supported_std_z_ext; break; case RV_ISA_CLASS_S: table = riscv_supported_std_s_ext; break; - case RV_ISA_CLASS_X: - break; + case RV_ISA_CLASS_X: table = riscv_supported_vendor_x_ext; break; default: table = riscv_supported_std_ext; } diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 21d867e9cf0..30afd200b7d 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -20,6 +20,7 @@ * RISC-V-Modifiers:: RISC-V Assembler Modifiers * RISC-V-Formats:: RISC-V Instruction Formats * RISC-V-ATTRIBUTE:: RISC-V Object Attribute +* RISC-V-CustomExts:: RISC-V Custom (Vendor-Defined) Extensions @end menu @node RISC-V-Options @@ -692,3 +693,16 @@ the privileged specification. It will report errors if object files of different privileged specification versions are merged. @end table + +@node RISC-V-CustomExts +@section RISC-V Custom (Vendor-Defined) Extensions +@cindex custom (vendor-defined) extensions, RISC-V +@cindex RISC-V custom (vendor-defined) extensions + +The following table lists the custom (vendor-defined) RISC-V +extensions supported and provides the location of their +publicly-released documentation: + +@table @r + +@end table -- 2.37.2
From: Christoph Müllner <christoph.muellner@vrull.eu> T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadCmo extension, a collection of T-Head specific cache management operations. The 'th' prefix and the "XTheadCmo" extension are documented in a PR for the RISC-V toolchain conventions ([1]). In total XTheadCmo introduces the following 21 instructions: * DCACHE.{C,CI,I}ALL * DCACHE.{C,CI,I}{PA,VA,SW} rs1 * DCACHE.C{PAL1,VAL1} rs1 * ICACHE.I{ALL,ALLS} * ICACHE.I{PA,VA} rs1 * L2CACHE.{C,CI,I}ALL Contrary to Zicbom, the XTheadCmo instructions don't have a constant displacement, therefore we have a different syntax for the arguments. To clarify this is intended behaviour, there is a set of negative test for Zicbom-style arguments in x-thead-cmo-fail.s. [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 v2: - Add missing DECLARE_INSN() list - Fix ordering Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- bfd/elfxx-riscv.c | 5 ++ gas/doc/c-riscv.texi | 4 ++ gas/testsuite/gas/riscv/x-thead-cmo-fail.d | 3 + gas/testsuite/gas/riscv/x-thead-cmo-fail.l | 22 ++++++++ gas/testsuite/gas/riscv/x-thead-cmo-fail.s | 22 ++++++++ gas/testsuite/gas/riscv/x-thead-cmo.d | 30 ++++++++++ gas/testsuite/gas/riscv/x-thead-cmo.s | 22 ++++++++ include/opcode/riscv-opc.h | 65 ++++++++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 25 +++++++++ 10 files changed, 199 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.d create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 1d891dee610..62e45d21d9a 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1223,6 +1223,7 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] = static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = { + {"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2385,6 +2386,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: return riscv_subset_supports (rps, "h"); + case INSN_CLASS_XTHEADCMO: + return riscv_subset_supports (rps, "xtheadcmo"); default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); @@ -2512,6 +2515,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "svinval"; case INSN_CLASS_H: return _("h"); + case INSN_CLASS_XTHEADCMO: + return "xtheadcmo"; default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 30afd200b7d..10e9429c83e 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -704,5 +704,9 @@ extensions supported and provides the location of their publicly-released documentation: @table @r +@item XTheadCmo +The XTheadCmo extension provides instructions for cache management. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. @end table diff --git a/gas/testsuite/gas/riscv/x-thead-cmo-fail.d b/gas/testsuite/gas/riscv/x-thead-cmo-fail.d new file mode 100644 index 00000000000..de794ea5837 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-cmo-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64i_xtheadcmo +#source: x-thead-cmo-fail.s +#error_output: x-thead-cmo-fail.l diff --git a/gas/testsuite/gas/riscv/x-thead-cmo-fail.l b/gas/testsuite/gas/riscv/x-thead-cmo-fail.l new file mode 100644 index 00000000000..4381fe19a99 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-cmo-fail.l @@ -0,0 +1,22 @@ +.*: Assembler messages: +.*: Error: illegal operands `th.dcache.call x1' +.*: Error: illegal operands `th.dcache.ciall x1' +.*: Error: illegal operands `th.dcache.iall x1' +.*: Error: illegal operands `th.dcache.cpa 0\(x1\)' +.*: Error: illegal operands `th.dcache.cipa 0\(x1\)' +.*: Error: illegal operands `th.dcache.ipa 0\(x1\)' +.*: Error: illegal operands `th.dcache.cva 0\(x1\)' +.*: Error: illegal operands `th.dcache.civa 0\(x1\)' +.*: Error: illegal operands `th.dcache.iva 0\(x1\)' +.*: Error: illegal operands `th.dcache.csw 0\(x1\)' +.*: Error: illegal operands `th.dcache.cisw 0\(x1\)' +.*: Error: illegal operands `th.dcache.isw 0\(x1\)' +.*: Error: illegal operands `th.dcache.cpal1 0\(x1\)' +.*: Error: illegal operands `th.dcache.cval1 0\(x1\)' +.*: Error: illegal operands `th.icache.iall x1' +.*: Error: illegal operands `th.icache.ialls x1' +.*: Error: illegal operands `th.icache.ipa 0\(x1\)' +.*: Error: illegal operands `th.icache.iva 0\(x1\)' +.*: Error: illegal operands `th.l2cache.call x1' +.*: Error: illegal operands `th.l2cache.ciall x1' +.*: Error: illegal operands `th.l2cache.iall x1' diff --git a/gas/testsuite/gas/riscv/x-thead-cmo-fail.s b/gas/testsuite/gas/riscv/x-thead-cmo-fail.s new file mode 100644 index 00000000000..591d982eae5 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-cmo-fail.s @@ -0,0 +1,22 @@ +target: + th.dcache.call x1 + th.dcache.ciall x1 + th.dcache.iall x1 + th.dcache.cpa 0(x1) + th.dcache.cipa 0(x1) + th.dcache.ipa 0(x1) + th.dcache.cva 0(x1) + th.dcache.civa 0(x1) + th.dcache.iva 0(x1) + th.dcache.csw 0(x1) + th.dcache.cisw 0(x1) + th.dcache.isw 0(x1) + th.dcache.cpal1 0(x1) + th.dcache.cval1 0(x1) + th.icache.iall x1 + th.icache.ialls x1 + th.icache.ipa 0(x1) + th.icache.iva 0(x1) + th.l2cache.call x1 + th.l2cache.ciall x1 + th.l2cache.iall x1 diff --git a/gas/testsuite/gas/riscv/x-thead-cmo.d b/gas/testsuite/gas/riscv/x-thead-cmo.d new file mode 100644 index 00000000000..f482ddcbc28 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-cmo.d @@ -0,0 +1,30 @@ +#as: -march=rv64i_xtheadcmo +#source: x-thead-cmo.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+0010000b[ ]+th.dcache.call +[ ]+[0-9a-f]+:[ ]+0030000b[ ]+th.dcache.ciall +[ ]+[0-9a-f]+:[ ]+0020000b[ ]+th.dcache.iall +[ ]+[0-9a-f]+:[ ]+0295000b[ ]+th.dcache.cpa[ ]+a0 +[ ]+[0-9a-f]+:[ ]+02b5800b[ ]+th.dcache.cipa[ ]+a1 +[ ]+[0-9a-f]+:[ ]+02a6000b[ ]+th.dcache.ipa[ ]+a2 +[ ]+[0-9a-f]+:[ ]+0256800b[ ]+th.dcache.cva[ ]+a3 +[ ]+[0-9a-f]+:[ ]+0277000b[ ]+th.dcache.civa[ ]+a4 +[ ]+[0-9a-f]+:[ ]+0267800b[ ]+th.dcache.iva[ ]+a5 +[ ]+[0-9a-f]+:[ ]+0218000b[ ]+th.dcache.csw[ ]+a6 +[ ]+[0-9a-f]+:[ ]+0238800b[ ]+th.dcache.cisw[ ]+a7 +[ ]+[0-9a-f]+:[ ]+0222800b[ ]+th.dcache.isw[ ]+t0 +[ ]+[0-9a-f]+:[ ]+0283000b[ ]+th.dcache.cpal1[ ]+t1 +[ ]+[0-9a-f]+:[ ]+0243800b[ ]+th.dcache.cval1[ ]+t2 +[ ]+[0-9a-f]+:[ ]+0100000b[ ]+th.icache.iall +[ ]+[0-9a-f]+:[ ]+0110000b[ ]+th.icache.ialls +[ ]+[0-9a-f]+:[ ]+038e000b[ ]+th.icache.ipa[ ]+t3 +[ ]+[0-9a-f]+:[ ]+030e800b[ ]+th.icache.iva[ ]+t4 +[ ]+[0-9a-f]+:[ ]+0150000b[ ]+th.l2cache.call +[ ]+[0-9a-f]+:[ ]+0170000b[ ]+th.l2cache.ciall +[ ]+[0-9a-f]+:[ ]+0160000b[ ]+th.l2cache.iall diff --git a/gas/testsuite/gas/riscv/x-thead-cmo.s b/gas/testsuite/gas/riscv/x-thead-cmo.s new file mode 100644 index 00000000000..2a4b54a941b --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-cmo.s @@ -0,0 +1,22 @@ +target: + th.dcache.call + th.dcache.ciall + th.dcache.iall + th.dcache.cpa a0 + th.dcache.cipa a1 + th.dcache.ipa a2 + th.dcache.cva a3 + th.dcache.civa a4 + th.dcache.iva a5 + th.dcache.csw a6 + th.dcache.cisw a7 + th.dcache.isw t0 + th.dcache.cpal1 t1 + th.dcache.cval1 t2 + th.icache.iall + th.icache.ialls + th.icache.ipa t3 + th.icache.iva t4 + th.l2cache.call + th.l2cache.ciall + th.l2cache.iall diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 88b8d7ff595..53b1c224518 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2113,6 +2113,49 @@ #define MASK_CBO_INVAL 0xfff07fff #define MATCH_CBO_ZERO 0x40200f #define MASK_CBO_ZERO 0xfff07fff +/* Vendor-specific (T-Head) XTheadCmo instructions. */ +#define MATCH_TH_DCACHE_CALL 0x0010000b +#define MASK_TH_DCACHE_CALL 0xffffffff +#define MATCH_TH_DCACHE_CIALL 0x0030000b +#define MASK_TH_DCACHE_CIALL 0xffffffff +#define MATCH_TH_DCACHE_IALL 0x0020000b +#define MASK_TH_DCACHE_IALL 0xffffffff +#define MATCH_TH_DCACHE_CPA 0x0290000b +#define MASK_TH_DCACHE_CPA 0xfff07fff +#define MATCH_TH_DCACHE_CIPA 0x02b0000b +#define MASK_TH_DCACHE_CIPA 0xfff07fff +#define MATCH_TH_DCACHE_IPA 0x02a0000b +#define MASK_TH_DCACHE_IPA 0xfff07fff +#define MATCH_TH_DCACHE_CVA 0x0250000b +#define MASK_TH_DCACHE_CVA 0xfff07fff +#define MATCH_TH_DCACHE_CIVA 0x0270000b +#define MASK_TH_DCACHE_CIVA 0xfff07fff +#define MATCH_TH_DCACHE_IVA 0x0260000b +#define MASK_TH_DCACHE_IVA 0xfff07fff +#define MATCH_TH_DCACHE_CSW 0x0210000b +#define MASK_TH_DCACHE_CSW 0xfff07fff +#define MATCH_TH_DCACHE_CISW 0x0230000b +#define MASK_TH_DCACHE_CISW 0xfff07fff +#define MATCH_TH_DCACHE_ISW 0x0220000b +#define MASK_TH_DCACHE_ISW 0xfff07fff +#define MATCH_TH_DCACHE_CPAL1 0x0280000b +#define MASK_TH_DCACHE_CPAL1 0xfff07fff +#define MATCH_TH_DCACHE_CVAL1 0x0240000b +#define MASK_TH_DCACHE_CVAL1 0xfff07fff +#define MATCH_TH_ICACHE_IALL 0x0100000b +#define MASK_TH_ICACHE_IALL 0xffffffff +#define MATCH_TH_ICACHE_IALLS 0x0110000b +#define MASK_TH_ICACHE_IALLS 0xffffffff +#define MATCH_TH_ICACHE_IPA 0x0380000b +#define MASK_TH_ICACHE_IPA 0xfff07fff +#define MATCH_TH_ICACHE_IVA 0x0300000b +#define MASK_TH_ICACHE_IVA 0xfff07fff +#define MATCH_TH_L2CACHE_CALL 0x0150000b +#define MASK_TH_L2CACHE_CALL 0xffffffff +#define MATCH_TH_L2CACHE_CIALL 0x0170000b +#define MASK_TH_L2CACHE_CIALL 0xffffffff +#define MATCH_TH_L2CACHE_IALL 0x0160000b +#define MASK_TH_L2CACHE_IALL 0xffffffff /* Unprivileged Counter/Timers CSR addresses. */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 @@ -2852,6 +2895,28 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN); DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH); DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL); DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO); +/* Vendor-specific (T-Head) XTheadCmo instructions. */ +DECLARE_INSN(th_dcache_call, MATCH_TH_DCACHE_CALL, MASK_TH_DCACHE_CALL) +DECLARE_INSN(th_dcache_ciall, MATCH_TH_DCACHE_CIALL, MASK_TH_DCACHE_CIALL) +DECLARE_INSN(th_dcache_iall, MATCH_TH_DCACHE_IALL, MASK_TH_DCACHE_IALL) +DECLARE_INSN(th_dcache_cpa, MATCH_TH_DCACHE_CPA, MASK_TH_DCACHE_CPA) +DECLARE_INSN(th_dcache_cipa, MATCH_TH_DCACHE_CIPA, MASK_TH_DCACHE_CIPA) +DECLARE_INSN(th_dcache_ipa, MATCH_TH_DCACHE_IPA, MASK_TH_DCACHE_IPA) +DECLARE_INSN(th_dcache_cva, MATCH_TH_DCACHE_CVA, MASK_TH_DCACHE_CVA) +DECLARE_INSN(th_dcache_civa, MATCH_TH_DCACHE_CIVA, MASK_TH_DCACHE_CIVA) +DECLARE_INSN(th_dcache_iva, MATCH_TH_DCACHE_IVA, MASK_TH_DCACHE_IVA) +DECLARE_INSN(th_dcache_csw, MATCH_TH_DCACHE_CSW, MASK_TH_DCACHE_CSW) +DECLARE_INSN(th_dcache_cisw, MATCH_TH_DCACHE_CISW, MASK_TH_DCACHE_CISW) +DECLARE_INSN(th_dcache_isw, MATCH_TH_DCACHE_ISW, MASK_TH_DCACHE_ISW) +DECLARE_INSN(th_dcache_cpal1, MATCH_TH_DCACHE_CPAL1, MASK_TH_DCACHE_CPAL1) +DECLARE_INSN(th_dcache_cval1, MATCH_TH_DCACHE_CVAL1, MASK_TH_DCACHE_CVAL1) +DECLARE_INSN(th_icache_iall, MATCH_TH_ICACHE_IALL, MASK_TH_ICACHE_IALL) +DECLARE_INSN(th_icache_ialls, MATCH_TH_ICACHE_IALLS, MASK_TH_ICACHE_IALLS) +DECLARE_INSN(th_icache_ipa, MATCH_TH_ICACHE_IPA, MASK_TH_ICACHE_IPA) +DECLARE_INSN(th_icache_iva, MATCH_TH_ICACHE_IVA, MASK_TH_ICACHE_IVA) +DECLARE_INSN(th_l2cache_call, MATCH_TH_L2CACHE_CALL, MASK_TH_L2CACHE_CALL) +DECLARE_INSN(th_l2cache_ciall, MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL) +DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL) #endif /* DECLARE_INSN */ #ifdef DECLARE_CSR /* Unprivileged Counter/Timers CSRs. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f1dabeaab8e..d36983140a2 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -398,6 +398,7 @@ enum riscv_insn_class INSN_CLASS_ZICBOP, INSN_CLASS_ZICBOZ, INSN_CLASS_H, + INSN_CLASS_XTHEADCMO, }; /* This structure holds information for a particular instruction. */ diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 79be78eb367..bf073f20e71 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1825,6 +1825,31 @@ const struct riscv_opcode riscv_opcodes[] = {"hsv.w", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE }, {"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE }, +/* Vendor-specific (T-Head) XTheadCmo instructions. */ +{"th.dcache.call", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_DCACHE_CALL, MASK_TH_DCACHE_CALL, match_opcode, 0}, +{"th.dcache.ciall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_DCACHE_CIALL, MASK_TH_DCACHE_CIALL, match_opcode, 0}, +{"th.dcache.iall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_DCACHE_IALL, MASK_TH_DCACHE_IALL, match_opcode, 0}, +{"th.dcache.cpa", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CPA, MASK_TH_DCACHE_CPA, match_opcode, 0}, +{"th.dcache.cipa", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CIPA, MASK_TH_DCACHE_CIPA, match_opcode, 0}, +{"th.dcache.ipa", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_IPA, MASK_TH_DCACHE_IPA, match_opcode, 0}, +{"th.dcache.cva", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CVA, MASK_TH_DCACHE_CVA, match_opcode, 0}, +{"th.dcache.civa", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CIVA, MASK_TH_DCACHE_CIVA, match_opcode, 0}, +{"th.dcache.iva", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_IVA, MASK_TH_DCACHE_IVA, match_opcode, 0}, +{"th.dcache.csw", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CSW, MASK_TH_DCACHE_CSW, match_opcode, 0}, +{"th.dcache.cisw", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CISW, MASK_TH_DCACHE_CISW, match_opcode, 0}, +{"th.dcache.isw", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_ISW, MASK_TH_DCACHE_ISW, match_opcode, 0}, +{"th.dcache.cpal1", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CPAL1, MASK_TH_DCACHE_CPAL1, match_opcode, 0}, +{"th.dcache.cval1", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CVAL1, MASK_TH_DCACHE_CVAL1, match_opcode, 0}, + +{"th.icache.iall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_ICACHE_IALL, MASK_TH_ICACHE_IALL, match_opcode, 0}, +{"th.icache.ialls", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_ICACHE_IALLS, MASK_TH_ICACHE_IALLS, match_opcode, 0}, +{"th.icache.ipa", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_ICACHE_IPA, MASK_TH_ICACHE_IPA, match_opcode, 0}, +{"th.icache.iva", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_ICACHE_IVA, MASK_TH_ICACHE_IVA, match_opcode, 0}, + +{"th.l2cache.call", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_L2CACHE_CALL, MASK_TH_L2CACHE_CALL, match_opcode, 0}, +{"th.l2cache.ciall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL, match_opcode, 0}, +{"th.l2cache.iall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL, match_opcode, 0}, + /* Terminate the list. */ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} }; -- 2.37.2
From: Christoph Müllner <christoph.muellner@vrull.eu> T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadSync extension, a collection of T-Head-specific multi-processor synchronization instructions. The 'th' prefix and the "XTheadSync" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- bfd/elfxx-riscv.c | 5 +++++ gas/doc/c-riscv.texi | 5 +++++ gas/testsuite/gas/riscv/x-thead-sync-fail.d | 3 +++ gas/testsuite/gas/riscv/x-thead-sync-fail.l | 6 ++++++ gas/testsuite/gas/riscv/x-thead-sync-fail.s | 6 ++++++ gas/testsuite/gas/riscv/x-thead-sync.d | 14 ++++++++++++++ gas/testsuite/gas/riscv/x-thead-sync.s | 6 ++++++ include/opcode/riscv-opc.h | 17 +++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 7 +++++++ 10 files changed, 70 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.d create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 62e45d21d9a..84f0de8d05b 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1224,6 +1224,7 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] = static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = { {"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2388,6 +2389,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "h"); case INSN_CLASS_XTHEADCMO: return riscv_subset_supports (rps, "xtheadcmo"); + case INSN_CLASS_XTHEADSYNC: + return riscv_subset_supports (rps, "xtheadsync"); default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); @@ -2517,6 +2520,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("h"); case INSN_CLASS_XTHEADCMO: return "xtheadcmo"; + case INSN_CLASS_XTHEADSYNC: + return "xtheadsync"; default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 10e9429c83e..c55dd0b812e 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -709,4 +709,9 @@ The XTheadCmo extension provides instructions for cache management. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XTheadSync +The XTheadSync extension provides instructions for multi-processor synchronization. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. + @end table diff --git a/gas/testsuite/gas/riscv/x-thead-sync-fail.d b/gas/testsuite/gas/riscv/x-thead-sync-fail.d new file mode 100644 index 00000000000..1d3fdbd53ef --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-sync-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64i_xtheadsync +#source: x-thead-sync-fail.s +#error_output: x-thead-sync-fail.l diff --git a/gas/testsuite/gas/riscv/x-thead-sync-fail.l b/gas/testsuite/gas/riscv/x-thead-sync-fail.l new file mode 100644 index 00000000000..52420008968 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-sync-fail.l @@ -0,0 +1,6 @@ +.*: Assembler messages: +.*: Error: illegal operands `th.sfence.vmas' +.*: Error: illegal operands `th.sync a0' +.*: Error: illegal operands `th.sync.i a0' +.*: Error: illegal operands `th.sync.is a0' +.*: Error: illegal operands `th.sync.s a0' diff --git a/gas/testsuite/gas/riscv/x-thead-sync-fail.s b/gas/testsuite/gas/riscv/x-thead-sync-fail.s new file mode 100644 index 00000000000..722a6da2691 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-sync-fail.s @@ -0,0 +1,6 @@ +target: + th.sfence.vmas + th.sync a0 + th.sync.i a0 + th.sync.is a0 + th.sync.s a0 diff --git a/gas/testsuite/gas/riscv/x-thead-sync.d b/gas/testsuite/gas/riscv/x-thead-sync.d new file mode 100644 index 00000000000..3c5e9eaa812 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-sync.d @@ -0,0 +1,14 @@ +#as: -march=rv64i_xtheadsync +#source: x-thead-sync.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+04b5000b[ ]+th.sfence.vmas[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+0180000b[ ]+th.sync +[ ]+[0-9a-f]+:[ ]+01a0000b[ ]+th.sync.i +[ ]+[0-9a-f]+:[ ]+01b0000b[ ]+th.sync.is +[ ]+[0-9a-f]+:[ ]+0190000b[ ]+th.sync.s diff --git a/gas/testsuite/gas/riscv/x-thead-sync.s b/gas/testsuite/gas/riscv/x-thead-sync.s new file mode 100644 index 00000000000..85b485693d8 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-sync.s @@ -0,0 +1,6 @@ +target: + th.sfence.vmas a0, a1 + th.sync + th.sync.i + th.sync.is + th.sync.s diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 53b1c224518..970cdf22b25 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2156,6 +2156,17 @@ #define MASK_TH_L2CACHE_CIALL 0xffffffff #define MATCH_TH_L2CACHE_IALL 0x0160000b #define MASK_TH_L2CACHE_IALL 0xffffffff +/* Vendor-specific (T-Head) XTheadSync instructions. */ +#define MATCH_TH_SFENCE_VMAS 0x0400000b +#define MASK_TH_SFENCE_VMAS 0xfe007fff +#define MATCH_TH_SYNC 0x0180000b +#define MASK_TH_SYNC 0xffffffff +#define MATCH_TH_SYNC_I 0x01a0000b +#define MASK_TH_SYNC_I 0xffffffff +#define MATCH_TH_SYNC_IS 0x01b0000b +#define MASK_TH_SYNC_IS 0xffffffff +#define MATCH_TH_SYNC_S 0x0190000b +#define MASK_TH_SYNC_S 0xffffffff /* Unprivileged Counter/Timers CSR addresses. */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 @@ -2917,6 +2928,12 @@ DECLARE_INSN(th_icache_iva, MATCH_TH_ICACHE_IVA, MASK_TH_ICACHE_IVA) DECLARE_INSN(th_l2cache_call, MATCH_TH_L2CACHE_CALL, MASK_TH_L2CACHE_CALL) DECLARE_INSN(th_l2cache_ciall, MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL) DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL) +/* Vendor-specific (T-Head) XTheadSync instructions. */ +DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS) +DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC) +DECLARE_INSN(th_sync_i, MATCH_TH_SYNC_I, MASK_TH_SYNC_I) +DECLARE_INSN(th_sync_is, MATCH_TH_SYNC_IS, MASK_TH_SYNC_IS) +DECLARE_INSN(th_sync_s, MATCH_TH_SYNC_S, MASK_TH_SYNC_S) #endif /* DECLARE_INSN */ #ifdef DECLARE_CSR /* Unprivileged Counter/Timers CSRs. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index d36983140a2..6fdc9c9302e 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -399,6 +399,7 @@ enum riscv_insn_class INSN_CLASS_ZICBOZ, INSN_CLASS_H, INSN_CLASS_XTHEADCMO, + INSN_CLASS_XTHEADSYNC, }; /* This structure holds information for a particular instruction. */ diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index bf073f20e71..8bba6487435 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1850,6 +1850,13 @@ const struct riscv_opcode riscv_opcodes[] = {"th.l2cache.ciall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL, match_opcode, 0}, {"th.l2cache.iall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadSync instructions. */ +{"th.sfence.vmas", 0, INSN_CLASS_XTHEADSYNC, "s,t",MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS, match_opcode, 0}, +{"th.sync", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC, MASK_TH_SYNC, match_opcode, 0}, +{"th.sync.i", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_I, MASK_TH_SYNC_I, match_opcode, 0}, +{"th.sync.is", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_IS, MASK_TH_SYNC_IS, match_opcode, 0}, +{"th.sync.s", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_S, MASK_TH_SYNC_S, match_opcode, 0}, + /* Terminate the list. */ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} }; -- 2.37.2
From: Christoph Müllner <christoph.muellner@vrull.eu> This patch introduces support for arbitrary signed or unsigned immediate encoding formats. The formats have the form "XsN@S" and "XuN@S" with N being the number of bits and S the LSB position. For example an immediate field of 5 bytes that encodes a signed value and is stored in the bits 24-20 of the instruction word can use the format specifier "Xs5@20". Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- gas/config/tc-riscv.c | 74 ++++++++++++++++++++++++++++++++++++++++++ include/opcode/riscv.h | 17 ++++++++++ opcodes/riscv-dis.c | 34 +++++++++++++++++++ 3 files changed, 125 insertions(+) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 2f5ee18e451..694d079863d 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -441,6 +441,9 @@ static char *expr_end; #define INSERT_OPERAND(FIELD, INSN, VALUE) \ INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) +#define INSERT_IMM(n, s, INSN, VALUE) \ + INSERT_BITS ((INSN).insn_opcode, VALUE, (1ULL<<n) - 1, s) + /* Determine if an instruction matches an opcode. */ #define OPCODE_MATCHES(OPCODE, OP) \ (((OPCODE) & MASK_##OP) == MATCH_##OP) @@ -1092,6 +1095,8 @@ arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) } #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift))) +#define USE_IMM(n, s) \ + (used_bits |= ((insn_t)((1ull<<n)-1) << (s))) /* For consistency checking, verify that all bits are specified either by the match/mask part of the instruction definition, or by the @@ -1253,6 +1258,31 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) goto unknown_validate_operand; } break; + case 'X': /* Integer immediate. */ + { + size_t n; + size_t s; + + switch (*++oparg) + { + case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ + goto use_imm; + case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ + goto use_imm; + use_imm: + n = strtol (++oparg, (char **)&oparg, 10); + if (*oparg != '@') + goto unknown_validate_operand; + s = strtol (++oparg, (char **)&oparg, 10); + oparg--; + + USE_IMM (n, s); + break; + default: + goto unknown_validate_operand; + } + } + break; default: unknown_validate_operand: as_bad (_("internal: bad RISC-V opcode " @@ -3262,6 +3292,50 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, asarg = expr_end; continue; + case 'X': /* Integer immediate. */ + { + size_t n; + size_t s; + bool sign; + + switch (*++oparg) + { + case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ + sign = true; + goto parse_imm; + case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ + sign = false; + goto parse_imm; + parse_imm: + n = strtol (++oparg, (char **)&oparg, 10); + if (*oparg != '@') + goto unknown_riscv_ip_operand; + s = strtol (++oparg, (char **)&oparg, 10); + oparg--; + + my_getExpression (imm_expr, asarg); + check_absolute_expr (ip, imm_expr, false); + if (!sign) + { + if (!VALIDATE_U_IMM (imm_expr->X_add_number, n)) + as_bad (_("improper immediate value (%lu)"), + (unsigned long) imm_expr->X_add_number); + } + else + { + if (!VALIDATE_S_IMM (imm_expr->X_add_number, n)) + as_bad (_("improper immediate value (%li)"), + (long) imm_expr->X_add_number); + } + INSERT_IMM (n, s, *ip, imm_expr->X_add_number); + imm_expr->X_op = O_absent; + asarg = expr_end; + continue; + default: + goto unknown_riscv_ip_operand; + } + } + break; default: unknown_riscv_ip_operand: as_fatal (_("internal: unknown argument type `%s'"), diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 6fdc9c9302e..faef28a3739 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -60,6 +60,7 @@ static const char * const riscv_pred_succ[16] = #define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) +#define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n))) #define EXTRACT_ITYPE_IMM(x) \ (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) @@ -347,6 +348,22 @@ static const char * const riscv_pred_succ[16] = #define EXTRACT_OPERAND(FIELD, INSN) \ EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD) +/* Extract an unsigned immediate operand on position s with n bits. */ +#define EXTRACT_U_IMM(n, s, l) \ + RV_X (l, s, n) + +/* Extract an signed immediate operand on position s with n bits. */ +#define EXTRACT_S_IMM(n, s, l) \ + RV_X_SIGNED (l, s, n) + +/* Validate that unsigned n-bit immediate is within bounds. */ +#define VALIDATE_U_IMM(v, n) \ + ((unsigned long) v < (1UL << n)) + +/* Validate that signed n-bit immediate is within bounds. */ +#define VALIDATE_S_IMM(v, n) \ + (v < (long) (1UL << (n-1)) && v >= -(offsetT) (1UL << (n-1))) + /* The maximal number of subset can be required. */ #define MAX_SUBSET_NUM 4 diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 7ae6e709290..c6ddea16dda 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -563,7 +563,41 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info print (info->stream, dis_style_text, "%d", rs1); break; + case 'X': /* Integer immediate. */ + { + size_t n; + size_t s; + bool sign; + + switch (*++oparg) + { + case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ + sign = true; + goto print_imm; + case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ + sign = false; + goto print_imm; + print_imm: + n = strtol (++oparg, (char **)&oparg, 10); + if (*oparg != '@') + goto undefined_modifier; + s = strtol (++oparg, (char **)&oparg, 10); + oparg--; + + if (!sign) + print (info->stream, dis_style_immediate, "%u", + (unsigned)EXTRACT_U_IMM (n, s, l)); + else + print (info->stream, dis_style_immediate, "%i", + (unsigned)EXTRACT_S_IMM (n, s, l)); + break; + default: + goto undefined_modifier; + } + } + break; default: + undefined_modifier: /* xgettext:c-format */ print (info->stream, dis_style_text, _("# internal error, undefined modifier (%c)"), -- 2.37.2
From: Christoph Müllner <christoph.muellner@vrull.eu> T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XThead{Ba,Bb,Bs} extensions, a collection of T-Head-specific bitmanipulation instructions. The 'th' prefix and the "XThead{Ba,Bb,Bs}" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- bfd/elfxx-riscv.c | 15 +++++++++ gas/doc/c-riscv.texi | 15 +++++++++ gas/testsuite/gas/riscv/x-thead-ba-fail.d | 3 ++ gas/testsuite/gas/riscv/x-thead-ba-fail.l | 3 ++ gas/testsuite/gas/riscv/x-thead-ba-fail.s | 3 ++ gas/testsuite/gas/riscv/x-thead-ba.d | 13 ++++++++ gas/testsuite/gas/riscv/x-thead-ba.s | 6 ++++ gas/testsuite/gas/riscv/x-thead-bb-fail.d | 3 ++ gas/testsuite/gas/riscv/x-thead-bb-fail.l | 7 ++++ gas/testsuite/gas/riscv/x-thead-bb-fail.s | 7 ++++ gas/testsuite/gas/riscv/x-thead-bb.d | 30 +++++++++++++++++ gas/testsuite/gas/riscv/x-thead-bb.s | 22 +++++++++++++ gas/testsuite/gas/riscv/x-thead-bs-fail.d | 3 ++ gas/testsuite/gas/riscv/x-thead-bs-fail.l | 3 ++ gas/testsuite/gas/riscv/x-thead-bs-fail.s | 3 ++ gas/testsuite/gas/riscv/x-thead-bs.d | 14 ++++++++ gas/testsuite/gas/riscv/x-thead-bs.s | 6 ++++ include/opcode/riscv-opc.h | 39 +++++++++++++++++++++++ include/opcode/riscv.h | 3 ++ opcodes/riscv-opc.c | 17 ++++++++++ 20 files changed, 215 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.d create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.s create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.d create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.s create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.d create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 84f0de8d05b..d8ccc694cff 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1223,6 +1223,9 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] = static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = { + {"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} @@ -2387,6 +2390,12 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: return riscv_subset_supports (rps, "h"); + case INSN_CLASS_XTHEADBA: + return riscv_subset_supports (rps, "xtheadba"); + case INSN_CLASS_XTHEADBB: + return riscv_subset_supports (rps, "xtheadbb"); + case INSN_CLASS_XTHEADBS: + return riscv_subset_supports (rps, "xtheadbs"); case INSN_CLASS_XTHEADCMO: return riscv_subset_supports (rps, "xtheadcmo"); case INSN_CLASS_XTHEADSYNC: @@ -2518,6 +2527,12 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "svinval"; case INSN_CLASS_H: return _("h"); + case INSN_CLASS_XTHEADBA: + return "xtheadba"; + case INSN_CLASS_XTHEADBB: + return "xtheadbb"; + case INSN_CLASS_XTHEADBS: + return "xtheadbs"; case INSN_CLASS_XTHEADCMO: return "xtheadcmo"; case INSN_CLASS_XTHEADSYNC: diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index c55dd0b812e..570a4f467f8 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -704,6 +704,21 @@ extensions supported and provides the location of their publicly-released documentation: @table @r +@item XTheadBa +The XTheadBa extension provides instructions for address calculations. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. + +@item XTheadBb +The XTheadBb extension provides instructions for basic bit-manipulation + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. + +@item XTheadBs +The XTheadBs extension provides single-bit instructions. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. + @item XTheadCmo The XTheadCmo extension provides instructions for cache management. diff --git a/gas/testsuite/gas/riscv/x-thead-ba-fail.d b/gas/testsuite/gas/riscv/x-thead-ba-fail.d new file mode 100644 index 00000000000..9fbb9351132 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-ba-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64i_xtheadba +#source: x-thead-ba-fail.s +#error_output: x-thead-ba-fail.l diff --git a/gas/testsuite/gas/riscv/x-thead-ba-fail.l b/gas/testsuite/gas/riscv/x-thead-ba-fail.l new file mode 100644 index 00000000000..4bb12e7f642 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-ba-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) diff --git a/gas/testsuite/gas/riscv/x-thead-ba-fail.s b/gas/testsuite/gas/riscv/x-thead-ba-fail.s new file mode 100644 index 00000000000..9a3b27d30e4 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-ba-fail.s @@ -0,0 +1,3 @@ +target: + th.addsl a0, a1, a2, -1 + th.addsl a0, a1, a2, 4 diff --git a/gas/testsuite/gas/riscv/x-thead-ba.d b/gas/testsuite/gas/riscv/x-thead-ba.d new file mode 100644 index 00000000000..bf4f8a5887f --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-ba.d @@ -0,0 +1,13 @@ +#as: -march=rv64i_xtheadba +#source: x-thead-ba.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00c5950b[ ]+th.addsl[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+02c5950b[ ]+th.addsl[ ]+a0,a1,a2,1 +[ ]+[0-9a-f]+:[ ]+04c5950b[ ]+th.addsl[ ]+a0,a1,a2,2 +[ ]+[0-9a-f]+:[ ]+06c5950b[ ]+th.addsl[ ]+a0,a1,a2,3 diff --git a/gas/testsuite/gas/riscv/x-thead-ba.s b/gas/testsuite/gas/riscv/x-thead-ba.s new file mode 100644 index 00000000000..5081c06e6aa --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-ba.s @@ -0,0 +1,6 @@ +target: + th.addsl a0, a1, a2, 0 + th.addsl a0, a1, a2, 1 + th.addsl a0, a1, a2, 2 + th.addsl a0, a1, a2, 3 + diff --git a/gas/testsuite/gas/riscv/x-thead-bb-fail.d b/gas/testsuite/gas/riscv/x-thead-bb-fail.d new file mode 100644 index 00000000000..1dc4c0682c1 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-bb-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64i_xtheadbb +#source: x-thead-bb-fail.s +#error_output: x-thead-bb-fail.l diff --git a/gas/testsuite/gas/riscv/x-thead-bb-fail.l b/gas/testsuite/gas/riscv/x-thead-bb-fail.l new file mode 100644 index 00000000000..dd4a0df664e --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-bb-fail.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(64\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(32\) +.*: Error: illegal operands `th.ext a0,64,62' +.*: Error: illegal operands `th.extu a0,-1,0' diff --git a/gas/testsuite/gas/riscv/x-thead-bb-fail.s b/gas/testsuite/gas/riscv/x-thead-bb-fail.s new file mode 100644 index 00000000000..5b91f5015fb --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-bb-fail.s @@ -0,0 +1,7 @@ +target: + th.srri a0, a1, -1 + th.srri a0, a1, 64 + th.srriw a0, a1, -1 + th.srriw a0, a1, 32 + th.ext a0, 64, 62 + th.extu a0, -1, 0 diff --git a/gas/testsuite/gas/riscv/x-thead-bb.d b/gas/testsuite/gas/riscv/x-thead-bb.d new file mode 100644 index 00000000000..3e5547aad47 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-bb.d @@ -0,0 +1,30 @@ +#as: -march=rv64i_xtheadbb +#source: x-thead-bb.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+1005950b[ ]+th.srri[ ]+a0,a1,0 +[ ]+[0-9a-f]+:[ ]+1015950b[ ]+th.srri[ ]+a0,a1,1 +[ ]+[0-9a-f]+:[ ]+13e5950b[ ]+th.srri[ ]+a0,a1,62 +[ ]+[0-9a-f]+:[ ]+13f5950b[ ]+th.srri[ ]+a0,a1,63 +[ ]+[0-9a-f]+:[ ]+1405950b[ ]+th.srriw[ ]+a0,a1,0 +[ ]+[0-9a-f]+:[ ]+1415950b[ ]+th.srriw[ ]+a0,a1,1 +[ ]+[0-9a-f]+:[ ]+15e5950b[ ]+th.srriw[ ]+a0,a1,30 +[ ]+[0-9a-f]+:[ ]+15f5950b[ ]+th.srriw[ ]+a0,a1,31 +[ ]+[0-9a-f]+:[ ]+0405a50b[ ]+th.ext[ ]+a0,a1,1,0 +[ ]+[0-9a-f]+:[ ]+7c05a50b[ ]+th.ext[ ]+a0,a1,31,0 +[ ]+[0-9a-f]+:[ ]+fdf5a50b[ ]+th.ext[ ]+a0,a1,63,31 +[ ]+[0-9a-f]+:[ ]+ffe5a50b[ ]+th.ext[ ]+a0,a1,63,62 +[ ]+[0-9a-f]+:[ ]+0405b50b[ ]+th.extu[ ]+a0,a1,1,0 +[ ]+[0-9a-f]+:[ ]+7c05b50b[ ]+th.extu[ ]+a0,a1,31,0 +[ ]+[0-9a-f]+:[ ]+fdf5b50b[ ]+th.extu[ ]+a0,a1,63,31 +[ ]+[0-9a-f]+:[ ]+ffe5b50b[ ]+th.extu[ ]+a0,a1,63,62 +[ ]+[0-9a-f]+:[ ]+8405950b[ ]+th.ff0[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+8605950b[ ]+th.ff1[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+8205950b[ ]+th.rev[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+9005950b[ ]+th.revw[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+8005950b[ ]+th.tstnbz[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/x-thead-bb.s b/gas/testsuite/gas/riscv/x-thead-bb.s new file mode 100644 index 00000000000..e31b3b69651 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-bb.s @@ -0,0 +1,22 @@ +target: + th.srri a0, a1, 0 + th.srri a0, a1, 1 + th.srri a0, a1, 62 + th.srri a0, a1, 63 + th.srriw a0, a1, 0 + th.srriw a0, a1, 1 + th.srriw a0, a1, 30 + th.srriw a0, a1, 31 + th.ext a0, a1, 1, 0 + th.ext a0, a1, 31, 0 + th.ext a0, a1, 63, 31 + th.ext a0, a1, 63, 62 + th.extu a0, a1, 1, 0 + th.extu a0, a1, 31, 0 + th.extu a0, a1, 63, 31 + th.extu a0, a1, 63, 62 + th.ff0 a0, a1 + th.ff1 a0, a1 + th.rev a0, a1 + th.revw a0, a1 + th.tstnbz a0, a1 diff --git a/gas/testsuite/gas/riscv/x-thead-bs-fail.d b/gas/testsuite/gas/riscv/x-thead-bs-fail.d new file mode 100644 index 00000000000..93265527da5 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-bs-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64i_xtheadbs +#source: x-thead-bs-fail.s +#error_output: x-thead-bs-fail.l diff --git a/gas/testsuite/gas/riscv/x-thead-bs-fail.l b/gas/testsuite/gas/riscv/x-thead-bs-fail.l new file mode 100644 index 00000000000..c8a7ff4e7f1 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-bs-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(64\) diff --git a/gas/testsuite/gas/riscv/x-thead-bs-fail.s b/gas/testsuite/gas/riscv/x-thead-bs-fail.s new file mode 100644 index 00000000000..fbb296e75fc --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-bs-fail.s @@ -0,0 +1,3 @@ +target: + th.tst a0, a1, -1 + th.tst a0, a1, 64 diff --git a/gas/testsuite/gas/riscv/x-thead-bs.d b/gas/testsuite/gas/riscv/x-thead-bs.d new file mode 100644 index 00000000000..18cfd28e5d7 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-bs.d @@ -0,0 +1,14 @@ +#as: -march=rv64i_xtheadbs +#source: x-thead-bs.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+8805950b[ ]+th.tst[ ]+a0,a1,0 +[ ]+[0-9a-f]+:[ ]+8815950b[ ]+th.tst[ ]+a0,a1,1 +[ ]+[0-9a-f]+:[ ]+89f5950b[ ]+th.tst[ ]+a0,a1,31 +[ ]+[0-9a-f]+:[ ]+8a05950b[ ]+th.tst[ ]+a0,a1,32 +[ ]+[0-9a-f]+:[ ]+8bf5950b[ ]+th.tst[ ]+a0,a1,63 diff --git a/gas/testsuite/gas/riscv/x-thead-bs.s b/gas/testsuite/gas/riscv/x-thead-bs.s new file mode 100644 index 00000000000..39db01cb959 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-bs.s @@ -0,0 +1,6 @@ +target: + th.tst a0, a1, 0 + th.tst a0, a1, 1 + th.tst a0, a1, 31 + th.tst a0, a1, 32 + th.tst a0, a1, 63 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 970cdf22b25..9ed5cb455f2 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2113,6 +2113,31 @@ #define MASK_CBO_INVAL 0xfff07fff #define MATCH_CBO_ZERO 0x40200f #define MASK_CBO_ZERO 0xfff07fff +/* Vendor-specific (T-Head) XTheadBa instructions. */ +#define MATCH_TH_ADDSL 0x0000100b +#define MASK_TH_ADDSL 0xf800707f +/* Vendor-specific (T-Head) XTheadBb instructions. */ +#define MATCH_TH_SRRI 0x1000100b +#define MASK_TH_SRRI 0xfc00707f +#define MATCH_TH_SRRIW 0x1400100b +#define MASK_TH_SRRIW 0xfe00707f +#define MATCH_TH_EXT 0x0000200b +#define MASK_TH_EXT 0x0000707f +#define MATCH_TH_EXTU 0x0000300b +#define MASK_TH_EXTU 0x0000707f +#define MATCH_TH_FF0 0x8400100b +#define MASK_TH_FF0 0xfff0707f +#define MATCH_TH_FF1 0x8600100b +#define MASK_TH_FF1 0xfff0707f +#define MATCH_TH_REV 0x8200100b +#define MASK_TH_REV 0xfff0707f +#define MATCH_TH_REVW 0x9000100b +#define MASK_TH_REVW 0xfff0707f +#define MATCH_TH_TSTNBZ 0x8000100b +#define MASK_TH_TSTNBZ 0xfff0707f +/* Vendor-specific (T-Head) XTheadBs instructions. */ +#define MATCH_TH_TST 0x8800100b +#define MASK_TH_TST 0xfc00707f /* Vendor-specific (T-Head) XTheadCmo instructions. */ #define MATCH_TH_DCACHE_CALL 0x0010000b #define MASK_TH_DCACHE_CALL 0xffffffff @@ -2906,6 +2931,20 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN); DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH); DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL); DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO); +/* Vendor-specific (T-Head) XTheadBa instructions. */ +DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) +/* Vendor-specific (T-Head) XTheadBb instructions. */ +DECLARE_INSN(th_srri, MATCH_TH_SRRI, MASK_TH_SRRI) +DECLARE_INSN(th_srriw, MATCH_TH_SRRIW, MASK_TH_SRRIW) +DECLARE_INSN(th_ext, MATCH_TH_EXT, MASK_TH_EXT) +DECLARE_INSN(th_extu, MATCH_TH_EXTU, MASK_TH_EXTU) +DECLARE_INSN(th_ff0, MATCH_TH_FF0, MASK_TH_FF0) +DECLARE_INSN(th_ff1, MATCH_TH_FF1, MASK_TH_FF1) +DECLARE_INSN(th_rev, MATCH_TH_REV, MASK_TH_REV) +DECLARE_INSN(th_revw, MATCH_TH_REVW, MASK_TH_REVW) +DECLARE_INSN(th_tstbnz, MATCH_TH_TSTNBZ, MASK_TH_TSTNBZ) +/* Vendor-specific (T-Head) XTheadBs instructions. */ +DECLARE_INSN(th_tst, MATCH_TH_TST, MASK_TH_TST) /* Vendor-specific (T-Head) XTheadCmo instructions. */ DECLARE_INSN(th_dcache_call, MATCH_TH_DCACHE_CALL, MASK_TH_DCACHE_CALL) DECLARE_INSN(th_dcache_ciall, MATCH_TH_DCACHE_CIALL, MASK_TH_DCACHE_CIALL) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index faef28a3739..53b5b3c5aaf 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -415,6 +415,9 @@ enum riscv_insn_class INSN_CLASS_ZICBOP, INSN_CLASS_ZICBOZ, INSN_CLASS_H, + INSN_CLASS_XTHEADBA, + INSN_CLASS_XTHEADBB, + INSN_CLASS_XTHEADBS, INSN_CLASS_XTHEADCMO, INSN_CLASS_XTHEADSYNC, }; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 8bba6487435..6f4a3f8236c 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1825,6 +1825,23 @@ const struct riscv_opcode riscv_opcodes[] = {"hsv.w", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE }, {"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE }, +/* Vendor-specific (T-Head) XTheadBa instructions. */ +{"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0}, + +/* Vendor-specific (T-Head) XTheadBb instructions. */ +{"th.srri", 0, INSN_CLASS_XTHEADBB, "d,s,Xu6@20", MATCH_TH_SRRI, MASK_TH_SRRI, match_opcode, 0}, +{"th.srriw", 64, INSN_CLASS_XTHEADBB, "d,s,Xu5@20", MATCH_TH_SRRIW, MASK_TH_SRRIW, match_opcode, 0}, +{"th.ext", 0, INSN_CLASS_XTHEADBB, "d,s,Xu6@26,Xu6@20", MATCH_TH_EXT, MASK_TH_EXT, match_opcode, 0}, +{"th.extu", 0, INSN_CLASS_XTHEADBB, "d,s,Xu6@26,Xu6@20", MATCH_TH_EXTU, MASK_TH_EXTU, match_opcode, 0}, +{"th.ff0", 0, INSN_CLASS_XTHEADBB, "d,s", MATCH_TH_FF0, MASK_TH_FF0, match_opcode, 0}, +{"th.ff1", 0, INSN_CLASS_XTHEADBB, "d,s", MATCH_TH_FF1, MASK_TH_FF1, match_opcode, 0}, +{"th.rev", 0, INSN_CLASS_XTHEADBB, "d,s", MATCH_TH_REV, MASK_TH_REV, match_opcode, 0}, +{"th.revw", 64, INSN_CLASS_XTHEADBB, "d,s", MATCH_TH_REVW, MASK_TH_REVW, match_opcode, 0}, +{"th.tstnbz", 0, INSN_CLASS_XTHEADBB, "d,s", MATCH_TH_TSTNBZ, MASK_TH_TSTNBZ, match_opcode, 0}, + +/* Vendor-specific (T-Head) XTheadBs instructions. */ +{"th.tst", 0, INSN_CLASS_XTHEADBS, "d,s,Xu6@20", MATCH_TH_TST, MASK_TH_TST, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadCmo instructions. */ {"th.dcache.call", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_DCACHE_CALL, MASK_TH_DCACHE_CALL, match_opcode, 0}, {"th.dcache.ciall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_DCACHE_CIALL, MASK_TH_DCACHE_CIALL, match_opcode, 0}, -- 2.37.2
From: Christoph Müllner <christoph.muellner@vrull.eu> T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadCondMov extension, a collection of T-Head-specific conditional move instructions. The 'th' prefix and the "XTheadCondMov" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- bfd/elfxx-riscv.c | 5 +++++ gas/doc/c-riscv.texi | 5 +++++ gas/testsuite/gas/riscv/x-thead-condmov.d | 11 +++++++++++ gas/testsuite/gas/riscv/x-thead-condmov.s | 3 +++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 4 ++++ 7 files changed, 37 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.d create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index d8ccc694cff..6bb8d6b2dc9 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1227,6 +1227,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadcondmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2398,6 +2399,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadbs"); case INSN_CLASS_XTHEADCMO: return riscv_subset_supports (rps, "xtheadcmo"); + case INSN_CLASS_XTHEADCONDMOV: + return riscv_subset_supports (rps, "xtheadcondmov"); case INSN_CLASS_XTHEADSYNC: return riscv_subset_supports (rps, "xtheadsync"); default: @@ -2535,6 +2538,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadbs"; case INSN_CLASS_XTHEADCMO: return "xtheadcmo"; + case INSN_CLASS_XTHEADCONDMOV: + return "xtheadcondmov"; case INSN_CLASS_XTHEADSYNC: return "xtheadsync"; default: diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 570a4f467f8..b1462ce213b 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -724,6 +724,11 @@ The XTheadCmo extension provides instructions for cache management. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XTheadCondMov +The XTheadCondMov extension provides instructions for conditional moves. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. + @item XTheadSync The XTheadSync extension provides instructions for multi-processor synchronization. diff --git a/gas/testsuite/gas/riscv/x-thead-condmov.d b/gas/testsuite/gas/riscv/x-thead-condmov.d new file mode 100644 index 00000000000..5972d09ec99 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-condmov.d @@ -0,0 +1,11 @@ +#as: -march=rv64i_xtheadcondmov +#source: x-thead-condmov.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+40c5950b[ ]+th.mveqz[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+42c5950b[ ]+th.mvnez[ ]+a0,a1,a2 diff --git a/gas/testsuite/gas/riscv/x-thead-condmov.s b/gas/testsuite/gas/riscv/x-thead-condmov.s new file mode 100644 index 00000000000..f71191d110b --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-condmov.s @@ -0,0 +1,3 @@ +target: + th.mveqz a0, a1, a2 + th.mvnez a0, a1, a2 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 9ed5cb455f2..5c0f6100e29 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2181,6 +2181,11 @@ #define MASK_TH_L2CACHE_CIALL 0xffffffff #define MATCH_TH_L2CACHE_IALL 0x0160000b #define MASK_TH_L2CACHE_IALL 0xffffffff +/* Vendor-specific (T-Head) XTheadCondMov instructions. */ +#define MATCH_TH_MVEQZ 0x4000100b +#define MASK_TH_MVEQZ 0xfe00707f +#define MATCH_TH_MVNEZ 0x4200100b +#define MASK_TH_MVNEZ 0xfe00707f /* Vendor-specific (T-Head) XTheadSync instructions. */ #define MATCH_TH_SFENCE_VMAS 0x0400000b #define MASK_TH_SFENCE_VMAS 0xfe007fff @@ -2967,6 +2972,9 @@ DECLARE_INSN(th_icache_iva, MATCH_TH_ICACHE_IVA, MASK_TH_ICACHE_IVA) DECLARE_INSN(th_l2cache_call, MATCH_TH_L2CACHE_CALL, MASK_TH_L2CACHE_CALL) DECLARE_INSN(th_l2cache_ciall, MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL) DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL) +/* Vendor-specific (T-Head) XTheadCondMov instructions. */ +DECLARE_INSN(th_mveqz, MATCH_TH_MVEQZ, MASK_TH_MVEQZ) +DECLARE_INSN(th_mvnez, MATCH_TH_MVNEZ, MASK_TH_MVNEZ) /* Vendor-specific (T-Head) XTheadSync instructions. */ DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS) DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 53b5b3c5aaf..d0ff929f84b 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -419,6 +419,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADBB, INSN_CLASS_XTHEADBS, INSN_CLASS_XTHEADCMO, + INSN_CLASS_XTHEADCONDMOV, INSN_CLASS_XTHEADSYNC, }; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 6f4a3f8236c..111308686fc 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1867,6 +1867,10 @@ const struct riscv_opcode riscv_opcodes[] = {"th.l2cache.ciall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL, match_opcode, 0}, {"th.l2cache.iall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadCondMov instructions. */ +{"th.mveqz", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVEQZ, MASK_TH_MVEQZ, match_opcode, 0}, +{"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadSync instructions. */ {"th.sfence.vmas", 0, INSN_CLASS_XTHEADSYNC, "s,t",MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS, match_opcode, 0}, {"th.sync", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC, MASK_TH_SYNC, match_opcode, 0}, -- 2.37.2
From: Christoph Müllner <christoph.muellner@vrull.eu> T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadMac extension, a collection of T-Head-specific multiply-accumulate instructions. The 'th' prefix and the "XTheadMac" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- bfd/elfxx-riscv.c | 5 +++++ gas/doc/c-riscv.texi | 5 +++++ gas/testsuite/gas/riscv/x-thead-mac.d | 15 +++++++++++++++ gas/testsuite/gas/riscv/x-thead-mac.s | 7 +++++++ include/opcode/riscv-opc.h | 20 ++++++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 8 ++++++++ 7 files changed, 61 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.d create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 6bb8d6b2dc9..8c30f75f7e6 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1228,6 +1228,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadcondmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2401,6 +2402,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadcmo"); case INSN_CLASS_XTHEADCONDMOV: return riscv_subset_supports (rps, "xtheadcondmov"); + case INSN_CLASS_XTHEADMAC: + return riscv_subset_supports (rps, "xtheadmac"); case INSN_CLASS_XTHEADSYNC: return riscv_subset_supports (rps, "xtheadsync"); default: @@ -2540,6 +2543,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadcmo"; case INSN_CLASS_XTHEADCONDMOV: return "xtheadcondmov"; + case INSN_CLASS_XTHEADMAC: + return "xtheadmac"; case INSN_CLASS_XTHEADSYNC: return "xtheadsync"; default: diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index b1462ce213b..401f7e443c2 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -729,6 +729,11 @@ The XTheadCondMov extension provides instructions for conditional moves. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XTheadMac +The XTheadMac extension provides multiply-accumulate instructions. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. + @item XTheadSync The XTheadSync extension provides instructions for multi-processor synchronization. diff --git a/gas/testsuite/gas/riscv/x-thead-mac.d b/gas/testsuite/gas/riscv/x-thead-mac.d new file mode 100644 index 00000000000..3f8e654797b --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-mac.d @@ -0,0 +1,15 @@ +#as: -march=rv64i_xtheadmac +#source: x-thead-mac.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+20c5950b[ ]+th.mula[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+28c5950b[ ]+th.mulah[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+24c5950b[ ]+th.mulaw[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+22c5950b[ ]+th.muls[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+2ac5950b[ ]+th.mulsh[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+26c5950b[ ]+th.mulsw[ ]+a0,a1,a2 diff --git a/gas/testsuite/gas/riscv/x-thead-mac.s b/gas/testsuite/gas/riscv/x-thead-mac.s new file mode 100644 index 00000000000..986b96f79e3 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-mac.s @@ -0,0 +1,7 @@ +target: + th.mula a0, a1, a2 + th.mulah a0, a1, a2 + th.mulaw a0, a1, a2 + th.muls a0, a1, a2 + th.mulsh a0, a1, a2 + th.mulsw a0, a1, a2 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 5c0f6100e29..b504ce019b6 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2186,6 +2186,19 @@ #define MASK_TH_MVEQZ 0xfe00707f #define MATCH_TH_MVNEZ 0x4200100b #define MASK_TH_MVNEZ 0xfe00707f +/* Vendor-specific (T-Head) XTheadMac instructions. */ +#define MATCH_TH_MULA 0x2000100b +#define MASK_TH_MULA 0xfe00707f +#define MATCH_TH_MULAH 0x2800100b +#define MASK_TH_MULAH 0xfe00707f +#define MATCH_TH_MULAW 0x2400100b +#define MASK_TH_MULAW 0xfe00707f +#define MATCH_TH_MULS 0x2200100b +#define MASK_TH_MULS 0xfe00707f +#define MATCH_TH_MULSH 0x2a00100b +#define MASK_TH_MULSH 0xfe00707f +#define MATCH_TH_MULSW 0x2600100b +#define MASK_TH_MULSW 0xfe00707f /* Vendor-specific (T-Head) XTheadSync instructions. */ #define MATCH_TH_SFENCE_VMAS 0x0400000b #define MASK_TH_SFENCE_VMAS 0xfe007fff @@ -2975,6 +2988,13 @@ DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL) /* Vendor-specific (T-Head) XTheadCondMov instructions. */ DECLARE_INSN(th_mveqz, MATCH_TH_MVEQZ, MASK_TH_MVEQZ) DECLARE_INSN(th_mvnez, MATCH_TH_MVNEZ, MASK_TH_MVNEZ) +/* Vendor-specific (T-Head) XTheadMac instructions. */ +DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA) +DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH) +DECLARE_INSN(th_mulaw, MATCH_TH_MULAW, MASK_TH_MULAW) +DECLARE_INSN(th_muls, MATCH_TH_MULS, MASK_TH_MULS) +DECLARE_INSN(th_mulsh, MATCH_TH_MULSH, MASK_TH_MULSH) +DECLARE_INSN(th_mulsw, MATCH_TH_MULSW, MASK_TH_MULSW) /* Vendor-specific (T-Head) XTheadSync instructions. */ DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS) DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index d0ff929f84b..854269a9d98 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -420,6 +420,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADBS, INSN_CLASS_XTHEADCMO, INSN_CLASS_XTHEADCONDMOV, + INSN_CLASS_XTHEADMAC, INSN_CLASS_XTHEADSYNC, }; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 111308686fc..5d5298923c8 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1871,6 +1871,14 @@ const struct riscv_opcode riscv_opcodes[] = {"th.mveqz", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVEQZ, MASK_TH_MVEQZ, match_opcode, 0}, {"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadMac instructions. */ +{"th.mula", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA, MASK_TH_MULA, match_opcode, 0}, +{"th.mulah", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAH, MASK_TH_MULAH, match_opcode, 0}, +{"th.mulaw", 64, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAW, MASK_TH_MULAW, match_opcode, 0}, +{"th.muls", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULS, MASK_TH_MULS, match_opcode, 0}, +{"th.mulsh", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULSH, MASK_TH_MULSH, match_opcode, 0}, +{"th.mulsw", 64, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULSW, MASK_TH_MULSW, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadSync instructions. */ {"th.sfence.vmas", 0, INSN_CLASS_XTHEADSYNC, "s,t",MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS, match_opcode, 0}, {"th.sync", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC, MASK_TH_SYNC, match_opcode, 0}, -- 2.37.2
From: Christoph Müllner <christoph.muellner@vrull.eu> T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadFMemIdx extension, a collection of T-Head-specific floating-point memory access instructions. The 'th' prefix and the "XTheadFMemIdx" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- bfd/elfxx-riscv.c | 5 ++++ gas/doc/c-riscv.texi | 5 ++++ .../gas/riscv/x-thead-fmemidx-fail.d | 3 +++ .../gas/riscv/x-thead-fmemidx-fail.l | 18 +++++++++++++ .../gas/riscv/x-thead-fmemidx-fail.s | 17 ++++++++++++ gas/testsuite/gas/riscv/x-thead-fmemidx.d | 25 ++++++++++++++++++ gas/testsuite/gas/riscv/x-thead-fmemidx.s | 17 ++++++++++++ include/opcode/riscv-opc.h | 26 +++++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 10 +++++++ 10 files changed, 127 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.d create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 8c30f75f7e6..52aa07877b9 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1228,6 +1228,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadcondmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadfmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} @@ -2402,6 +2403,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadcmo"); case INSN_CLASS_XTHEADCONDMOV: return riscv_subset_supports (rps, "xtheadcondmov"); + case INSN_CLASS_XTHEADFMEMIDX: + return riscv_subset_supports (rps, "xtheadfmemidx"); case INSN_CLASS_XTHEADMAC: return riscv_subset_supports (rps, "xtheadmac"); case INSN_CLASS_XTHEADSYNC: @@ -2543,6 +2546,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadcmo"; case INSN_CLASS_XTHEADCONDMOV: return "xtheadcondmov"; + case INSN_CLASS_XTHEADFMEMIDX: + return "xtheadfmemidx"; case INSN_CLASS_XTHEADMAC: return "xtheadmac"; case INSN_CLASS_XTHEADSYNC: diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 401f7e443c2..392be0e7e21 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -729,6 +729,11 @@ The XTheadCondMov extension provides instructions for conditional moves. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XTheadFMemIdx +The XTheadFMemIdx extension provides floating-point memory operations. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. + @item XTheadMac The XTheadMac extension provides multiply-accumulate instructions. diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d new file mode 100644 index 00000000000..a32e81eec46 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64i_xtheadfmemidx +#source: x-thead-fmemidx-fail.s +#error_output: x-thead-fmemidx-fail.l diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l new file mode 100644 index 00000000000..ef28f047b41 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l @@ -0,0 +1,18 @@ +.*: Assembler messages: +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) + diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s new file mode 100644 index 00000000000..e486c6a1423 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s @@ -0,0 +1,17 @@ +target: + th.flrd a0, a1, a2, -1 + th.flrd a0, a1, a2, 4 + th.flrw a0, a1, a2, -1 + th.flrw a0, a1, a2, 4 + th.flurd a0, a1, a2, -1 + th.flurd a0, a1, a2, 4 + th.flurw a0, a1, a2, -1 + th.flurw a0, a1, a2, 4 + th.fsrd a0, a1, a2, -1 + th.fsrd a0, a1, a2, 4 + th.fsrw a0, a1, a2, -1 + th.fsrw a0, a1, a2, 4 + th.fsurd a0, a1, a2, -1 + th.fsurd a0, a1, a2, 4 + th.fsurw a0, a1, a2, -1 + th.fsurw a0, a1, a2, 4 diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx.d b/gas/testsuite/gas/riscv/x-thead-fmemidx.d new file mode 100644 index 00000000000..dfa477c8fc4 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx.d @@ -0,0 +1,25 @@ +#as: -march=rv64i_xtheadfmemidx +#source: x-thead-fmemidx.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+60c5e50b[ ]+th.flrd[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+66c5e50b[ ]+th.flrd[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+40c5e50b[ ]+th.flrw[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+46c5e50b[ ]+th.flrw[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+70c5e50b[ ]+th.flurd[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+76c5e50b[ ]+th.flurd[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+50c5e50b[ ]+th.flurw[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+56c5e50b[ ]+th.flurw[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+60c5f50b[ ]+th.fsrd[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+66c5f50b[ ]+th.fsrd[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+40c5f50b[ ]+th.fsrw[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+46c5f50b[ ]+th.fsrw[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+70c5f50b[ ]+th.fsurd[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+76c5f50b[ ]+th.fsurd[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+50c5f50b[ ]+th.fsurw[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+56c5f50b[ ]+th.fsurw[ ]+a0,a1,a2,3 diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx.s b/gas/testsuite/gas/riscv/x-thead-fmemidx.s new file mode 100644 index 00000000000..0d70bb7e799 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx.s @@ -0,0 +1,17 @@ +target: + th.flrd a0, a1, a2, 0 + th.flrd a0, a1, a2, 3 + th.flrw a0, a1, a2, 0 + th.flrw a0, a1, a2, 3 + th.flurd a0, a1, a2, 0 + th.flurd a0, a1, a2, 3 + th.flurw a0, a1, a2, 0 + th.flurw a0, a1, a2, 3 + th.fsrd a0, a1, a2, 0 + th.fsrd a0, a1, a2, 3 + th.fsrw a0, a1, a2, 0 + th.fsrw a0, a1, a2, 3 + th.fsurd a0, a1, a2, 0 + th.fsurd a0, a1, a2, 3 + th.fsurw a0, a1, a2, 0 + th.fsurw a0, a1, a2, 3 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index b504ce019b6..ecba9f51c84 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2186,6 +2186,23 @@ #define MASK_TH_MVEQZ 0xfe00707f #define MATCH_TH_MVNEZ 0x4200100b #define MASK_TH_MVNEZ 0xfe00707f +/* Vendor-specific (T-Head) XTheadFMemIdx instructions. */ +#define MATCH_TH_FLRD 0x6000600b +#define MASK_TH_FLRD 0xf800707f +#define MATCH_TH_FLRW 0x4000600b +#define MASK_TH_FLRW 0xf800707f +#define MATCH_TH_FLURD 0x7000600b +#define MASK_TH_FLURD 0xf800707f +#define MATCH_TH_FLURW 0x5000600b +#define MASK_TH_FLURW 0xf800707f +#define MATCH_TH_FSRD 0x6000700b +#define MASK_TH_FSRD 0xf800707f +#define MATCH_TH_FSRW 0x4000700b +#define MASK_TH_FSRW 0xf800707f +#define MATCH_TH_FSURD 0x7000700b +#define MASK_TH_FSURD 0xf800707f +#define MATCH_TH_FSURW 0x5000700b +#define MASK_TH_FSURW 0xf800707f /* Vendor-specific (T-Head) XTheadMac instructions. */ #define MATCH_TH_MULA 0x2000100b #define MASK_TH_MULA 0xfe00707f @@ -2988,6 +3005,15 @@ DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL) /* Vendor-specific (T-Head) XTheadCondMov instructions. */ DECLARE_INSN(th_mveqz, MATCH_TH_MVEQZ, MASK_TH_MVEQZ) DECLARE_INSN(th_mvnez, MATCH_TH_MVNEZ, MASK_TH_MVNEZ) +/* Vendor-specific (T-Head) XTheadFMemIdx instructions. */ +DECLARE_INSN(th_flrd, MATCH_TH_FLRD, MASK_TH_FLRD) +DECLARE_INSN(th_flrw, MATCH_TH_FLRW, MASK_TH_FLRW) +DECLARE_INSN(th_flurd, MATCH_TH_FLURD, MASK_TH_FLURD) +DECLARE_INSN(th_flurw, MATCH_TH_FLURW, MASK_TH_FLURW) +DECLARE_INSN(th_fsrd, MATCH_TH_FSRD, MASK_TH_FSRD) +DECLARE_INSN(th_fsrw, MATCH_TH_FSRW, MASK_TH_FSRW) +DECLARE_INSN(th_fsurd, MATCH_TH_FSURD, MASK_TH_FSURD) +DECLARE_INSN(th_fsurw, MATCH_TH_FSURW, MASK_TH_FSURW) /* Vendor-specific (T-Head) XTheadMac instructions. */ DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA) DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 854269a9d98..1b7de3cb142 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -420,6 +420,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADBS, INSN_CLASS_XTHEADCMO, INSN_CLASS_XTHEADCONDMOV, + INSN_CLASS_XTHEADFMEMIDX, INSN_CLASS_XTHEADMAC, INSN_CLASS_XTHEADSYNC, }; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 5d5298923c8..6c1c4c9a1ad 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1871,6 +1871,16 @@ const struct riscv_opcode riscv_opcodes[] = {"th.mveqz", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVEQZ, MASK_TH_MVEQZ, match_opcode, 0}, {"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadFMemIdx instructions. */ +{"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLRD, MASK_TH_FLRD, match_opcode, 0}, +{"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLRW, MASK_TH_FLRW, match_opcode, 0}, +{"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, 0}, +{"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, 0}, +{"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSRD, MASK_TH_FSRD, match_opcode, 0}, +{"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSRW, MASK_TH_FSRW, match_opcode, 0}, +{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0}, +{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadMac instructions. */ {"th.mula", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA, MASK_TH_MULA, match_opcode, 0}, {"th.mulah", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAH, MASK_TH_MULAH, match_opcode, 0}, -- 2.37.2
From: Christoph Müllner <christoph.muellner@vrull.eu> T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadMemIdx extension, a collection of T-Head specific GPR memory access instructions. The 'th' prefix and the "XTheadMemIdx" extension are documented in a PR for the RISC-V toolchain conventions ([1]). In total XTheadCmo introduces the following 44 instructions (BU,HU,WU only for loads (zero-extend instead of sign-extend)): * {L,S}{D,W,WU,H,HU,B,BU}{IA,IB} rd, rs1, imm5, imm2 * {L,S}R{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2 * {L,S}UR{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2 [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- bfd/elfxx-riscv.c | 5 + gas/doc/c-riscv.texi | 5 + gas/testsuite/gas/riscv/x-thead-memidx-fail.d | 3 + gas/testsuite/gas/riscv/x-thead-memidx-fail.l | 14 ++ gas/testsuite/gas/riscv/x-thead-memidx-fail.s | 14 ++ gas/testsuite/gas/riscv/x-thead-memidx.d | 53 +++++++ gas/testsuite/gas/riscv/x-thead-memidx.s | 48 +++++++ include/opcode/riscv-opc.h | 134 ++++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 60 ++++++++ 10 files changed, 337 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.d create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 52aa07877b9..caa690913f0 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1230,6 +1230,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadcondmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadfmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2407,6 +2408,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadfmemidx"); case INSN_CLASS_XTHEADMAC: return riscv_subset_supports (rps, "xtheadmac"); + case INSN_CLASS_XTHEADMEMIDX: + return riscv_subset_supports (rps, "xtheadmemidx"); case INSN_CLASS_XTHEADSYNC: return riscv_subset_supports (rps, "xtheadsync"); default: @@ -2550,6 +2553,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadfmemidx"; case INSN_CLASS_XTHEADMAC: return "xtheadmac"; + case INSN_CLASS_XTHEADMEMIDX: + return "xtheadmemidx"; case INSN_CLASS_XTHEADSYNC: return "xtheadsync"; default: diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 392be0e7e21..ed3d98962e4 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -739,6 +739,11 @@ The XTheadMac extension provides multiply-accumulate instructions. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XTheadMemIdx +The XTheadMemIdx extension provides GPR memory operations. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. + @item XTheadSync The XTheadSync extension provides instructions for multi-processor synchronization. diff --git a/gas/testsuite/gas/riscv/x-thead-memidx-fail.d b/gas/testsuite/gas/riscv/x-thead-memidx-fail.d new file mode 100644 index 00000000000..086855c1030 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-memidx-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64gc_xtheadmemidx +#source: x-thead-memidx-fail.s +#error_output: x-thead-memidx-fail.l diff --git a/gas/testsuite/gas/riscv/x-thead-memidx-fail.l b/gas/testsuite/gas/riscv/x-thead-memidx-fail.l new file mode 100644 index 00000000000..c6bd25c0268 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-memidx-fail.l @@ -0,0 +1,14 @@ +.*: Assembler messages: +.*: Error: improper immediate value \(-17\) +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(16\) +.*: Error: improper immediate value \(4\) + +.*: Error: illegal operands `th.ldia a0,\(a0\),0,0' +.*: Error: illegal operands `th.ldib a0,\(a0\),0,0' + +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) + +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) diff --git a/gas/testsuite/gas/riscv/x-thead-memidx-fail.s b/gas/testsuite/gas/riscv/x-thead-memidx-fail.s new file mode 100644 index 00000000000..c9eb99ce52e --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-memidx-fail.s @@ -0,0 +1,14 @@ +target: + th.ldia a0, (a1), -17, 0 + th.ldib a0, (a1), 0, -1 + th.sdia a0, (a1), 16, 0 + th.sdib a0, (a1), 0, 4 + + th.ldia a0, (a0), 0, 0 + th.ldib a0, (a0), 0, 0 + + th.lrd a0, a1, a2, -1 + th.srd a0, a1, a2, 4 + + th.lurd a0, a1, a2, -1 + th.surd a0, a1, a2, 4 diff --git a/gas/testsuite/gas/riscv/x-thead-memidx.d b/gas/testsuite/gas/riscv/x-thead-memidx.d new file mode 100644 index 00000000000..03d39858aaa --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-memidx.d @@ -0,0 +1,53 @@ +#as: -march=rv64gc_xtheadmemidx +#source: x-thead-memidx.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+7805c50b[ ]+th.ldia[ ]+a0,\(a1\),0,0 +[ ]+[0-9a-f]+:[ ]+6af5c50b[ ]+th.ldib[ ]+a0,\(a1\),15,1 +[ ]+[0-9a-f]+:[ ]+5c05c50b[ ]+th.lwia[ ]+a0,\(a1\),0,2 +[ ]+[0-9a-f]+:[ ]+4f05c50b[ ]+th.lwib[ ]+a0,\(a1\),-16,3 +[ ]+[0-9a-f]+:[ ]+d805c50b[ ]+th.lwuia[ ]+a0,\(a1\),0,0 +[ ]+[0-9a-f]+:[ ]+caf5c50b[ ]+th.lwuib[ ]+a0,\(a1\),15,1 +[ ]+[0-9a-f]+:[ ]+3c05c50b[ ]+th.lhia[ ]+a0,\(a1\),0,2 +[ ]+[0-9a-f]+:[ ]+2f05c50b[ ]+th.lhib[ ]+a0,\(a1\),-16,3 +[ ]+[0-9a-f]+:[ ]+b805c50b[ ]+th.lhuia[ ]+a0,\(a1\),0,0 +[ ]+[0-9a-f]+:[ ]+aaf5c50b[ ]+th.lhuib[ ]+a0,\(a1\),15,1 +[ ]+[0-9a-f]+:[ ]+1c05c50b[ ]+th.lbia[ ]+a0,\(a1\),0,2 +[ ]+[0-9a-f]+:[ ]+0f05c50b[ ]+th.lbib[ ]+a0,\(a1\),-16,3 +[ ]+[0-9a-f]+:[ ]+9805c50b[ ]+th.lbuia[ ]+a0,\(a1\),0,0 +[ ]+[0-9a-f]+:[ ]+8af5c50b[ ]+th.lbuib[ ]+a0,\(a1\),15,1 +[ ]+[0-9a-f]+:[ ]+7905d50b[ ]+th.sdia[ ]+a0,\(a1\),-16,0 +[ ]+[0-9a-f]+:[ ]+6bf5d50b[ ]+th.sdib[ ]+a0,\(a1\),-1,1 +[ ]+[0-9a-f]+:[ ]+5c05d50b[ ]+th.swia[ ]+a0,\(a1\),0,2 +[ ]+[0-9a-f]+:[ ]+4e15d50b[ ]+th.swib[ ]+a0,\(a1\),1,3 +[ ]+[0-9a-f]+:[ ]+3845d50b[ ]+th.shia[ ]+a0,\(a1\),4,0 +[ ]+[0-9a-f]+:[ ]+2ad5d50b[ ]+th.shib[ ]+a0,\(a1\),13,1 +[ ]+[0-9a-f]+:[ ]+1ce5d50b[ ]+th.sbia[ ]+a0,\(a1\),14,2 +[ ]+[0-9a-f]+:[ ]+0ef5d50b[ ]+th.sbib[ ]+a0,\(a1\),15,3 +[ ]+[0-9a-f]+:[ ]+60c5c50b[ ]+th.lrd[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+42c5c50b[ ]+th.lrw[ ]+a0,a1,a2,1 +[ ]+[0-9a-f]+:[ ]+c4c5c50b[ ]+th.lrwu[ ]+a0,a1,a2,2 +[ ]+[0-9a-f]+:[ ]+26c5c50b[ ]+th.lrh[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+a0c5c50b[ ]+th.lrhu[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+02c5c50b[ ]+th.lrb[ ]+a0,a1,a2,1 +[ ]+[0-9a-f]+:[ ]+84c5c50b[ ]+th.lrbu[ ]+a0,a1,a2,2 +[ ]+[0-9a-f]+:[ ]+66c5d50b[ ]+th.srd[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+40c5d50b[ ]+th.srw[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+22c5d50b[ ]+th.srh[ ]+a0,a1,a2,1 +[ ]+[0-9a-f]+:[ ]+04c5d50b[ ]+th.srb[ ]+a0,a1,a2,2 +[ ]+[0-9a-f]+:[ ]+70c5c50b[ ]+th.lurd[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+52c5c50b[ ]+th.lurw[ ]+a0,a1,a2,1 +[ ]+[0-9a-f]+:[ ]+d4c5c50b[ ]+th.lurwu[ ]+a0,a1,a2,2 +[ ]+[0-9a-f]+:[ ]+36c5c50b[ ]+th.lurh[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+b0c5c50b[ ]+th.lurhu[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+12c5c50b[ ]+th.lurb[ ]+a0,a1,a2,1 +[ ]+[0-9a-f]+:[ ]+94c5c50b[ ]+th.lurbu[ ]+a0,a1,a2,2 +[ ]+[0-9a-f]+:[ ]+76c5d50b[ ]+th.surd[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+50c5d50b[ ]+th.surw[ ]+a0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+32c5d50b[ ]+th.surh[ ]+a0,a1,a2,1 +[ ]+[0-9a-f]+:[ ]+14c5d50b[ ]+th.surb[ ]+a0,a1,a2,2 diff --git a/gas/testsuite/gas/riscv/x-thead-memidx.s b/gas/testsuite/gas/riscv/x-thead-memidx.s new file mode 100644 index 00000000000..ef3907cf9af --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-memidx.s @@ -0,0 +1,48 @@ +target: + th.ldia a0, (a1), 0, 0 + th.ldib a0, (a1), 15, 1 + th.lwia a0, (a1), 0, 2 + th.lwib a0, (a1), -16, 3 + th.lwuia a0, (a1), 0, 0 + th.lwuib a0, (a1), 15, 1 + th.lhia a0, (a1), 0, 2 + th.lhib a0, (a1), -16, 3 + th.lhuia a0, (a1), 0, 0 + th.lhuib a0, (a1), 15, 1 + th.lbia a0, (a1), 0, 2 + th.lbib a0, (a1), -16, 3 + th.lbuia a0, (a1), 0, 0 + th.lbuib a0, (a1), 15, 1 + + th.sdia a0, (a1), -16, 0 + th.sdib a0, (a1), -1, 1 + th.swia a0, (a1), 0, 2 + th.swib a0, (a1), 1, 3 + th.shia a0, (a1), 4, 0 + th.shib a0, (a1), 13, 1 + th.sbia a0, (a1), 14, 2 + th.sbib a0, (a1), 15, 3 + + th.lrd a0, a1, a2, 0 + th.lrw a0, a1, a2, 1 + th.lrwu a0, a1, a2, 2 + th.lrh a0, a1, a2, 3 + th.lrhu a0, a1, a2, 0 + th.lrb a0, a1, a2, 1 + th.lrbu a0, a1, a2, 2 + th.srd a0, a1, a2, 3 + th.srw a0, a1, a2, 0 + th.srh a0, a1, a2, 1 + th.srb a0, a1, a2, 2 + + th.lurd a0, a1, a2, 0 + th.lurw a0, a1, a2, 1 + th.lurwu a0, a1, a2, 2 + th.lurh a0, a1, a2, 3 + th.lurhu a0, a1, a2, 0 + th.lurb a0, a1, a2, 1 + th.lurbu a0, a1, a2, 2 + th.surd a0, a1, a2, 3 + th.surw a0, a1, a2, 0 + th.surh a0, a1, a2, 1 + th.surb a0, a1, a2, 2 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index ecba9f51c84..ab87be248f4 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2216,6 +2216,95 @@ #define MASK_TH_MULSH 0xfe00707f #define MATCH_TH_MULSW 0x2600100b #define MASK_TH_MULSW 0xfe00707f +/* Vendor-specific (T-Head) XTheadMemIdx instructions. */ +#define MATCH_TH_LDIA 0x7800400b +#define MASK_TH_LDIA 0xf800707f +#define MATCH_TH_LDIB 0x6800400b +#define MASK_TH_LDIB 0xf800707f +#define MATCH_TH_LWIA 0x5800400b +#define MASK_TH_LWIA 0xf800707f +#define MATCH_TH_LWIB 0x4800400b +#define MASK_TH_LWIB 0xf800707f +#define MATCH_TH_LWUIA 0xd800400b +#define MASK_TH_LWUIA 0xf800707f +#define MATCH_TH_LWUIB 0xc800400b +#define MASK_TH_LWUIB 0xf800707f +#define MATCH_TH_LHIA 0x3800400b +#define MASK_TH_LHIA 0xf800707f +#define MATCH_TH_LHIB 0x2800400b +#define MASK_TH_LHIB 0xf800707f +#define MATCH_TH_LHUIA 0xb800400b +#define MASK_TH_LHUIA 0xf800707f +#define MATCH_TH_LHUIB 0xa800400b +#define MASK_TH_LHUIB 0xf800707f +#define MATCH_TH_LBIA 0x1800400b +#define MASK_TH_LBIA 0xf800707f +#define MATCH_TH_LBIB 0x0800400b +#define MASK_TH_LBIB 0xf800707f +#define MATCH_TH_LBUIA 0x9800400b +#define MASK_TH_LBUIA 0xf800707f +#define MATCH_TH_LBUIB 0x8800400b +#define MASK_TH_LBUIB 0xf800707f +#define MATCH_TH_SDIA 0x7800500b +#define MASK_TH_SDIA 0xf800707f +#define MATCH_TH_SDIB 0x6800500b +#define MASK_TH_SDIB 0xf800707f +#define MATCH_TH_SWIA 0x5800500b +#define MASK_TH_SWIA 0xf800707f +#define MATCH_TH_SWIB 0x4800500b +#define MASK_TH_SWIB 0xf800707f +#define MATCH_TH_SHIA 0x3800500b +#define MASK_TH_SHIA 0xf800707f +#define MATCH_TH_SHIB 0x2800500b +#define MASK_TH_SHIB 0xf800707f +#define MATCH_TH_SBIA 0x1800500b +#define MASK_TH_SBIA 0xf800707f +#define MATCH_TH_SBIB 0x0800500b +#define MASK_TH_SBIB 0xf800707f +#define MATCH_TH_LRD 0x6000400b +#define MASK_TH_LRD 0xf800707f +#define MATCH_TH_LRW 0x4000400b +#define MASK_TH_LRW 0xf800707f +#define MATCH_TH_LRWU 0xc000400b +#define MASK_TH_LRWU 0xf800707f +#define MATCH_TH_LRH 0x2000400b +#define MASK_TH_LRH 0xf800707f +#define MATCH_TH_LRHU 0xa000400b +#define MASK_TH_LRHU 0xf800707f +#define MATCH_TH_LRB 0x0000400b +#define MASK_TH_LRB 0xf800707f +#define MATCH_TH_LRBU 0x8000400b +#define MASK_TH_LRBU 0xf800707f +#define MATCH_TH_SRD 0x6000500b +#define MASK_TH_SRD 0xf800707f +#define MATCH_TH_SRW 0x4000500b +#define MASK_TH_SRW 0xf800707f +#define MATCH_TH_SRH 0x2000500b +#define MASK_TH_SRH 0xf800707f +#define MATCH_TH_SRB 0x0000500b +#define MASK_TH_SRB 0xf800707f +#define MATCH_TH_LURD 0x7000400b +#define MASK_TH_LURD 0xf800707f +#define MATCH_TH_LURW 0x5000400b +#define MASK_TH_LURW 0xf800707f +#define MATCH_TH_LURWU 0xd000400b +#define MASK_TH_LURWU 0xf800707f +#define MATCH_TH_LURH 0x3000400b +#define MASK_TH_LURH 0xf800707f +#define MATCH_TH_LURHU 0xb000400b +#define MASK_TH_LURHU 0xf800707f +#define MATCH_TH_LURB 0x1000400b +#define MASK_TH_LURB 0xf800707f +#define MATCH_TH_LURBU 0x9000400b +#define MASK_TH_LURBU 0xf800707f +#define MATCH_TH_SURD 0x7000500b +#define MASK_TH_SURD 0xf800707f +#define MATCH_TH_SURW 0x5000500b +#define MASK_TH_SURW 0xf800707f +#define MATCH_TH_SURH 0x3000500b +#define MASK_TH_SURH 0xf800707f +#define MATCH_TH_SURB 0x1000500b +#define MASK_TH_SURB 0xf800707f /* Vendor-specific (T-Head) XTheadSync instructions. */ #define MATCH_TH_SFENCE_VMAS 0x0400000b #define MASK_TH_SFENCE_VMAS 0xfe007fff @@ -3021,6 +3110,51 @@ DECLARE_INSN(th_mulaw, MATCH_TH_MULAW, MASK_TH_MULAW) DECLARE_INSN(th_muls, MATCH_TH_MULS, MASK_TH_MULS) DECLARE_INSN(th_mulsh, MATCH_TH_MULSH, MASK_TH_MULSH) DECLARE_INSN(th_mulsw, MATCH_TH_MULSW, MASK_TH_MULSW) +/* Vendor-specific (T-Head) XTheadMemIdx instructions. */ +DECLARE_INSN(th_ldia, MATCH_TH_LDIA, MASK_TH_LDIA) +DECLARE_INSN(th_ldib, MATCH_TH_LDIB, MASK_TH_LDIB) +DECLARE_INSN(th_lwia, MATCH_TH_LWIA, MASK_TH_LWIA) +DECLARE_INSN(th_lwib, MATCH_TH_LWIB, MASK_TH_LWIB) +DECLARE_INSN(th_lwuia, MATCH_TH_LWUIA, MASK_TH_LWUIA) +DECLARE_INSN(th_lwuib, MATCH_TH_LWUIB, MASK_TH_LWUIB) +DECLARE_INSN(th_lhia, MATCH_TH_LHIA, MASK_TH_LHIA) +DECLARE_INSN(th_lhib, MATCH_TH_LHIB, MASK_TH_LHIB) +DECLARE_INSN(th_lhuia, MATCH_TH_LHUIA, MASK_TH_LHUIA) +DECLARE_INSN(th_lhuib, MATCH_TH_LHUIB, MASK_TH_LHUIB) +DECLARE_INSN(th_lbia, MATCH_TH_LBIA, MASK_TH_LBIA) +DECLARE_INSN(th_lbib, MATCH_TH_LBIB, MASK_TH_LBIB) +DECLARE_INSN(th_lbuia, MATCH_TH_LBUIA, MASK_TH_LBUIA) +DECLARE_INSN(th_lbuib, MATCH_TH_LBUIB, MASK_TH_LBUIB) +DECLARE_INSN(th_sdia, MATCH_TH_SDIA, MASK_TH_SDIA) +DECLARE_INSN(th_sdib, MATCH_TH_SDIB, MASK_TH_SDIB) +DECLARE_INSN(th_swia, MATCH_TH_SWIA, MASK_TH_SWIA) +DECLARE_INSN(th_swib, MATCH_TH_SWIB, MASK_TH_SWIB) +DECLARE_INSN(th_shia, MATCH_TH_SHIA, MASK_TH_SHIA) +DECLARE_INSN(th_shib, MATCH_TH_SHIB, MASK_TH_SHIB) +DECLARE_INSN(th_sbia, MATCH_TH_SBIA, MASK_TH_SBIA) +DECLARE_INSN(th_sbib, MATCH_TH_SBIB, MASK_TH_SBIB) +DECLARE_INSN(th_lrd, MATCH_TH_LRD, MASK_TH_LRD) +DECLARE_INSN(th_lrw, MATCH_TH_LRW, MASK_TH_LRW) +DECLARE_INSN(th_lrwu, MATCH_TH_LRWU, MASK_TH_LRWU) +DECLARE_INSN(th_lrh, MATCH_TH_LRH, MASK_TH_LRH) +DECLARE_INSN(th_lrhu, MATCH_TH_LRHU, MASK_TH_LRHU) +DECLARE_INSN(th_lrb, MATCH_TH_LRB, MASK_TH_LRB) +DECLARE_INSN(th_lrbu, MATCH_TH_LRBU, MASK_TH_LRBU) +DECLARE_INSN(th_srd, MATCH_TH_SRD, MASK_TH_SRD) +DECLARE_INSN(th_srw, MATCH_TH_SRW, MASK_TH_SRW) +DECLARE_INSN(th_srh, MATCH_TH_SRH, MASK_TH_SRH) +DECLARE_INSN(th_srb, MATCH_TH_SRB, MASK_TH_SRB) +DECLARE_INSN(th_lurd, MATCH_TH_LURD, MASK_TH_LURD) +DECLARE_INSN(th_lurw, MATCH_TH_LURW, MASK_TH_LURW) +DECLARE_INSN(th_lurwu, MATCH_TH_LURWU, MASK_TH_LURWU) +DECLARE_INSN(th_lurh, MATCH_TH_LURH, MASK_TH_LURH) +DECLARE_INSN(th_lurhu, MATCH_TH_LURHU, MASK_TH_LURHU) +DECLARE_INSN(th_lurb, MATCH_TH_LURB, MASK_TH_LURB) +DECLARE_INSN(th_lurbu, MATCH_TH_LURBU, MASK_TH_LURBU) +DECLARE_INSN(th_surd, MATCH_TH_SURD, MASK_TH_SURD) +DECLARE_INSN(th_surw, MATCH_TH_SURW, MASK_TH_SURW) +DECLARE_INSN(th_surh, MATCH_TH_SURH, MASK_TH_SURH) +DECLARE_INSN(th_surb, MATCH_TH_SURB, MASK_TH_SURB) /* Vendor-specific (T-Head) XTheadSync instructions. */ DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS) DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 1b7de3cb142..2546d6ce8d5 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -422,6 +422,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADCONDMOV, INSN_CLASS_XTHEADFMEMIDX, INSN_CLASS_XTHEADMAC, + INSN_CLASS_XTHEADMEMIDX, INSN_CLASS_XTHEADSYNC, }; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 6c1c4c9a1ad..5aed98c1003 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -266,6 +266,18 @@ match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op, return match_opcode (op, insn) && vd == vs1 && vs1 == vs2; } +static int +match_th_load_inc(const struct riscv_opcode *op, + insn_t insn) +{ + /* Load-increment has the following restriction: + * The values of rd and rs1 must not be the same. */ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + + return rd != rs1 && match_opcode (op, insn); +} + const struct riscv_opcode riscv_opcodes[] = { /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ @@ -1881,6 +1893,54 @@ const struct riscv_opcode riscv_opcodes[] = {"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0}, {"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadMemIdx instructions. */ +{"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, 0}, +{"th.ldib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIB, MASK_TH_LDIB, match_th_load_inc, 0}, +{"th.lwia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LWIA, MASK_TH_LWIA, match_th_load_inc, 0}, +{"th.lwib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LWIB, MASK_TH_LWIB, match_th_load_inc, 0}, +{"th.lwuia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LWUIA, MASK_TH_LWUIA, match_th_load_inc, 0}, +{"th.lwuib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LWUIB, MASK_TH_LWUIB, match_th_load_inc, 0}, +{"th.lhia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LHIA, MASK_TH_LHIA, match_th_load_inc, 0}, +{"th.lhib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LHIB, MASK_TH_LHIB, match_th_load_inc, 0}, +{"th.lhuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LHUIA, MASK_TH_LHUIA, match_th_load_inc, 0}, +{"th.lhuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LHUIB, MASK_TH_LHUIB, match_th_load_inc, 0}, +{"th.lbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LBIA, MASK_TH_LBIA, match_th_load_inc, 0}, +{"th.lbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LBIB, MASK_TH_LBIB, match_th_load_inc, 0}, +{"th.lbuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LBUIA, MASK_TH_LBUIA, match_th_load_inc, 0}, +{"th.lbuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LBUIB, MASK_TH_LBUIB, match_th_load_inc, 0}, +{"th.sdia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SDIA, MASK_TH_SDIA, match_opcode, 0}, +{"th.sdib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SDIB, MASK_TH_SDIB, match_opcode, 0}, +{"th.swia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SWIA, MASK_TH_SWIA, match_opcode, 0}, +{"th.swib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SWIB, MASK_TH_SWIB, match_opcode, 0}, +{"th.shia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SHIA, MASK_TH_SHIA, match_opcode, 0}, +{"th.shib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SHIB, MASK_TH_SHIB, match_opcode, 0}, +{"th.sbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SBIA, MASK_TH_SBIA, match_opcode, 0}, +{"th.sbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SBIB, MASK_TH_SBIB, match_opcode, 0}, + +{"th.lrd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRD, MASK_TH_LRD, match_opcode, 0}, +{"th.lrw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRW, MASK_TH_LRW, match_opcode, 0}, +{"th.lrwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRWU, MASK_TH_LRWU, match_opcode, 0}, +{"th.lrh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRH, MASK_TH_LRH, match_opcode, 0}, +{"th.lrhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRHU, MASK_TH_LRHU, match_opcode, 0}, +{"th.lrb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRB, MASK_TH_LRB, match_opcode, 0}, +{"th.lrbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRBU, MASK_TH_LRBU, match_opcode, 0}, +{"th.srd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SRD, MASK_TH_SRD, match_opcode, 0}, +{"th.srw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SRW, MASK_TH_SRW, match_opcode, 0}, +{"th.srh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SRH, MASK_TH_SRH, match_opcode, 0}, +{"th.srb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SRB, MASK_TH_SRB, match_opcode, 0}, + +{"th.lurd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURD, MASK_TH_LURD, match_opcode, 0}, +{"th.lurw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURW, MASK_TH_LURW, match_opcode, 0}, +{"th.lurwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURWU, MASK_TH_LURWU, match_opcode, 0}, +{"th.lurh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURH, MASK_TH_LURH, match_opcode, 0}, +{"th.lurhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURHU, MASK_TH_LURHU, match_opcode, 0}, +{"th.lurb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURB, MASK_TH_LURB, match_opcode, 0}, +{"th.lurbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURBU, MASK_TH_LURBU, match_opcode, 0}, +{"th.surd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURD, MASK_TH_SURD, match_opcode, 0}, +{"th.surw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURW, MASK_TH_SURW, match_opcode, 0}, +{"th.surh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURH, MASK_TH_SURH, match_opcode, 0}, +{"th.surb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURB, MASK_TH_SURB, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadMac instructions. */ {"th.mula", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA, MASK_TH_MULA, match_opcode, 0}, {"th.mulah", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAH, MASK_TH_MULAH, match_opcode, 0}, -- 2.37.2
From: Christoph Müllner <christoph.muellner@vrull.eu> This patch introduces support for arbitrary literal instruction arguments, that are not encoded in the opcode. A typical use case for this feature would be an instruction that applies an implicit shift by a constant value on an immediate (that is a real operand). With this patch it is possible to make this shift visible in the dissasembly and support such artificial parameter as part of the asssembly code. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- gas/config/tc-riscv.c | 10 ++++++++++ opcodes/riscv-dis.c | 9 +++++++++ 2 files changed, 19 insertions(+) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 694d079863d..c8bee193730 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1265,6 +1265,9 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) switch (*++oparg) { + case 'l': /* Literal. */ + oparg += strcspn(oparg, ",") - 1; + break; case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ goto use_imm; case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ @@ -3300,6 +3303,13 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, switch (*++oparg) { + case 'l': /* Literal. */ + n = strcspn (++oparg, ","); + if (strncmp (oparg, asarg, n)) + as_bad (_("unexpected literal (%s)"), asarg); + oparg += n - 1; + asarg += n; + continue; case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ sign = true; goto parse_imm; diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index c6ddea16dda..bc8588522d5 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -571,6 +571,15 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info switch (*++oparg) { + case 'l': /* Literal. */ + oparg++; + while (*oparg && *oparg != ',') + { + print (info->stream, dis_style_text, "%c", *oparg); + oparg++; + } + oparg--; + break; case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ sign = true; goto print_imm; -- 2.37.2
From: Christoph Müllner <christoph.muellner@vrull.eu> T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadMemPair extension, a collection of T-Head specific two-GP-register memory operations. The 'th' prefix and the "XTheadMemPair" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> --- bfd/elfxx-riscv.c | 5 ++++ gas/doc/c-riscv.texi | 5 ++++ .../gas/riscv/x-thead-mempair-fail.d | 3 ++ .../gas/riscv/x-thead-mempair-fail.l | 30 +++++++++++++++++++ .../gas/riscv/x-thead-mempair-fail.s | 30 +++++++++++++++++++ gas/testsuite/gas/riscv/x-thead-mempair.d | 14 +++++++++ gas/testsuite/gas/riscv/x-thead-mempair.s | 6 ++++ include/opcode/riscv-opc.h | 17 +++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 24 +++++++++++++++ 10 files changed, 135 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.s create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.d create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index caa690913f0..82e0c519507 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1231,6 +1231,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadfmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadmempair", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2410,6 +2411,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadmac"); case INSN_CLASS_XTHEADMEMIDX: return riscv_subset_supports (rps, "xtheadmemidx"); + case INSN_CLASS_XTHEADMEMPAIR: + return riscv_subset_supports (rps, "xtheadmempair"); case INSN_CLASS_XTHEADSYNC: return riscv_subset_supports (rps, "xtheadsync"); default: @@ -2555,6 +2558,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadmac"; case INSN_CLASS_XTHEADMEMIDX: return "xtheadmemidx"; + case INSN_CLASS_XTHEADMEMPAIR: + return "xtheadmempair"; case INSN_CLASS_XTHEADSYNC: return "xtheadsync"; default: diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index ed3d98962e4..cc63760cb80 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -744,6 +744,11 @@ The XTheadMemIdx extension provides GPR memory operations. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XTheadMemPair +The XTheadMemPair extension provides two-GP-register memory operations. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. + @item XTheadSync The XTheadSync extension provides instructions for multi-processor synchronization. diff --git a/gas/testsuite/gas/riscv/x-thead-mempair-fail.d b/gas/testsuite/gas/riscv/x-thead-mempair-fail.d new file mode 100644 index 00000000000..e05f370f082 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-mempair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64gc_xtheadmempair +#source: x-thead-mempair-fail.s +#error_output: x-thead-mempair-fail.l diff --git a/gas/testsuite/gas/riscv/x-thead-mempair-fail.l b/gas/testsuite/gas/riscv/x-thead-mempair-fail.l new file mode 100644 index 00000000000..32d98f47501 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-mempair-fail.l @@ -0,0 +1,30 @@ +.*: Assembler messages: +.*: Error: illegal operands `th.ldd a0,a1,\(a2\),0' +.*: Error: illegal operands `th.lwd a0,a1,\(a2\),1' +.*: Error: illegal operands `th.lwud a0,a1,\(a2\),2' +.*: Error: illegal operands `th.sdd a0,a1,\(a2\),3' +.*: Error: illegal operands `th.swd a0,a1,\(a2\),0' + +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: unexpected literal \(3\) + +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: unexpected literal \(4\) + +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: unexpected literal \(4\) + +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: unexpected literal \(3\) + +.*: Error: improper immediate value \(18446744073709551615\) +.*: Error: improper immediate value \(4\) +.*: Error: unexpected literal \(4\) + +.*: Error: illegal operands `th.ldd a0,a0,\(a1\),0' +.*: Error: illegal operands `th.ldd a0,a1,\(a0\),0' +.*: Error: illegal operands `th.ldd a1,a0,\(a0\),0' diff --git a/gas/testsuite/gas/riscv/x-thead-mempair-fail.s b/gas/testsuite/gas/riscv/x-thead-mempair-fail.s new file mode 100644 index 00000000000..5936ea70fed --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-mempair-fail.s @@ -0,0 +1,30 @@ +target: + th.ldd a0, a1, (a2), 0 + th.lwd a0, a1, (a2), 1 + th.lwud a0, a1, (a2), 2 + th.sdd a0, a1, (a2), 3 + th.swd a0, a1, (a2), 0 + + th.ldd a0, a1, (a2), -1, 4 + th.ldd a0, a1, (a2), 4, 4 + th.ldd a0, a1, (a2), 0, 3 + + th.lwd a0, a1, (a2), -1, 3 + th.lwd a0, a1, (a2), 4, 3 + th.lwd a0, a1, (a2), 0, 4 + + th.lwud a0, a1, (a2), -1, 3 + th.lwud a0, a1, (a2), 4, 3 + th.lwud a0, a1, (a2), 0, 4 + + th.sdd a0, a1, (a2), -1, 4 + th.sdd a0, a1, (a2), 4, 4 + th.sdd a0, a1, (a2), 0, 3 + + th.swd a0, a1, (a2), -1, 3 + th.swd a0, a1, (a2), 4, 3 + th.swd a0, a1, (a2), 0, 4 + + th.ldd a0, a0, (a1), 0 + th.ldd a0, a1, (a0), 0 + th.ldd a1, a0, (a0), 0 diff --git a/gas/testsuite/gas/riscv/x-thead-mempair.d b/gas/testsuite/gas/riscv/x-thead-mempair.d new file mode 100644 index 00000000000..8f62044e9b7 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-mempair.d @@ -0,0 +1,14 @@ +#as: -march=rv64gc_xtheadmempair +#source: x-thead-mempair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+f8b6450b[ ]+th.ldd[ ]+a0,a1,\(a2\),0,4 +[ ]+[0-9a-f]+:[ ]+e2b6450b[ ]+th.lwd[ ]+a0,a1,\(a2\),1,3 +[ ]+[0-9a-f]+:[ ]+f4b6450b[ ]+th.lwud[ ]+a0,a1,\(a2\),2,3 +[ ]+[0-9a-f]+:[ ]+feb6550b[ ]+th.sdd[ ]+a0,a1,\(a2\),3,4 +[ ]+[0-9a-f]+:[ ]+e0b6550b[ ]+th.swd[ ]+a0,a1,\(a2\),0,3 diff --git a/gas/testsuite/gas/riscv/x-thead-mempair.s b/gas/testsuite/gas/riscv/x-thead-mempair.s new file mode 100644 index 00000000000..4ee203971fa --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-mempair.s @@ -0,0 +1,6 @@ +target: + th.ldd a0, a1, (a2), 0, 4 + th.lwd a0, a1, (a2), 1, 3 + th.lwud a0, a1, (a2), 2, 3 + th.sdd a0, a1, (a2), 3, 4 + th.swd a0, a1, (a2), 0, 3 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index ab87be248f4..43a6bef5863 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2216,6 +2216,17 @@ #define MASK_TH_MULSH 0xfe00707f #define MATCH_TH_MULSW 0x2600100b #define MASK_TH_MULSW 0xfe00707f +/* Vendor-specific (T-Head) XTheadMemPair instructions. */ +#define MATCH_TH_LDD 0xf800400b +#define MASK_TH_LDD 0xf800707f +#define MATCH_TH_LWD 0xe000400b +#define MASK_TH_LWD 0xf800707f +#define MATCH_TH_LWUD 0xf000400b +#define MASK_TH_LWUD 0xf800707f +#define MATCH_TH_SDD 0xf800500b +#define MASK_TH_SDD 0xf800707f +#define MATCH_TH_SWD 0xe000500b +#define MASK_TH_SWD 0xf800707f /* Vendor-specific (T-Head) XTheadMemIdx instructions. */ #define MATCH_TH_LDIA 0x7800400b #define MASK_TH_LDIA 0xf800707f @@ -3155,6 +3166,12 @@ DECLARE_INSN(th_surd, MATCH_TH_SURD, MASK_TH_SURD) DECLARE_INSN(th_surw, MATCH_TH_SURW, MASK_TH_SURW) DECLARE_INSN(th_surh, MATCH_TH_SURH, MASK_TH_SURH) DECLARE_INSN(th_surb, MATCH_TH_SURB, MASK_TH_SURB) +/* Vendor-specific (T-Head) XTheadMemPair instructions. */ +DECLARE_INSN(th_ldd, MATCH_TH_LDD, MASK_TH_LDD) +DECLARE_INSN(th_lwd, MATCH_TH_LWD, MASK_TH_LWD) +DECLARE_INSN(th_lwud, MATCH_TH_LWUD, MASK_TH_LWUD) +DECLARE_INSN(th_sdd, MATCH_TH_SDD, MASK_TH_SDD) +DECLARE_INSN(th_swd, MATCH_TH_SWD, MASK_TH_SWD) /* Vendor-specific (T-Head) XTheadSync instructions. */ DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS) DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 2546d6ce8d5..1b329ef1557 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -423,6 +423,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADFMEMIDX, INSN_CLASS_XTHEADMAC, INSN_CLASS_XTHEADMEMIDX, + INSN_CLASS_XTHEADMEMPAIR, INSN_CLASS_XTHEADSYNC, }; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 5aed98c1003..c1bcdb7b6b9 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -278,6 +278,23 @@ match_th_load_inc(const struct riscv_opcode *op, return rd != rs1 && match_opcode (op, insn); } +static int +match_th_load_pair(const struct riscv_opcode *op, + insn_t insn) +{ + /* Load pair instructions use the following encoding: + * - rd1 = RD (insn[11:7]) + * - rd2 = RS2 (insn[24:20]) + * - rs = RS1 ([19:15]) + * This function matches if the following restriction is met: + * The values of rd1, rd2, and rs1 must not be the same. */ + int rd1 = (insn & MASK_RD) >> OP_SH_RD; + int rd2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs = (insn & MASK_RS1) >> OP_SH_RS1; + + return rd1 != rd2 && rd1 != rs && rd2 != rs && match_opcode (op, insn); +} + const struct riscv_opcode riscv_opcodes[] = { /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ @@ -1941,6 +1958,13 @@ const struct riscv_opcode riscv_opcodes[] = {"th.surh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURH, MASK_TH_SURH, match_opcode, 0}, {"th.surb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURB, MASK_TH_SURB, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadMemPair instructions. */ +{"th.ldd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", MATCH_TH_LDD, MASK_TH_LDD, match_th_load_pair, 0}, +{"th.lwd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", MATCH_TH_LWD, MASK_TH_LWD, match_th_load_pair, 0}, +{"th.lwud", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", MATCH_TH_LWUD, MASK_TH_LWUD, match_th_load_pair, 0}, +{"th.sdd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", MATCH_TH_SDD, MASK_TH_SDD, match_opcode, 0}, +{"th.swd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", MATCH_TH_SWD, MASK_TH_SWD, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadMac instructions. */ {"th.mula", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA, MASK_TH_MULA, match_opcode, 0}, {"th.mulah", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAH, MASK_TH_MULAH, match_opcode, 0}, -- 2.37.2
On Sun, Sep 18, 2022 at 3:24 PM Christoph Muellner <christoph.muellner@vrull.eu> wrote: > > From: Christoph Müllner <christoph.muellner@vrull.eu> > > This series introduces support for the T-Head vendor extensions, > which are implemented e.g. in the XuanTie C906 and XuanTie C910 > processors: > * XTheadBa > * XTheadBb > * XTheadBs > * XTheadCmo > * XTheadCondMov > * XTheadFMemIdx > * XTheadMac > * XTheadMemIdx > * XTheadMemPair > * XTheadSync > > The xthead* extensions are documented here: > https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf > > The "th." instruction prefix prevents future conflicts with standard > extensions and has been documentented in the RISC-V toolchain conventions: > https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 > > The goal of this patchset is to provide access to these instructions > so that compilers/users can optimize SW accordingly. > > Note, that the T-Head vendor extensions do not contain all > vendor-specific functionality of the T-Head SoCs (e.g. no vendor-specific > CSRs are included). Instead the extensions cover coherent functionality, > that is exposed to S and U mode. > > The patchset attempts to minimize code changes in generic/infrastructure code. > All patches in this series come with tests to avoid future regressions. > > v2: > * Drop -mcpu= support patches > * Add extensions to riscv_multi_subset_supports_ext > * Rename operand 'L' to 'Xl' Thanks for updating these. > Christoph Müllner (11): > RISC-V: Add generic support for vendor extensions > RISC-V: Add T-Head CMO vendor extension > RISC-V: Add T-Head SYNC vendor extension > RISC-V: Add support for arbitrary immediate encoding formats > RISC-V: Add T-Head Bitmanip vendor extension > RISC-V: Add T-Head CondMov vendor extension > RISC-V: Add T-Head MAC vendor extension > RISC-V: Add T-Head FMemIdx vendor extension > RISC-V: Add T-Head MemIdx vendor extension > RISC-V: Add support for literal instruction arguments > RISC-V: Add T-Head MemPair vendor extension Looks good to me, I had heard from many people that we need the support of t-head vendor extensions for al long time, so please commit them if you think it's time. Thanks for all your contribution Nelson > bfd/elfxx-riscv.c | 59 +++- > gas/config/tc-riscv.c | 84 +++++ > gas/doc/c-riscv.texi | 63 ++++ > gas/testsuite/gas/riscv/x-thead-ba-fail.d | 3 + > gas/testsuite/gas/riscv/x-thead-ba-fail.l | 3 + > gas/testsuite/gas/riscv/x-thead-ba-fail.s | 3 + > gas/testsuite/gas/riscv/x-thead-ba.d | 13 + > gas/testsuite/gas/riscv/x-thead-ba.s | 6 + > gas/testsuite/gas/riscv/x-thead-bb-fail.d | 3 + > gas/testsuite/gas/riscv/x-thead-bb-fail.l | 7 + > gas/testsuite/gas/riscv/x-thead-bb-fail.s | 7 + > gas/testsuite/gas/riscv/x-thead-bb.d | 30 ++ > gas/testsuite/gas/riscv/x-thead-bb.s | 22 ++ > gas/testsuite/gas/riscv/x-thead-bs-fail.d | 3 + > gas/testsuite/gas/riscv/x-thead-bs-fail.l | 3 + > gas/testsuite/gas/riscv/x-thead-bs-fail.s | 3 + > gas/testsuite/gas/riscv/x-thead-bs.d | 14 + > gas/testsuite/gas/riscv/x-thead-bs.s | 6 + > gas/testsuite/gas/riscv/x-thead-cmo-fail.d | 3 + > gas/testsuite/gas/riscv/x-thead-cmo-fail.l | 22 ++ > gas/testsuite/gas/riscv/x-thead-cmo-fail.s | 22 ++ > gas/testsuite/gas/riscv/x-thead-cmo.d | 30 ++ > gas/testsuite/gas/riscv/x-thead-cmo.s | 22 ++ > gas/testsuite/gas/riscv/x-thead-condmov.d | 11 + > gas/testsuite/gas/riscv/x-thead-condmov.s | 3 + > .../gas/riscv/x-thead-fmemidx-fail.d | 3 + > .../gas/riscv/x-thead-fmemidx-fail.l | 18 + > .../gas/riscv/x-thead-fmemidx-fail.s | 17 + > gas/testsuite/gas/riscv/x-thead-fmemidx.d | 25 ++ > gas/testsuite/gas/riscv/x-thead-fmemidx.s | 17 + > gas/testsuite/gas/riscv/x-thead-mac.d | 15 + > gas/testsuite/gas/riscv/x-thead-mac.s | 7 + > gas/testsuite/gas/riscv/x-thead-memidx-fail.d | 3 + > gas/testsuite/gas/riscv/x-thead-memidx-fail.l | 14 + > gas/testsuite/gas/riscv/x-thead-memidx-fail.s | 14 + > gas/testsuite/gas/riscv/x-thead-memidx.d | 53 +++ > gas/testsuite/gas/riscv/x-thead-memidx.s | 48 +++ > .../gas/riscv/x-thead-mempair-fail.d | 3 + > .../gas/riscv/x-thead-mempair-fail.l | 30 ++ > .../gas/riscv/x-thead-mempair-fail.s | 30 ++ > gas/testsuite/gas/riscv/x-thead-mempair.d | 14 + > gas/testsuite/gas/riscv/x-thead-mempair.s | 6 + > gas/testsuite/gas/riscv/x-thead-sync-fail.d | 3 + > gas/testsuite/gas/riscv/x-thead-sync-fail.l | 6 + > gas/testsuite/gas/riscv/x-thead-sync-fail.s | 6 + > gas/testsuite/gas/riscv/x-thead-sync.d | 14 + > gas/testsuite/gas/riscv/x-thead-sync.s | 6 + > include/opcode/riscv-opc.h | 326 ++++++++++++++++++ > include/opcode/riscv.h | 27 ++ > opcodes/riscv-dis.c | 43 +++ > opcodes/riscv-opc.c | 155 +++++++++ > 51 files changed, 1346 insertions(+), 2 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.s > > -- > 2.37.2 >
[-- Attachment #1: Type: text/plain, Size: 8844 bytes --] On Thu, Sep 22, 2022 at 3:55 PM Nelson Chu <nelson@rivosinc.com> wrote: > On Sun, Sep 18, 2022 at 3:24 PM Christoph Muellner > <christoph.muellner@vrull.eu> wrote: > > > > From: Christoph Müllner <christoph.muellner@vrull.eu> > > > > This series introduces support for the T-Head vendor extensions, > > which are implemented e.g. in the XuanTie C906 and XuanTie C910 > > processors: > > * XTheadBa > > * XTheadBb > > * XTheadBs > > * XTheadCmo > > * XTheadCondMov > > * XTheadFMemIdx > > * XTheadMac > > * XTheadMemIdx > > * XTheadMemPair > > * XTheadSync > > > > The xthead* extensions are documented here: > > > https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf > > > > The "th." instruction prefix prevents future conflicts with standard > > extensions and has been documentented in the RISC-V toolchain > conventions: > > https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 > > > > The goal of this patchset is to provide access to these instructions > > so that compilers/users can optimize SW accordingly. > > > > Note, that the T-Head vendor extensions do not contain all > > vendor-specific functionality of the T-Head SoCs (e.g. no vendor-specific > > CSRs are included). Instead the extensions cover coherent functionality, > > that is exposed to S and U mode. > > > > The patchset attempts to minimize code changes in generic/infrastructure > code. > > All patches in this series come with tests to avoid future regressions. > > > > v2: > > * Drop -mcpu= support patches > > * Add extensions to riscv_multi_subset_supports_ext > > * Rename operand 'L' to 'Xl' > > Thanks for updating these. > > > Christoph Müllner (11): > > RISC-V: Add generic support for vendor extensions > > RISC-V: Add T-Head CMO vendor extension > > RISC-V: Add T-Head SYNC vendor extension > > RISC-V: Add support for arbitrary immediate encoding formats > > RISC-V: Add T-Head Bitmanip vendor extension > > RISC-V: Add T-Head CondMov vendor extension > > RISC-V: Add T-Head MAC vendor extension > > RISC-V: Add T-Head FMemIdx vendor extension > > RISC-V: Add T-Head MemIdx vendor extension > > RISC-V: Add support for literal instruction arguments > > RISC-V: Add T-Head MemPair vendor extension > > Looks good to me, I had heard from many people that we need the > support of t-head vendor extensions for al long time, so please commit > them if you think it's time. > I don't have write access, but Philipp Tomsich will push changes upstream later today. Thank you for the review! > > Thanks for all your contribution > Nelson > > > bfd/elfxx-riscv.c | 59 +++- > > gas/config/tc-riscv.c | 84 +++++ > > gas/doc/c-riscv.texi | 63 ++++ > > gas/testsuite/gas/riscv/x-thead-ba-fail.d | 3 + > > gas/testsuite/gas/riscv/x-thead-ba-fail.l | 3 + > > gas/testsuite/gas/riscv/x-thead-ba-fail.s | 3 + > > gas/testsuite/gas/riscv/x-thead-ba.d | 13 + > > gas/testsuite/gas/riscv/x-thead-ba.s | 6 + > > gas/testsuite/gas/riscv/x-thead-bb-fail.d | 3 + > > gas/testsuite/gas/riscv/x-thead-bb-fail.l | 7 + > > gas/testsuite/gas/riscv/x-thead-bb-fail.s | 7 + > > gas/testsuite/gas/riscv/x-thead-bb.d | 30 ++ > > gas/testsuite/gas/riscv/x-thead-bb.s | 22 ++ > > gas/testsuite/gas/riscv/x-thead-bs-fail.d | 3 + > > gas/testsuite/gas/riscv/x-thead-bs-fail.l | 3 + > > gas/testsuite/gas/riscv/x-thead-bs-fail.s | 3 + > > gas/testsuite/gas/riscv/x-thead-bs.d | 14 + > > gas/testsuite/gas/riscv/x-thead-bs.s | 6 + > > gas/testsuite/gas/riscv/x-thead-cmo-fail.d | 3 + > > gas/testsuite/gas/riscv/x-thead-cmo-fail.l | 22 ++ > > gas/testsuite/gas/riscv/x-thead-cmo-fail.s | 22 ++ > > gas/testsuite/gas/riscv/x-thead-cmo.d | 30 ++ > > gas/testsuite/gas/riscv/x-thead-cmo.s | 22 ++ > > gas/testsuite/gas/riscv/x-thead-condmov.d | 11 + > > gas/testsuite/gas/riscv/x-thead-condmov.s | 3 + > > .../gas/riscv/x-thead-fmemidx-fail.d | 3 + > > .../gas/riscv/x-thead-fmemidx-fail.l | 18 + > > .../gas/riscv/x-thead-fmemidx-fail.s | 17 + > > gas/testsuite/gas/riscv/x-thead-fmemidx.d | 25 ++ > > gas/testsuite/gas/riscv/x-thead-fmemidx.s | 17 + > > gas/testsuite/gas/riscv/x-thead-mac.d | 15 + > > gas/testsuite/gas/riscv/x-thead-mac.s | 7 + > > gas/testsuite/gas/riscv/x-thead-memidx-fail.d | 3 + > > gas/testsuite/gas/riscv/x-thead-memidx-fail.l | 14 + > > gas/testsuite/gas/riscv/x-thead-memidx-fail.s | 14 + > > gas/testsuite/gas/riscv/x-thead-memidx.d | 53 +++ > > gas/testsuite/gas/riscv/x-thead-memidx.s | 48 +++ > > .../gas/riscv/x-thead-mempair-fail.d | 3 + > > .../gas/riscv/x-thead-mempair-fail.l | 30 ++ > > .../gas/riscv/x-thead-mempair-fail.s | 30 ++ > > gas/testsuite/gas/riscv/x-thead-mempair.d | 14 + > > gas/testsuite/gas/riscv/x-thead-mempair.s | 6 + > > gas/testsuite/gas/riscv/x-thead-sync-fail.d | 3 + > > gas/testsuite/gas/riscv/x-thead-sync-fail.l | 6 + > > gas/testsuite/gas/riscv/x-thead-sync-fail.s | 6 + > > gas/testsuite/gas/riscv/x-thead-sync.d | 14 + > > gas/testsuite/gas/riscv/x-thead-sync.s | 6 + > > include/opcode/riscv-opc.h | 326 ++++++++++++++++++ > > include/opcode/riscv.h | 27 ++ > > opcodes/riscv-dis.c | 43 +++ > > opcodes/riscv-opc.c | 155 +++++++++ > > 51 files changed, 1346 insertions(+), 2 deletions(-) > > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.l > > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.l > > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.l > > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.l > > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l > > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.l > > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.l > > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.l > > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.s > > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.d > > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.s > > > > -- > > 2.37.2 > > >