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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id e24-20020a170906315800b0073d15dfdc09sm13754108eje.11.2022.09.18.00.24.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Sep 2022 00:24:09 -0700 (PDT) From: Christoph Muellner To: binutils@sourceware.org, Nelson Chu , Kito Cheng , Jim Wilson , Philipp Tomsich , Palmer Dabbelt , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v2 10/11] RISC-V: Add support for literal instruction arguments Date: Sun, 18 Sep 2022 09:23:55 +0200 Message-Id: <20220918072356.2496130-11-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220918072356.2496130-1-christoph.muellner@vrull.eu> References: <20220918072356.2496130-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_MANYTO,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph Müllner This patch introduces support for arbitrary literal instruction arguments, that are not encoded in the opcode. A typical use case for this feature would be an instruction that applies an implicit shift by a constant value on an immediate (that is a real operand). With this patch it is possible to make this shift visible in the dissasembly and support such artificial parameter as part of the asssembly code. Signed-off-by: Christoph Müllner --- gas/config/tc-riscv.c | 10 ++++++++++ opcodes/riscv-dis.c | 9 +++++++++ 2 files changed, 19 insertions(+) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 694d079863d..c8bee193730 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1265,6 +1265,9 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) switch (*++oparg) { + case 'l': /* Literal. */ + oparg += strcspn(oparg, ",") - 1; + break; case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ goto use_imm; case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ @@ -3300,6 +3303,13 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, switch (*++oparg) { + case 'l': /* Literal. */ + n = strcspn (++oparg, ","); + if (strncmp (oparg, asarg, n)) + as_bad (_("unexpected literal (%s)"), asarg); + oparg += n - 1; + asarg += n; + continue; case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ sign = true; goto parse_imm; diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index c6ddea16dda..bc8588522d5 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -571,6 +571,15 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info switch (*++oparg) { + case 'l': /* Literal. */ + oparg++; + while (*oparg && *oparg != ',') + { + print (info->stream, dis_style_text, "%c", *oparg); + oparg++; + } + oparg--; + break; case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ sign = true; goto print_imm; -- 2.37.2