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From: Christoph Muellner <christoph.muellner@vrull.eu>
To: binutils@sourceware.org, Nelson Chu <nelson@rivosinc.com>,
	Kito Cheng <kito.cheng@sifive.com>,
	Jim Wilson <jim.wilson.gcc@gmail.com>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Cooper Qu <cooper.qu@linux.alibaba.com>,
	Lifang Xia <lifang_xia@linux.alibaba.com>,
	Yunhai Shang <yunhai@linux.alibaba.com>,
	Zhiwei Liu <zhiwei_liu@linux.alibaba.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH v2 04/11] RISC-V: Add support for arbitrary immediate encoding formats
Date: Sun, 18 Sep 2022 09:23:49 +0200	[thread overview]
Message-ID: <20220918072356.2496130-5-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20220918072356.2496130-1-christoph.muellner@vrull.eu>

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch introduces support for arbitrary signed or unsigned immediate
encoding formats. The formats have the form "XsN@S" and "XuN@S" with N
being the number of bits and S the LSB position.

For example an immediate field of 5 bytes that encodes a signed value
and is stored in the bits 24-20 of the instruction word can use the
format specifier "Xs5@20".

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gas/config/tc-riscv.c  | 74 ++++++++++++++++++++++++++++++++++++++++++
 include/opcode/riscv.h | 17 ++++++++++
 opcodes/riscv-dis.c    | 34 +++++++++++++++++++
 3 files changed, 125 insertions(+)

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 2f5ee18e451..694d079863d 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -441,6 +441,9 @@ static char *expr_end;
 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
   INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
 
+#define INSERT_IMM(n, s, INSN, VALUE) \
+  INSERT_BITS ((INSN).insn_opcode, VALUE, (1ULL<<n) - 1, s)
+
 /* Determine if an instruction matches an opcode.  */
 #define OPCODE_MATCHES(OPCODE, OP) \
   (((OPCODE) & MASK_##OP) == MATCH_##OP)
@@ -1092,6 +1095,8 @@ arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
 }
 
 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
+#define USE_IMM(n, s) \
+  (used_bits |= ((insn_t)((1ull<<n)-1) << (s)))
 
 /* For consistency checking, verify that all bits are specified either
    by the match/mask part of the instruction definition, or by the
@@ -1253,6 +1258,31 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 		goto unknown_validate_operand;
 	    }
 	  break;
+	case 'X': /* Integer immediate.  */
+	  {
+	    size_t n;
+	    size_t s;
+
+	    switch (*++oparg)
+	      {
+		case 's': /* 'XsN@S' ... N-bit signed immediate at bit S.  */
+		  goto use_imm;
+		case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S.  */
+		  goto use_imm;
+		use_imm:
+		  n = strtol (++oparg, (char **)&oparg, 10);
+		  if (*oparg != '@')
+		    goto unknown_validate_operand;
+		  s = strtol (++oparg, (char **)&oparg, 10);
+		  oparg--;
+
+		  USE_IMM (n, s);
+		  break;
+		default:
+		  goto unknown_validate_operand;
+	      }
+	  }
+	  break;
 	default:
 	unknown_validate_operand:
 	  as_bad (_("internal: bad RISC-V opcode "
@@ -3262,6 +3292,50 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	      asarg = expr_end;
 	      continue;
 
+	    case 'X': /* Integer immediate.  */
+	      {
+		size_t n;
+		size_t s;
+		bool sign;
+
+		switch (*++oparg)
+		  {
+		    case 's': /* 'XsN@S' ... N-bit signed immediate at bit S.  */
+		      sign = true;
+		      goto parse_imm;
+		    case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S.  */
+		      sign = false;
+		      goto parse_imm;
+		    parse_imm:
+		      n = strtol (++oparg, (char **)&oparg, 10);
+		      if (*oparg != '@')
+			goto unknown_riscv_ip_operand;
+		      s = strtol (++oparg, (char **)&oparg, 10);
+		      oparg--;
+
+		      my_getExpression (imm_expr, asarg);
+		      check_absolute_expr (ip, imm_expr, false);
+		      if (!sign)
+			{
+			  if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
+			    as_bad (_("improper immediate value (%lu)"),
+				    (unsigned long) imm_expr->X_add_number);
+			}
+		      else
+			{
+			  if (!VALIDATE_S_IMM (imm_expr->X_add_number, n))
+			    as_bad (_("improper immediate value (%li)"),
+				    (long) imm_expr->X_add_number);
+			}
+		      INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
+		      imm_expr->X_op = O_absent;
+		      asarg = expr_end;
+		      continue;
+		    default:
+		      goto unknown_riscv_ip_operand;
+		  }
+	      }
+	      break;
 	    default:
 	    unknown_riscv_ip_operand:
 	      as_fatal (_("internal: unknown argument type `%s'"),
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 6fdc9c9302e..faef28a3739 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -60,6 +60,7 @@ static const char * const riscv_pred_succ[16] =
 
 #define RV_X(x, s, n)  (((x) >> (s)) & ((1 << (n)) - 1))
 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
+#define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n)))
 
 #define EXTRACT_ITYPE_IMM(x) \
   (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
@@ -347,6 +348,22 @@ static const char * const riscv_pred_succ[16] =
 #define EXTRACT_OPERAND(FIELD, INSN) \
   EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
 
+/* Extract an unsigned immediate operand on position s with n bits.  */
+#define EXTRACT_U_IMM(n, s, l) \
+  RV_X (l, s, n)
+
+/* Extract an signed immediate operand on position s with n bits.  */
+#define EXTRACT_S_IMM(n, s, l) \
+  RV_X_SIGNED (l, s, n)
+
+/* Validate that unsigned n-bit immediate is within bounds.  */
+#define VALIDATE_U_IMM(v, n) \
+  ((unsigned long) v < (1UL << n))
+
+/* Validate that signed n-bit immediate is within bounds.  */
+#define VALIDATE_S_IMM(v, n) \
+  (v < (long) (1UL << (n-1)) && v >= -(offsetT) (1UL << (n-1)))
+
 /* The maximal number of subset can be required.  */
 #define MAX_SUBSET_NUM 4
 
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 7ae6e709290..c6ddea16dda 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -563,7 +563,41 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	  print (info->stream, dis_style_text, "%d", rs1);
 	  break;
 
+	case 'X': /* Integer immediate.  */
+	  {
+	    size_t n;
+	    size_t s;
+	    bool sign;
+
+	    switch (*++oparg)
+	      {
+		case 's': /* 'XsN@S' ... N-bit signed immediate at bit S.  */
+		  sign = true;
+		  goto print_imm;
+		case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S.  */
+		  sign = false;
+		  goto print_imm;
+		print_imm:
+		  n = strtol (++oparg, (char **)&oparg, 10);
+		  if (*oparg != '@')
+		    goto undefined_modifier;
+		  s = strtol (++oparg, (char **)&oparg, 10);
+		  oparg--;
+
+		  if (!sign)
+		    print (info->stream, dis_style_immediate, "%u",
+			   (unsigned)EXTRACT_U_IMM (n, s, l));
+		  else
+		    print (info->stream, dis_style_immediate, "%i",
+			   (unsigned)EXTRACT_S_IMM (n, s, l));
+		  break;
+		default:
+		  goto undefined_modifier;
+	      }
+	  }
+	  break;
 	default:
+	undefined_modifier:
 	  /* xgettext:c-format */
 	  print (info->stream, dis_style_text,
 		 _("# internal error, undefined modifier (%c)"),
-- 
2.37.2


  parent reply	other threads:[~2022-09-18  7:24 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-18  7:23 [PATCH v2 00/11] Add support for the T-Head vendor extensions Christoph Muellner
2022-09-18  7:23 ` [PATCH v2 01/11] RISC-V: Add generic support for " Christoph Muellner
2022-09-18  7:23 ` [PATCH v2 02/11] RISC-V: Add T-Head CMO vendor extension Christoph Muellner
2022-09-18  7:23 ` [PATCH v2 03/11] RISC-V: Add T-Head SYNC " Christoph Muellner
2022-09-18  7:23 ` Christoph Muellner [this message]
2022-09-18  7:23 ` [PATCH v2 05/11] RISC-V: Add T-Head Bitmanip " Christoph Muellner
2022-09-18  7:23 ` [PATCH v2 06/11] RISC-V: Add T-Head CondMov " Christoph Muellner
2022-09-18  7:23 ` [PATCH v2 07/11] RISC-V: Add T-Head MAC " Christoph Muellner
2022-09-18  7:23 ` [PATCH v2 08/11] RISC-V: Add T-Head FMemIdx " Christoph Muellner
2022-09-18  7:23 ` [PATCH v2 09/11] RISC-V: Add T-Head MemIdx " Christoph Muellner
2022-09-18  7:23 ` [PATCH v2 10/11] RISC-V: Add support for literal instruction arguments Christoph Muellner
2022-09-18  7:23 ` [PATCH v2 11/11] RISC-V: Add T-Head MemPair vendor extension Christoph Muellner
2022-09-22 13:55 ` [PATCH v2 00/11] Add support for the T-Head vendor extensions Nelson Chu
2022-09-22 14:06   ` Christoph Müllner

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