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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id u3-20020a05640207c300b00451e3160451sm13381912edy.89.2022.09.18.01.55.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Sep 2022 01:55:55 -0700 (PDT) From: Christoph Muellner To: binutils@sourceware.org, Nelson Chu , Kito Cheng , Jim Wilson , Philipp Tomsich , Palmer Dabbelt , Aaron Durbin , Tsukasa OI Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4] RISC-V: Add Zawrs ISA extension support Date: Sun, 18 Sep 2022 10:55:53 +0200 Message-Id: <20220918085553.2562193-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_MANYTO,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph Müllner This patch adds support for the Zawrs ISA extension ("wrs.nto" and "wrs.sto" instructions). The specification can be found here: https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc Note, that the Zawrs extension is frozen but not ratified yet. v4: * Fix location of added code (follow extension ordering policy) v3: * Fix location of added code (follow extension ordering policy) * Rebase on master (and resolve conflicts) * Drop RFC tag as Zawrs got frozen v2: * Adjustments according to a specification change Signed-off-by: Christoph Müllner --- bfd/elfxx-riscv.c | 5 +++++ gas/testsuite/gas/riscv/zawrs-32.d | 11 +++++++++++ gas/testsuite/gas/riscv/zawrs.d | 11 +++++++++++ gas/testsuite/gas/riscv/zawrs.s | 3 +++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 4 ++++ 7 files changed, 43 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zawrs-32.d create mode 100644 gas/testsuite/gas/riscv/zawrs.d create mode 100644 gas/testsuite/gas/riscv/zawrs.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index e03b312a381..4b27cea3a02 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1162,6 +1162,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2293,6 +2294,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zmmul"); case INSN_CLASS_A: return riscv_subset_supports (rps, "a"); + case INSN_CLASS_ZAWRS: + return riscv_subset_supports (rps, "zawrs"); case INSN_CLASS_F: return riscv_subset_supports (rps, "f"); case INSN_CLASS_D: @@ -2410,6 +2413,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _ ("m' or `zmmul"); case INSN_CLASS_A: return "a"; + case INSN_CLASS_ZAWRS: + return "zawrs"; case INSN_CLASS_F: return "f"; case INSN_CLASS_D: diff --git a/gas/testsuite/gas/riscv/zawrs-32.d b/gas/testsuite/gas/riscv/zawrs-32.d new file mode 100644 index 00000000000..32e3a07fb3a --- /dev/null +++ b/gas/testsuite/gas/riscv/zawrs-32.d @@ -0,0 +1,11 @@ +#as: -march=rv32i_zawrs +#source: zawrs.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+00d00073[ ]+wrs.nto +[ ]+[0-9a-f]+:[ ]+01d00073[ ]+wrs.sto diff --git a/gas/testsuite/gas/riscv/zawrs.d b/gas/testsuite/gas/riscv/zawrs.d new file mode 100644 index 00000000000..9fe44f7e359 --- /dev/null +++ b/gas/testsuite/gas/riscv/zawrs.d @@ -0,0 +1,11 @@ +#as: -march=rv64i_zawrs +#source: zawrs.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+00d00073[ ]+wrs.nto +[ ]+[0-9a-f]+:[ ]+01d00073[ ]+wrs.sto diff --git a/gas/testsuite/gas/riscv/zawrs.s b/gas/testsuite/gas/riscv/zawrs.s new file mode 100644 index 00000000000..138b7b5ca77 --- /dev/null +++ b/gas/testsuite/gas/riscv/zawrs.s @@ -0,0 +1,3 @@ +target: + wrs.nto + wrs.sto diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 88b8d7ff595..98fe6764ab9 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2113,6 +2113,11 @@ #define MASK_CBO_INVAL 0xfff07fff #define MATCH_CBO_ZERO 0x40200f #define MASK_CBO_ZERO 0xfff07fff +/* Zawrs intructions. */ +#define MATCH_WRS_NTO 0x00d00073 +#define MASK_WRS_NTO 0xffffffff +#define MATCH_WRS_STO 0x01d00073 +#define MASK_WRS_STO 0xffffffff /* Unprivileged Counter/Timers CSR addresses. */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 @@ -2852,6 +2857,9 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN); DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH); DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL); DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO); +/* Zawrs instructions. */ +DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) +DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) #endif /* DECLARE_INSN */ #ifdef DECLARE_CSR /* Unprivileged Counter/Timers CSRs. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f1dabeaab8e..7a42a48ba7d 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -368,6 +368,7 @@ enum riscv_insn_class INSN_CLASS_ZIFENCEI, INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_ZMMUL, + INSN_CLASS_ZAWRS, INSN_CLASS_F_OR_ZFINX, INSN_CLASS_D_OR_ZDINX, INSN_CLASS_Q_OR_ZQINX, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 79be78eb367..0ea0f77a2d4 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -921,6 +921,10 @@ const struct riscv_opcode riscv_opcodes[] = {"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 }, {"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 }, +/* Zawrs instructions. */ +{"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 }, +{"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 }, + /* Zbb or zbkb instructions. */ {"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 }, {"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 }, -- 2.37.2