From: zengxiao@eswincomputing.com
To: binutils@sourceware.org
Cc: zhengyu@eswincomputing.com, jinyanjiang@eswincomputing.com,
cri-sw-toolchain@eswincomputing.com,
zengxiao <zengxiao@eswincomputing.com>,
gaofei@eswincomputing.com
Subject: [PATCH 1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard
Date: Fri, 14 Oct 2022 14:35:20 +0800 [thread overview]
Message-ID: <20221014063520.1428330-2-zengxiao@eswincomputing.com> (raw)
In-Reply-To: <20221014063520.1428330-1-zengxiao@eswincomputing.com>
From: zengxiao <zengxiao@eswincomputing.com>
This patch makes R_RISCV_SUB6 conforms to riscv abi standard.
R_RISCV_SUB6 only the lower 6 bits of the code are valid.
The proposed specification which can be found in 8.5. Relocations of,
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/download/v1.0-rc4/riscv-abi.pdf
bfd/ChangeLog:
* elfxx-riscv.c (riscv_elf_add_sub_reloc): Take the lower
6 bits as the significant bit
reviewed-by: gaofei@eswincomputing.com
jinyanjiang@eswincomputing.com
Signed-off-by: zengxiao <zengxiao@eswincomputing.com>
---
bfd/elfxx-riscv.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index f0c91cc97f7..0fbfedd17fe 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -994,6 +994,13 @@ riscv_elf_add_sub_reloc (bfd *abfd,
relocation = old_value + relocation;
break;
case R_RISCV_SUB6:
+ {
+ bfd_vma six_bit_valid_value = old_value & howto->dst_mask;
+ six_bit_valid_value -= relocation;
+ relocation = (six_bit_valid_value & howto->dst_mask) |
+ (old_value & ~howto->dst_mask);
+ }
+ break;
case R_RISCV_SUB8:
case R_RISCV_SUB16:
case R_RISCV_SUB32:
--
2.34.1
next prev parent reply other threads:[~2022-10-14 6:35 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-14 6:35 [PATCH 0/1] " zengxiao
2022-10-14 6:35 ` zengxiao [this message]
2022-11-11 15:32 Re:[PATCH 1/1] " shihua
2022-11-18 4:59 ` Palmer Dabbelt
2022-11-18 8:33 ` [PATCH " Nelson Chu
2022-11-21 10:51 ` Xiao Zeng
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