From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id CCAE63858D3C for ; Wed, 19 Oct 2022 14:56:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CCAE63858D3C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666191374; x=1697727374; h=from:to:cc:subject:date:message-id; bh=fPkottVXjPzkOdikxrReqJg3sroVY7b+nrd27PI74V4=; b=Qib3vtSWmVDPBXywFAu9ofO+ww5V0RwRArc0dJsiqfSmOQyPgaEF+0bM KOYo4LgdzjBHn4p+BErNPXAr4+01OqJKUfOjxp/pJ7a1DJY5hJLSa9qiL +YgNC0oyUEaj0Tx1uQwmYECDhnDajut/+WUYCK2Qk1wxl49vog+21cjxQ sIDGLxm67UntkRz0HZ5PQHTba2zVVeitYFwe+eNQ+9QNcDVBYb+usfGx/ hV7mE9Lnw9lrWhCYPQf9TbYM1Bq0AoxoI9dk52meG5x55uUvPs8rWC8kq 2LP57n2Nq02sldSYB8Nuknt7pWmd4OfD/o2840as15yeZra4kZwsN34BZ A==; X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="289749448" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="289749448" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 07:56:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="804336371" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="804336371" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga005.jf.intel.com with ESMTP; 19 Oct 2022 07:56:11 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id AD9BB100511A; Wed, 19 Oct 2022 22:56:10 +0800 (CST) From: Haochen Jiang To: binutils@sourceware.org Cc: jbeulich@suse.com, hjl.tools@gmail.com Subject: [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Date: Wed, 19 Oct 2022 22:55:58 +0800 Message-Id: <20221019145608.45213-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi all, This is our v2 patches for newly released Intel Architecture Instruction Set Extensions and Future Features. The document comes following: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html The changes we HAVEN'T DONE: 1. All the reviews in AVX-NE-CONVERT, RAO-INT, PREFETCHI. The patch owner for AVX-NE-CONVERT and RAO-INT is currently busy with the GCC patches adjustment for these two ISAs and haven't finished the change yet. We will update that in next version. For PREFETCHI, since it is quite special, some more discussion is welcomed before further change. For these three patches, there might have some general changes and will be mentioned below. 2. The Suffix things in CMPccXADD. We have inconsistency for No_Suf usage for CMPccXADD and RAO-INT. We will align them in next version. The changes we HAVE DONE: 1. The AVX2 prereq for AVX-IFMA and AVX-VNNI-INT8. 2. The changes from ANY_xxx to xxx for CMPccXADD, WRMSRNS, MSRLIST. It is very unlikely for these three ISAs have future ISAs that depend on them. Therefore, I changed ANY_xxx to xxx. For other ISAs, we keep the ANY_xxx since we suppose there might be dependency on them. But it still need discussion. There is potential we will remove some of them in v3 (most likely AMX-FP16 and PREFETCHI). And we haven't removed those flags in i386-gen.c. It seems that we could also safely remove them right? 3. Removed lockbad testcases in WRMSRNS, MSRLIST, PREFETCHI. Since most of the insts are lockbad, the testcases in these three patches are not needed. 4. Combined CMPccXADD insts in i386-opc.tbl. Use to combine them, also include those alias not is documentation. Including them is better for developer to use them. 5. Changes in tables due to folding AVXVNNI entry patch. 6. Correct the wrong comment for CpuUnused in CMPccXADD patch and add missing comma for SUBARCH in that patch. 7. Fix in comments for singular, VexVVVV=1 to VexVVVV, Vex128 to Vex. 8. Removal for ALL noxxx things in texi file. The reviews need further discussion/investigation: 1. PseudoVexPrefix related ISAs. 2. Table combination and usage in CMPccXADD. Need further investigation how we could make it simpler. And I haven't investigated whether OP_M usage can save the modrm_table pass. 3. SwapSources in CMPccXADD. We may need a special identifier for CMPccXADD since we have VVVV at operand 3, where it is always at operand 2 for all other insts which have VVVV. That is the reason we reuse SwapSources. It might be not that same as the original meaning. But we want to avoid adding a bit for this very rare case. Do we need to change that? 4. The replacement from _ to - in i386-opc.tbl comments. It seems that recent ISA patches are mostly using _. So I am confused about that. 5. Testcase for WRMSRNS and MSRLIST. The 32bit and 64bit can be shared as mentioned. But we cannot just remove one of them right? All the above are the changes in V2 patch. If there is something missing, just remind us. Thx, Haochen