From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id D018E3857831 for ; Wed, 19 Oct 2022 15:17:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D018E3857831 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666192667; x=1697728667; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=eS4HQcTCGlEgIuTvvsu3FBb4eCBUJYK9g7XWW06llFo=; b=ezHDjOQg9ylMJRxmzvtnyhNXIy9Jtg6xLN2nFSwLdFktEOwoq9DGvbwO GvEnmEOxOv/QcYUM8NXORzXMiFX7ku+cUJKE5ZMYvoPV9OiKOmUkzC8+A q7uDhAbq6/rpRdap1VM4j/aiTEXtLPVQiEx/g0xTnpQpsb3nQBOfmNUlL aToZUVhLGd3nWeSSvTy92d/vN4f4qFcFyiXPb/GXm3YtqhW7RUJk7uc1H fdzU+Jdw/Z/LsMgPpBaoZUDVoUganfb9kWH3x7KSpItFMNs5heXIcJHJl QzzBMion1YxWkU/tbCSHfitEMd64TAFuS0hbpr6lBkReJgWKrWb+0iomO Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="304056039" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="304056039" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 08:17:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="692434888" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="692434888" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga008.fm.intel.com with ESMTP; 19 Oct 2022 08:17:42 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 17C381007834; Wed, 19 Oct 2022 23:17:37 +0800 (CST) From: Haochen Jiang To: binutils@sourceware.org Cc: jbeulich@suse.com, hjl.tools@gmail.com, "Cui, Lili" Subject: [PATCH 10/10] Support Intel PREFETCHI Date: Wed, 19 Oct 2022 23:15:34 +0800 Message-Id: <20221019151534.45521-11-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221019151534.45521-1-haochen.jiang@intel.com> References: <20221019151534.45521-1-haochen.jiang@intel.com> X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: "Cui, Lili" gas/ * NEWS: Add support for Intel PREFETCHI instruction. * config/tc-i386.c: Add prefetchi. * doc/c-i386.texi: Document .prefetchi. * testsuite/gas/i386/i386.exp: Run PREFETCHI tests. * testsuite/gas/i386/x86-64-lfence-load.d: Add PREFETCHI. * testsuite/gas/i386/x86-64-lfence-load.s: Likewise. * testsuite/gas/i386/x86-64-prefetchi-intel.d: New test. * testsuite/gas/i386/x86-64-prefetchi-inval-register.d: Likewise. * testsuite/gas/i386/x86-64-prefetchi-inval-register.s: Likewise. * testsuite/gas/i386/x86-64-prefetchi.d: Likewise. * testsuite/gas/i386/x86-64-prefetchi.s: Likewise. opcodes/ * i386-dis.c (MOD_0F18_REG_6): New. (MOD_0F18_REG_7): Ditto. (X86_64_MOD_0F18_REG_6): Ditto. (X86_64_MOD_0F18_REG_7): Ditto. (x86_64_table): Add X86_64_MOD_0F18_REG_6 and X86_64_MOD_0F18_REG_7. (mod_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7. (PREFETCHI_Fixup): New. * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHI_FLAGS and CPU_ANY_PREFETCHI_FLAGS. (cpu_flags): Add CpuPREFETCHI. * i386-opc.h (CpuPREFETCHI): New. (i386_cpu_flags): Add cpuprefetchi. * i386-opc.tbl: Add Intel PREFETCHI instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. --- gas/NEWS | 2 + gas/config/tc-i386.c | 4 +- gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/i386.exp | 3 + gas/testsuite/gas/i386/x86-64-lfence-load.d | 2 + gas/testsuite/gas/i386/x86-64-lfence-load.s | 2 + .../gas/i386/x86-64-prefetchi-intel.d | 16 + .../i386/x86-64-prefetchi-inval-register.d | 13 + .../i386/x86-64-prefetchi-inval-register.s | 9 + gas/testsuite/gas/i386/x86-64-prefetchi.d | 15 + gas/testsuite/gas/i386/x86-64-prefetchi.s | 14 + opcodes/i386-dis.c | 46 +- opcodes/i386-gen.c | 5 + opcodes/i386-init.h | 524 +- opcodes/i386-opc.h | 3 + opcodes/i386-opc.tbl | 7 + opcodes/i386-tbl.h | 7876 +++++++++-------- 17 files changed, 4362 insertions(+), 4182 deletions(-) create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi.d create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi.s diff --git a/gas/NEWS b/gas/NEWS index 961449545d..5eb479f5a1 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel PREFETCHI instructions. + * Add support for Intel AMX-FP16 instructions. * Add support for Intel MSRLIST instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 906e9db9ad..4312ffb4a9 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] = SUBARCH (raoint, RAOINT, ANY_RAOINT, false), SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false), SUBARCH (msrlist, MSRLIST, MSRLIST, false), + SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false), }; #undef SUBARCH @@ -4522,7 +4523,8 @@ load_insn_p (void) { /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0, prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn, - bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */ + bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote, prefetchit0 + prefetchit1. */ if (i.tm.opcode_modifier.anysize) return 0; diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index b739d5f32e..08fe718de0 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -201,6 +201,7 @@ accept various extension mnemonics. For example, @code{raoint}, @code{wrmsrns}, @code{msrlist}, +@code{prefetchi}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1496,7 +1497,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} @item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert} @item @samp{.cmpccxadd} @tab @samp{.raoint} @tab @samp{.wrmsrns} -@item @samp{.msrlist} +@item @samp{.msrlist} @tab @samp{.prefetchi} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 9f5fa7f612..80bd2835ca 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -1209,6 +1209,9 @@ if [gas_64_check] then { run_dump_test "x86-64-tdx" run_dump_test "x86-64-tsxldtrk" run_dump_test "x86-64-hreset" + run_dump_test "x86-64-prefetchi" + run_dump_test "x86-64-prefetchi-intel" + run_dump_test "x86-64-prefetchi-inval-register" run_dump_test "x86-64-vp2intersect" run_dump_test "x86-64-vp2intersect-intel" run_list_test "x86-64-vp2intersect-inval-bcast" diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.d b/gas/testsuite/gas/i386/x86-64-lfence-load.d index 2af86fc93f..17c3b9f286 100644 --- a/gas/testsuite/gas/i386/x86-64-lfence-load.d +++ b/gas/testsuite/gas/i386/x86-64-lfence-load.d @@ -33,6 +33,8 @@ Disassembly of section .text: +[a-f0-9]+: 0f 18 55 00 prefetcht1 0x0\(%rbp\) +[a-f0-9]+: 0f 18 5d 00 prefetcht2 0x0\(%rbp\) +[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%rbp\) + +[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+> + +[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+> +[a-f0-9]+: 0f a1 pop %fs +[a-f0-9]+: 0f ae e8 lfence +[a-f0-9]+: 9d popf diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.s b/gas/testsuite/gas/i386/x86-64-lfence-load.s index 2a3ac6b7d2..c478082416 100644 --- a/gas/testsuite/gas/i386/x86-64-lfence-load.s +++ b/gas/testsuite/gas/i386/x86-64-lfence-load.s @@ -20,6 +20,8 @@ _start: prefetcht1 (%rbp) prefetcht2 (%rbp) prefetchw (%rbp) + prefetchit0 0x12345678(%rip) + prefetchit1 0x12345678(%rip) pop %fs popf xlatb (%rbx) diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d b/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d new file mode 100644 index 0000000000..7f72f0a1eb --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dwMintel +#name: x86-64 PREFETCHI insns (Intel disassembly) +#source: x86-64-prefetchi.s + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+> +[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+> +[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+> +[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+> +#pass diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d new file mode 100644 index 0000000000..b29b1ae237 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d @@ -0,0 +1,13 @@ +#as: +#objdump: -dw +#name: x86-64 PREFETCHI INVAL REGISTER insns + +.*: +file format .* + + +Disassembly of section .text: + +0+ <\.text>: +[ ]*[a-f0-9]+:[ ]0f 18 39[ ]*nopl \(%rcx\) +[ ]*[a-f0-9]+:[ ]0f 18 31[ ]*nopl \(%rcx\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s new file mode 100644 index 0000000000..550449a0c9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s @@ -0,0 +1,9 @@ +.text + #prefetchit0 (%rcx) PREFETCHIT0/1 apply without RIP-relative addressing, should stay NOPs. + .byte 0x0f + .byte 0x18 + .byte 0x39 + #prefetchit1 (%rcx) PREFETCHIT1/1 apply without RIP-relative addressing, should stay NOPs. + .byte 0x0f + .byte 0x18 + .byte 0x31 diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi.d b/gas/testsuite/gas/i386/x86-64-prefetchi.d new file mode 100644 index 0000000000..c8ab92d147 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-prefetchi.d @@ -0,0 +1,15 @@ +#as: +#objdump: -dw +#name: x86-64 PREFETCHI insns + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+> +[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+> +[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+> +[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+> +#pass diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi.s b/gas/testsuite/gas/i386/x86-64-prefetchi.s new file mode 100644 index 0000000000..cc7c61e9a9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-prefetchi.s @@ -0,0 +1,14 @@ +# Check 64bit PREFETCHI instructions + + .allow_index_reg + .text +_start: + + prefetchit0 0x12345678(%rip) + prefetchit1 0x12345678(%rip) + + .intel_syntax noprefix + + prefetchit0 BYTE PTR [rip+0x12345678] + prefetchit1 BYTE PTR [rip+0x12345678] + diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 60712c7c5b..11a471dd1a 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -114,6 +114,7 @@ static void FXSAVE_Fixup (instr_info *, int, int); static void MOVSXD_Fixup (instr_info *, int, int); static void DistinctDest_Fixup (instr_info *, int, int); +static void PREFETCHI_Fixup (instr_info *, int, int); /* This character is used to encode style information within the output buffers. See oappend_insert_style for more details. */ @@ -841,6 +842,8 @@ enum MOD_0F18_REG_1, MOD_0F18_REG_2, MOD_0F18_REG_3, + MOD_0F18_REG_6, + MOD_0F18_REG_7, MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0, MOD_0F1B_PREFIX_1, @@ -1297,6 +1300,8 @@ enum X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1, X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3, X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1, + X86_64_MOD_0F18_REG_6, + X86_64_MOD_0F18_REG_7, X86_64_0F24, X86_64_0F26, X86_64_0FC7_REG_6_MOD_3_PREFIX_1, @@ -2768,8 +2773,8 @@ static const struct dis386 reg_table[][8] = { { MOD_TABLE (MOD_0F18_REG_3) }, { "nopQ", { Ev }, 0 }, { "nopQ", { Ev }, 0 }, - { "nopQ", { Ev }, 0 }, - { "nopQ", { Ev }, 0 }, + { MOD_TABLE (MOD_0F18_REG_6) }, + { MOD_TABLE (MOD_0F18_REG_7) }, }, /* REG_0F1C_P_0_MOD_0 */ { @@ -4414,6 +4419,18 @@ static const struct dis386 x86_64_table[][2] = { { "psmash", { Skip_MODRM }, 0 }, }, + /* X86_64_MOD_0F18_REG_6 */ + { + { "nopQ", { Ev }, 0 }, + { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 }, + }, + + /* X86_64_MOD_0F18_REG_7 */ + { + { "nopQ", { Ev }, 0 }, + { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 }, + }, + { /* X86_64_0F24 */ { "movZ", { Em, Td }, 0 }, @@ -8213,6 +8230,16 @@ static const struct dis386 mod_table[][2] = { { "prefetcht2", { Mb }, 0 }, { "nopQ", { Ev }, 0 }, }, + { + /* MOD_0F18_REG_6 */ + { X86_64_TABLE (X86_64_MOD_0F18_REG_6) }, + { "nopQ", { Ev }, 0 }, + }, + { + /* MOD_0F18_REG_7 */ + { X86_64_TABLE (X86_64_MOD_0F18_REG_7) }, + { "nopQ", { Ev }, 0 }, + }, { /* MOD_0F1A_PREFIX_0 */ { "bndldx", { Gbnd, Mv_bnd }, 0 }, @@ -14028,3 +14055,18 @@ OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) } oappend (ins, "sae}"); } + +static void +PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag) +{ + if (ins->modrm.mod != 0 || ins->modrm.rm != 5) + { + if (ins->intel_syntax) + ins->mnemonicendp = stpcpy (ins->obuf, "nop "); + else + ins->mnemonicendp = stpcpy (ins->obuf, "nopl "); + bytemode = v_mode; + } + + OP_M (ins, bytemode, sizeflag); +} diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 86383ba793..2ec503aebc 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -259,6 +259,8 @@ static initializer cpu_flag_init[] = "CpuWRMSRNS" }, { "CPU_MSRLIST_FLAGS", "CpuMSRLIST" }, + { "CPU_PREFETCHI_FLAGS", + "CpuPREFETCHI"}, { "CPU_IAMCU_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, { "CPU_ADX_FLAGS", @@ -471,6 +473,8 @@ static initializer cpu_flag_init[] = "CpuWRMSRNS" }, { "CPU_ANY_MSRLIST_FLAGS", "CpuMSRLIST" }, + { "CPU_ANY_PREFETCHI_FLAGS", + "CpuPREFETCHI" }, }; static initializer operand_type_init[] = @@ -679,6 +683,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuRAOINT), BITFIELD (CpuWRMSRNS), BITFIELD (CpuMSRLIST), + BITFIELD (CpuPREFETCHI), BITFIELD (CpuMWAITX), BITFIELD (CpuCLZERO), BITFIELD (CpuOSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index b548769d75..9252627612 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -223,6 +223,8 @@ enum CpuWRMSRNS, /* Intel MSRLIST Instructions support required. */ CpuMSRLIST, + /* PREFETCHI instruction required */ + CpuPREFETCHI, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -411,6 +413,7 @@ typedef union i386_cpu_flags unsigned int cpuraoint:1; unsigned int cpuwrmsrns:1; unsigned int cpumsrlist:1; + unsigned int cpuprefetchi:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 6057664193..3d9d649c11 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3325,3 +3325,10 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|N wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} // MSRLIST instructions end. + +// PREFETCHI instructions. + +prefetchit0, 0xf18, 0x7, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex } +prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex } + +// PREFETCHI instructions end. -- 2.18.1