From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 38E673858424 for ; Wed, 19 Oct 2022 15:17:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 38E673858424 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666192665; x=1697728665; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=vb0whdd4ejBBsir2OYQFquTIOnKSk1PbbjGakaPrhjw=; b=HwVHq/vA9XZlkcSNnxQEM502JD8QtCmcNElHRrDKZPcvUl0RYZfJNjsH U/3XKpObx1PvLMDNuPJ3+lOXlcxDiJO49ojsmWVM5Ff5X+U0znjNNomM/ EErpswDjmBuouNSwwWB/zVO59dHaQDoyUWnQSQ6I9fdE3tTDOOe4HpDi1 4WgFHetvrKC8BxjBRTYsAWe5+chou0TZJlegNwMpFSJHNBqckjgH++Jf0 PxIxRyAoFVHdIodKLC3pTwKpIS0hJebLLvRvIZKGGynmJXXDyNMsqKlXy 1WKpYTw8bX65SYL+kXK8zOCK06oLAKXKBUcd1iIdG5RWRoNDIz0WIJm3J Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="304056031" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="304056031" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 08:17:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="692434878" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="692434878" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga008.fm.intel.com with ESMTP; 19 Oct 2022 08:17:39 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id BDEB31007807; Wed, 19 Oct 2022 23:17:36 +0800 (CST) From: Haochen Jiang To: binutils@sourceware.org Cc: jbeulich@suse.com, hjl.tools@gmail.com, Kong Lingling Subject: [PATCH 06/10] Support Intel RAO-INT Date: Wed, 19 Oct 2022 23:15:30 +0800 Message-Id: <20221019151534.45521-7-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221019151534.45521-1-haochen.jiang@intel.com> References: <20221019151534.45521-1-haochen.jiang@intel.com> X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Kong Lingling gas/ChangeLog: * NEWS: Support Intel RAO-INT. * config/tc-i386.c: Add raoint. * doc/c-i386.texi: Document .raoint. * testsuite/gas/i386/i386.exp: Run RAOINT tests. * testsuite/gas/i386/raoint-intel.d: New test. * testsuite/gas/i386/raoint.d: Ditto. * testsuite/gas/i386/raoint.s: Ditto. * testsuite/gas/i386/x86-64-raoint-intel.d: Ditto. * testsuite/gas/i386/x86-64-raoint.d: Ditto. * testsuite/gas/i386/x86-64-raoint.s: Ditto. opcodes/ChangeLog: * i386-dis.c (MOD_0F38FC): New. (PREFIX_0F38FC): Ditto. (mod_table): Add MOD_0F38FC. (prefix_table): Add PREFIX_0F38FC. * i386-gen.c: (cpu_flag_init): Add CPU_RAOINT_FLAGS and CPU_ANY_RAOINT_FLAGS. * i386-init.h: Regenerated. * i386-opc.h: (CpuRAOINT): New. (i386_cpu_flags): Add cpuraoint. * i386-opc.tbl: Add RAOINT instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 1 + gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/i386.exp | 4 + gas/testsuite/gas/i386/raoint-intel.d | 18 + gas/testsuite/gas/i386/raoint.d | 18 + gas/testsuite/gas/i386/raoint.s | 15 + gas/testsuite/gas/i386/x86-64-raoint-intel.d | 18 + gas/testsuite/gas/i386/x86-64-raoint.d | 18 + gas/testsuite/gas/i386/x86-64-raoint.s | 15 + opcodes/i386-dis.c | 16 +- opcodes/i386-gen.c | 5 + opcodes/i386-init.h | 514 +- opcodes/i386-opc.h | 5 +- opcodes/i386-opc.tbl | 9 + opcodes/i386-tbl.h | 7902 +++++++++--------- 16 files changed, 4391 insertions(+), 4172 deletions(-) create mode 100644 gas/testsuite/gas/i386/raoint-intel.d create mode 100644 gas/testsuite/gas/i386/raoint.d create mode 100644 gas/testsuite/gas/i386/raoint.s create mode 100644 gas/testsuite/gas/i386/x86-64-raoint-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.d create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.s diff --git a/gas/NEWS b/gas/NEWS index 9757209a9f..f352c5ab89 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel RAO-INT instructions. + * Add support for Intel CMPccXADD instructions. * Add support for Intel AVX-NE-CONVERT instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 81bbf22fec..0ca9b43610 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1098,6 +1098,7 @@ static const arch_entry cpu_arch[] = SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false), SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false), + SUBARCH (raoint, RAOINT, ANY_RAOINT, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 24ea55579e..e15cf7a7aa 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -198,6 +198,7 @@ accept various extension mnemonics. For example, @code{avx_vnni_int8}, @code{avx_ne_convert}, @code{cmpccxadd}, +@code{raoint}, @code{amx_int8}, @code{amx_bf16}, @code{amx_tile}, @@ -1491,7 +1492,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} @item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert} -@item @samp{.cmpccxadd} +@item @samp{.cmpccxadd} @tab @samp{.raoint} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index fb2e2aa446..1eb0eabb6b 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -486,6 +486,8 @@ if [gas_32_check] then { run_dump_test "avx-ne-convert" run_dump_test "avx-ne-convert-intel" run_list_test "cmpccxadd-inval" + run_dump_test "raoint" + run_dump_test "raoint-intel" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" @@ -1162,6 +1164,8 @@ if [gas_64_check] then { run_dump_test "x86-64-avx-ne-convert-intel" run_dump_test "x86-64-cmpccxadd" run_dump_test "x86-64-cmpccxadd-intel" + run_dump_test "x86-64-raoint" + run_dump_test "x86-64-raoint-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/gas/testsuite/gas/i386/raoint-intel.d b/gas/testsuite/gas/i386/raoint-intel.d new file mode 100644 index 0000000000..b50d423a5f --- /dev/null +++ b/gas/testsuite/gas/i386/raoint-intel.d @@ -0,0 +1,18 @@ +#as: +#objdump: -dw -Mintel +#name: i386 RAOINT insns (Intel disassembly) +#source: raoint.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx diff --git a/gas/testsuite/gas/i386/raoint.d b/gas/testsuite/gas/i386/raoint.d new file mode 100644 index 0000000000..2c310c5cc7 --- /dev/null +++ b/gas/testsuite/gas/i386/raoint.d @@ -0,0 +1,18 @@ +#as: +#objdump: -dw +#name: i386 RAOINT insns +#source: raoint.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\) +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\) +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\) +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\) +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\) +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\) +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\) +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\) diff --git a/gas/testsuite/gas/i386/raoint.s b/gas/testsuite/gas/i386/raoint.s new file mode 100644 index 0000000000..63398dfb82 --- /dev/null +++ b/gas/testsuite/gas/i386/raoint.s @@ -0,0 +1,15 @@ +# Check 32bit AVX-NE-CONVERT instructions + + .allow_index_reg + .text +_start: + aadd %edx, (%eax) #RAO-INT + aand %edx, (%eax) #RAO-INT + aor %edx, (%eax) #RAO-INT + axor %edx, (%eax) #RAO-INT + +.intel_syntax noprefix + aadd DWORD PTR [eax], %edx #RAO-INT + aand DWORD PTR [eax], %edx #RAO-INT + aor DWORD PTR [eax], %edx #RAO-INT + axor DWORD PTR [eax], %edx #RAO-INT diff --git a/gas/testsuite/gas/i386/x86-64-raoint-intel.d b/gas/testsuite/gas/i386/x86-64-raoint-intel.d new file mode 100644 index 0000000000..d7de4849a2 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-raoint-intel.d @@ -0,0 +1,18 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 RAOINT insns (Intel disassembly) +#source: x86-64-raoint.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx diff --git a/gas/testsuite/gas/i386/x86-64-raoint.d b/gas/testsuite/gas/i386/x86-64-raoint.d new file mode 100644 index 0000000000..711fe48064 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-raoint.d @@ -0,0 +1,18 @@ +#as: +#objdump: -dw +#name: x86_64 RAOINT insns +#source: x86-64-raoint.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\) +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\) +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\) +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\) +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\) +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\) +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\) +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\) diff --git a/gas/testsuite/gas/i386/x86-64-raoint.s b/gas/testsuite/gas/i386/x86-64-raoint.s new file mode 100644 index 0000000000..28590626ca --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-raoint.s @@ -0,0 +1,15 @@ +# Check 64bit RAOINT instructions + + .allow_index_reg + .text +_start: + aadd %rdx, (%rax) #RAO-INT + aand %rdx, (%rax) #RAO-INT + aor %rdx, (%rax) #RAO-INT + axor %rdx, (%rax) #RAO-INT + +.intel_syntax noprefix + aadd QWORD PTR [rax], %rdx #RAO-INT + aand QWORD PTR [rax], %rdx #RAO-INT + aor QWORD PTR [rax], %rdx #RAO-INT + axor QWORD PTR [rax], %rdx #RAO-INT diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index c68fbcdbb5..3a990e4e63 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -887,6 +887,7 @@ enum MOD_0F38F9, MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1, + MOD_0F38FC, MOD_0F3A0F_PREFIX_1, MOD_VEX_0F12_PREFIX_0, @@ -1086,6 +1087,7 @@ enum PREFIX_0F38F8, PREFIX_0F38FA, PREFIX_0F38FB, + PREFIX_0F38FC, PREFIX_0F3A0F, PREFIX_VEX_0F10, PREFIX_VEX_0F11, @@ -3598,6 +3600,14 @@ static const struct dis386 prefix_table[][4] = { { MOD_TABLE (MOD_0F38FB_PREFIX_1) }, }, + /* PREFIX_0F38FC */ + { + { "aadd", { Edq, Gdq }, PREFIX_OPCODE }, + { "axor", { Edq, Gdq }, PREFIX_OPCODE }, + { "aand", { Edq, Gdq }, PREFIX_OPCODE }, + { "aor", { Edq, Gdq }, PREFIX_OPCODE }, + }, + /* PREFIX_0F3A0F */ { { Bad_Opcode }, @@ -4802,7 +4812,7 @@ static const struct dis386 three_byte_table[][256] = { { MOD_TABLE (MOD_0F38F9) }, { PREFIX_TABLE (PREFIX_0F38FA) }, { PREFIX_TABLE (PREFIX_0F38FB) }, - { Bad_Opcode }, + { MOD_TABLE (MOD_0F38FC) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8374,6 +8384,10 @@ static const struct dis386 mod_table[][2] = { { Bad_Opcode }, { "encodekey256", { Gd, Ed }, 0 }, }, + { + /* MOD_0F38FC */ + { PREFIX_TABLE (PREFIX_0F38FC) }, + }, { /* MOD_0F3A0F_PREFIX_1 */ { Bad_Opcode }, diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 36ff8aa5ff..5d75646c7e 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -253,6 +253,8 @@ static initializer cpu_flag_init[] = "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" }, { "CPU_CMPCCXADD_FLAGS", "CpuCMPCCXADD" }, + { "CPU_RAOINT_FLAGS", + "CpuRAOINT" }, { "CPU_IAMCU_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, { "CPU_ADX_FLAGS", @@ -455,6 +457,8 @@ static initializer cpu_flag_init[] = "CpuAVX_NE_CONVERT" }, { "CPU_ANY_CMPCCXADD_FLAGS", "CpuCMPCCXADD" }, + { "CPU_ANY_RAOINT_FLAGS", + "CpuRAOINT" }, }; static initializer operand_type_init[] = @@ -660,6 +664,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuAVX_VNNI_INT8), BITFIELD (CpuAVX_NE_CONVERT), BITFIELD (CpuCMPCCXADD), + BITFIELD (CpuRAOINT), BITFIELD (CpuMWAITX), BITFIELD (CpuCLZERO), BITFIELD (CpuOSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index d29c711531..cb6c372203 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -217,6 +217,8 @@ enum CpuAVX_NE_CONVERT, /* Intel CMPccXADD instructions support required. */ CpuCMPCCXADD, + /* Intel RAO INT Instructions support required. */ + CpuRAOINT, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -298,7 +300,7 @@ enum /* If you get a compiler error for zero width of the unused field, comment it out. */ -// #define CpuUnused (CpuMax + 1) +#define CpuUnused (CpuMax + 1) /* We can check if an instruction is available with array instead of bitfield. */ @@ -400,6 +402,7 @@ typedef union i386_cpu_flags unsigned int cpuavx_vnni_int8:1; unsigned int cpuavx_ne_convert:1; unsigned int cpucmpccxadd:1; + unsigned int cpuraoint:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 0732e07d80..dacafe1e14 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3302,3 +3302,12 @@ vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|Che cmpxadd, 0x66e, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVVV|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } // CMPCCXADD instructions end. + +// RAOINT instructions. + +aadd, 0xf38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex} +aand, 0x660f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex} +aor, 0xf20f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex} +axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex} + +// RAOINT instructions end. -- 2.18.1