From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id 830D43857830 for ; Mon, 31 Oct 2022 03:07:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 830D43857830 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667185636; x=1698721636; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=rMQL5eR9uCsLaRJoXv2531h7lbHosM1HlE/AJJCU0oQ=; b=StQlpuRV3OMONp3+9Hsm1fQAsnWdf69XH1PiEhveoERFqdtr3YUDD/+r QDPsVP/k4DWiS701kGPb39E9rx2ycK7PYZl1fNgXpZ/NUgcp/HyiaNTI5 K+vOLewZ1gbP4LJ2JUAyagH1HP0KP9NxmyD3Q9BMa1N8hiN3L1xWWT/yJ 1eg6ijajnjM8f8ewP6Bf96XGS8iVZW9LaT3wxkIGopCW318BOQJnSS5Ul +yGqeSSiDaEjcYvWXueP3qdIjgPd2TY2L0KV7gZ4XongdgQFxmvNGlcqJ UbNG9vRUnK6jfmc0DMMfS3lPAzhBYCxEWlp2J5r4lpRb5alauTl6f+lna w==; X-IronPort-AV: E=McAfee;i="6500,9779,10516"; a="309893282" X-IronPort-AV: E=Sophos;i="5.95,227,1661842800"; d="scan'208";a="309893282" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2022 20:07:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10516"; a="702363180" X-IronPort-AV: E=Sophos;i="5.95,227,1661842800"; d="scan'208";a="702363180" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 30 Oct 2022 20:07:10 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id BFE1E10056BA; Mon, 31 Oct 2022 11:07:09 +0800 (CST) From: Haochen Jiang To: binutils@sourceware.org Cc: jbeulich@suse.com, hjl.tools@gmail.com, Hongyu Wang Subject: [PATCH 1/6] Support Intel AVX-IFMA Date: Mon, 31 Oct 2022 11:05:02 +0800 Message-Id: <20221031030507.35588-2-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221031030507.35588-1-haochen.jiang@intel.com> References: <20221031030507.35588-1-haochen.jiang@intel.com> X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Hongyu Wang x86: Support Intel AVX-IFMA Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is cleared by default. Without {vex} pseudo prefix, Intel IFMA instructions are encoded with EVEX prefix. {vex} pseudo prefix will turn on VEX encoding for Intel IFMA instructions. gas/ * NEWS: Support Intel AVX-IFMA. * config/tc-i386.c (cpu_arch): Add avx_ifma. * doc/c-i386.texi: Document .avx_ifma. * testsuite/gas/i386/avx-ifma.d: New file. * testsuite/gas/i386/avx-ifma-intel.d: Likewise. * testsuite/gas/i386/avx-ifma.s: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX IFMA tests. opcodes/ * i386-dis.c (PREFIX_VEX_0F38B4): New. (PREFIX_VEX_0F38B5): Likewise. (VEX_W_0F38B4_P_2): Likewise. (VEX_W_0F38B5_P_2): Likewise. (prefix_table): Add PREFIX_VEX_0F38B4 and PREFIX_VEX_0F38B5. (vex_table): Add VEX_W_0F38B4_P_2 and VEX_W_0F38B5_P_2. * i386-dis-evex.h: Fold AVX512IFMA entries to AVX-IFMA. * i386-gen.c (cpu_flag_init): Clear the CpuAVX_IFMA bit in CPU_UNKNOWN_FLAGS. Add CPU_AVX_IFMA_FLGAS and CPU_ANY_AVX_IFMA_FLAGS. Add CpuAVX_IFMA to CPU_AVX2_FLAGS. (cpu_flags): Add CpuAVX_IFMA. * i386-opc.h (CpuAVX_IFMA): New. (i386_cpu_flags): Add cpuavx_ifma. * i386-opc.tbl: Add Intel AVX IFMA instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. Co-authored-by: Haochen Jiang --- gas/NEWS | 2 + gas/config/tc-i386.c | 1 + gas/doc/c-i386.texi | 7 +- gas/testsuite/gas/i386/avx-ifma-intel.d | 37 + gas/testsuite/gas/i386/avx-ifma-inval.l | 3 + gas/testsuite/gas/i386/avx-ifma-inval.s | 7 + gas/testsuite/gas/i386/avx-ifma.d | 37 + gas/testsuite/gas/i386/avx-ifma.s | 40 + gas/testsuite/gas/i386/i386.exp | 6 + gas/testsuite/gas/i386/noavx512-1.l | 24 +- .../gas/i386/x86-64-avx-ifma-intel.d | 34 + .../gas/i386/x86-64-avx-ifma-inval.l | 4 + .../gas/i386/x86-64-avx-ifma-inval.s | 8 + gas/testsuite/gas/i386/x86-64-avx-ifma.d | 34 + gas/testsuite/gas/i386/x86-64-avx-ifma.s | 23 + opcodes/i386-dis-evex.h | 4 +- opcodes/i386-dis.c | 16 +- opcodes/i386-gen.c | 7 +- opcodes/i386-init.h | 524 +- opcodes/i386-opc.h | 3 + opcodes/i386-opc.tbl | 7 + opcodes/i386-tbl.h | 7810 +++++++++-------- 22 files changed, 4477 insertions(+), 4161 deletions(-) create mode 100644 gas/testsuite/gas/i386/avx-ifma-intel.d create mode 100644 gas/testsuite/gas/i386/avx-ifma-inval.l create mode 100644 gas/testsuite/gas/i386/avx-ifma-inval.s create mode 100644 gas/testsuite/gas/i386/avx-ifma.d create mode 100644 gas/testsuite/gas/i386/avx-ifma.s create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma.d create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma.s diff --git a/gas/NEWS b/gas/NEWS index d7f6a267d9..121aaa80c5 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel AVX-IFMA instructions. + * Add support for Intel PREFETCHI instructions. * Add support for Intel AMX-FP16 instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 59745efb4b..adbc22de8d 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1096,6 +1096,7 @@ static const arch_entry cpu_arch[] = SUBARCH (hreset, HRESET, ANY_HRESET, false), SUBARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, false), SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false), + SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 55a587bfc1..7bdbd26538 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -195,6 +195,7 @@ accept various extension mnemonics. For example, @code{avx_vnni}, @code{avx512_fp16}, @code{prefetchi}, +@code{avx_ifma}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -828,9 +829,9 @@ prefix which generates REX prefix unconditionally. @samp{@{nooptimize@}} -- disable instruction size optimization. @end itemize -Mnemonics of Intel VNNI instructions are encoded with the EVEX prefix +Mnemonics of Intel VNNI/IFMA instructions are encoded with the EVEX prefix by default. The pseudo @samp{@{vex@}} prefix can be used to encode -mnemonics of Intel VNNI instructions with the VEX prefix. +mnemonics of Intel VNNI/IFMA instructions with the VEX prefix. @cindex conversion instructions, i386 @cindex i386 conversion instructions @@ -1488,7 +1489,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect} @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} -@item @samp{.prefetchi} +@item @samp{.prefetchi} @tab @samp{.avx_ifma} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/avx-ifma-intel.d b/gas/testsuite/gas/i386/avx-ifma-intel.d new file mode 100644 index 0000000000..b56ba847bf --- /dev/null +++ b/gas/testsuite/gas/i386/avx-ifma-intel.d @@ -0,0 +1,37 @@ +#as: +#objdump: -dw -Mintel +#name: i386 AVX IFMA insns (Intel disassembly) +#source: avx-ifma.s + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 d2[ ]*\{vex\} vpmadd52huq xmm2,xmm4,xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq xmm2,xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 d2[ ]*\{vex\} vpmadd52huq ymm2,ymm4,ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq ymm2,ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq xmm2,xmm4,xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq xmm2,xmm4,xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 d2[ ]*\{vex\} vpmadd52luq xmm2,xmm4,xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq xmm2,xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq ymm2,ymm4,ymm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq ymm2,ymm4,ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 d2[ ]*\{vex\} vpmadd52luq ymm2,ymm4,ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq ymm2,ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 b5 c0[ ]*vpmadd52huq zmm0,zmm0,zmm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq ymm0,ymm0,ymm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq xmm0,xmm0,xmm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq ymm0,ymm0,ymm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq xmm0,xmm0,xmm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq ymm0,ymm0,ymm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq xmm0,xmm0,xmm0 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2 +#pass diff --git a/gas/testsuite/gas/i386/avx-ifma-inval.l b/gas/testsuite/gas/i386/avx-ifma-inval.l new file mode 100644 index 0000000000..5294c2ca73 --- /dev/null +++ b/gas/testsuite/gas/i386/avx-ifma-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:6: Error: unsupported .* `vpmadd52huq' +.*:7: Error: operand .* `vpmadd52huq' diff --git a/gas/testsuite/gas/i386/avx-ifma-inval.s b/gas/testsuite/gas/i386/avx-ifma-inval.s new file mode 100644 index 0000000000..4b763b6e45 --- /dev/null +++ b/gas/testsuite/gas/i386/avx-ifma-inval.s @@ -0,0 +1,7 @@ +# Check illegal in AVXIFMA instructions + + .text + .arch .noavx512ifma +_start: + vpmadd52huq %xmm2, %xmm4, %xmm2{%k6} + vpmadd52huq %zmm2, %zmm4, %zmm2 diff --git a/gas/testsuite/gas/i386/avx-ifma.d b/gas/testsuite/gas/i386/avx-ifma.d new file mode 100644 index 0000000000..c84b4caad8 --- /dev/null +++ b/gas/testsuite/gas/i386/avx-ifma.d @@ -0,0 +1,37 @@ +#as: +#objdump: -dw +#name: i386 AVX IFMA insns +#source: avx-ifma.s + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 d2[ ]*\{vex\} vpmadd52huq %xmm2,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq \(%ecx\),%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 d2[ ]*\{vex\} vpmadd52huq %ymm2,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq \(%ecx\),%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq %xmm2,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq %xmm2,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 d2[ ]*\{vex\} vpmadd52luq %xmm2,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq \(%ecx\),%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq %ymm2,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq %ymm2,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 d2[ ]*\{vex\} vpmadd52luq %ymm2,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq \(%ecx\),%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 b5 c0[ ]*vpmadd52huq %zmm0,%zmm0,%zmm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq %ymm0,%ymm0,%ymm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq %xmm0,%xmm0,%xmm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq %ymm0,%ymm0,%ymm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq %xmm0,%xmm0,%xmm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq %ymm0,%ymm0,%ymm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq %xmm0,%xmm0,%xmm0 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2 +#pass diff --git a/gas/testsuite/gas/i386/avx-ifma.s b/gas/testsuite/gas/i386/avx-ifma.s new file mode 100644 index 0000000000..81046966d7 --- /dev/null +++ b/gas/testsuite/gas/i386/avx-ifma.s @@ -0,0 +1,40 @@ + .allow_index_reg + +.macro test_insn mnemonic + \mnemonic %xmm2, %xmm4, %xmm2 + {evex} \mnemonic %xmm2, %xmm4, %xmm2 + {vex} \mnemonic %xmm2, %xmm4, %xmm2 + {vex} \mnemonic (%ecx), %xmm4, %xmm2 + \mnemonic %ymm2, %ymm4, %ymm2 + {evex} \mnemonic %ymm2, %ymm4, %ymm2 + {vex} \mnemonic %ymm2, %ymm4, %ymm2 + {vex} \mnemonic (%ecx), %ymm4, %ymm2 +.endm + + .text +_start: + test_insn vpmadd52huq + test_insn vpmadd52luq + + .arch .noavx512vl + + vpmadd52huq %zmm0, %zmm0, %zmm0 + vpmadd52huq %ymm0, %ymm0, %ymm0 + vpmadd52huq %xmm0, %xmm0, %xmm0 + + .arch default + .arch .noavx512ifma + + vpmadd52huq %ymm0, %ymm0, %ymm0 + vpmadd52huq %xmm0, %xmm0, %xmm0 + + .arch default + .arch .noavx512f + + vpmadd52huq %ymm0, %ymm0, %ymm0 + vpmadd52huq %xmm0, %xmm0, %xmm0 + + .arch default + .arch .avx_ifma + vpmadd52huq %xmm2, %xmm4, %xmm2 + vpmadd52huq %ymm2, %ymm4, %ymm2 diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 22233d7483..96ab1a02d1 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -474,6 +474,9 @@ if [gas_32_check] then { run_list_test "avx512_bf16_vl-inval" run_dump_test "avx-vnni" run_list_test "avx-vnni-inval" + run_dump_test "avx-ifma" + run_dump_test "avx-ifma-intel" + run_list_test "avx-ifma-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" @@ -1142,6 +1145,9 @@ if [gas_64_check] then { run_dump_test "x86-64-amx-fp16" run_dump_test "x86-64-amx-fp16-intel" run_dump_test "x86-64-amx-fp16-bad" + run_dump_test "x86-64-avx-ifma" + run_dump_test "x86-64-avx-ifma-intel" + run_list_test "x86-64-avx-ifma-inval" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/gas/testsuite/gas/i386/noavx512-1.l b/gas/testsuite/gas/i386/noavx512-1.l index 15a6fc689b..a289b23619 100644 --- a/gas/testsuite/gas/i386/noavx512-1.l +++ b/gas/testsuite/gas/i386/noavx512-1.l @@ -37,9 +37,9 @@ .*:120: Error: .*not supported.* .*:121: Error: .*not supported.* .*:122: Error: .*not supported.* -.*:126: Error: .*not supported.* -.*:127: Error: .*not supported.* -.*:128: Error: .*not supported.* +.*:126: Error: .*operand .* +.*:127: Error: .*unsupported .* +.*:128: Error: .*unsupported .* .*:135: Error: .*operand size mismatch.* .*:136: Error: .*unsupported masking.* .*:137: Error: .*unsupported masking.* @@ -50,9 +50,9 @@ .*:142: Error: .*not supported.* .*:143: Error: .*not supported.* .*:144: Error: .*not supported.* -.*:148: Error: .*not supported.* -.*:149: Error: .*not supported.* -.*:150: Error: .*not supported.* +.*:148: Error: .*operand .* +.*:149: Error: .*unsupported .* +.*:150: Error: .*unsupported .* .*:151: Error: .*not supported.* .*:157: Error: .*operand size mismatch.* .*:158: Error: .*unsupported masking.* @@ -64,9 +64,9 @@ .*:164: Error: .*not supported.* .*:165: Error: .*not supported.* .*:166: Error: .*not supported.* -.*:170: Error: .*not supported.* -.*:171: Error: .*not supported.* -.*:172: Error: .*not supported.* +.*:170: Error: .*operand .* +.*:171: Error: .*unsupported .* +.*:172: Error: .*unsupported .* .*:173: Error: .*not supported.* .*:174: Error: .*not supported.* .*:175: Error: .*not supported.* @@ -84,9 +84,9 @@ .*:189: Error: .*bad register name.* .*:190: Error: .*unknown vector operation.* .*:191: Error: .*unknown vector operation.* -.*:192: Error: .*not supported.* -.*:193: Error: .*not supported.* -.*:194: Error: .*not supported.* +.*:192: Error: .*bad register name.* +.*:193: Error: .*unknown vector operation.* +.*:194: Error: .*unknown vector operation.* .*:195: Error: .*not supported.* .*:196: Error: .*not supported.* .*:197: Error: .*not supported.* diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d b/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d new file mode 100644 index 0000000000..0b3b053e5d --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d @@ -0,0 +1,34 @@ +#as: +#objdump: -dw -Mintel +#name: x86-64 AVX IFMA insns (Intel disassembly) +#source: x86-64-avx-ifma.s + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12 +[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b5 d4[ ]*\{vex\} vpmadd52huq xmm2,xmm4,xmm12 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq xmm2,xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b5 d6[ ]*vpmadd52huq xmm2,xmm4,xmm22 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12 +[ ]*[a-f0-9]+:[ ]*c4 c2 dd b5 d4[ ]*\{vex\} vpmadd52huq ymm2,ymm4,ymm12 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq ymm2,ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b5 d6[ ]*vpmadd52huq ymm2,ymm4,ymm22 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq xmm2,xmm4,xmm12 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq xmm2,xmm4,xmm12 +[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b4 d4[ ]*\{vex\} vpmadd52luq xmm2,xmm4,xmm12 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq xmm2,xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b4 d6[ ]*vpmadd52luq xmm2,xmm4,xmm22 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq ymm2,ymm4,ymm12 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq ymm2,ymm4,ymm12 +[ ]*[a-f0-9]+:[ ]*c4 c2 dd b4 d4[ ]*\{vex\} vpmadd52luq ymm2,ymm4,ymm12 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq ymm2,ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b4 d6[ ]*vpmadd52luq ymm2,ymm4,ymm22 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l new file mode 100644 index 0000000000..fad43f6768 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l @@ -0,0 +1,4 @@ +.* Assembler messages: +.*:6: Error: unsupported .* `vpmadd52huq' +.*:7: Error: unsupported .* `vpmadd52huq' +.*:8: Error: operand .* `vpmadd52huq' diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s new file mode 100644 index 0000000000..76da0f1a37 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s @@ -0,0 +1,8 @@ +# Check illegal in AVXIFMA instructions + + .text + .arch .noavx512ifma +_start: + vpmadd52huq %xmm2, %xmm4, %xmm2{%k6} + vpmadd52huq %xmm22, %xmm4, %xmm2{%k1} + vpmadd52huq %zmm2, %zmm4, %zmm2 diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma.d b/gas/testsuite/gas/i386/x86-64-avx-ifma.d new file mode 100644 index 0000000000..b1670b68b6 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-ifma.d @@ -0,0 +1,34 @@ +#as: +#objdump: -dw +#name: x86-64 AVX IFMA insns +#source: x86-64-avx-ifma.s + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b5 d4[ ]*\{vex\} vpmadd52huq %xmm12,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq \(%rcx\),%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b5 d6[ ]*vpmadd52huq %xmm22,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 c2 dd b5 d4[ ]*\{vex\} vpmadd52huq %ymm12,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq \(%rcx\),%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b5 d6[ ]*vpmadd52huq %ymm22,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq %xmm12,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq %xmm12,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b4 d4[ ]*\{vex\} vpmadd52luq %xmm12,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq \(%rcx\),%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b4 d6[ ]*vpmadd52luq %xmm22,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq %ymm12,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq %ymm12,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 c2 dd b4 d4[ ]*\{vex\} vpmadd52luq %ymm12,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq \(%rcx\),%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b4 d6[ ]*vpmadd52luq %ymm22,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma.s b/gas/testsuite/gas/i386/x86-64-avx-ifma.s new file mode 100644 index 0000000000..bfc524a103 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-ifma.s @@ -0,0 +1,23 @@ + .allow_index_reg + +.macro test_insn mnemonic + \mnemonic %xmm12, %xmm4, %xmm2 + {evex} \mnemonic %xmm12, %xmm4, %xmm2 + {vex} \mnemonic %xmm12, %xmm4, %xmm2 + {vex} \mnemonic (%rcx), %xmm4, %xmm2 + \mnemonic %xmm22, %xmm4, %xmm2 + \mnemonic %ymm12, %ymm4, %ymm2 + {evex} \mnemonic %ymm12, %ymm4, %ymm2 + {vex} \mnemonic %ymm12, %ymm4, %ymm2 + {vex} \mnemonic (%rcx), %ymm4, %ymm2 + \mnemonic %ymm22, %ymm4, %ymm2 +.endm + + .text +_start: + test_insn vpmadd52huq + test_insn vpmadd52luq + + .arch .avx_ifma + vpmadd52huq %xmm12, %xmm4, %xmm2 + vpmadd52huq %ymm12, %ymm4, %ymm2 diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index 070af858f5..65935a328c 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -495,8 +495,8 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA }, - { "vpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA }, + { VEX_W_TABLE (VEX_W_0F38B4) }, + { VEX_W_TABLE (VEX_W_0F38B5) }, { "%XEvfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA }, { "%XEvfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA }, /* B8 */ diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index fb197c40ea..ba232939d7 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1534,6 +1534,8 @@ enum VEX_W_0F385E_X86_64_P_3, VEX_W_0F3878, VEX_W_0F3879, + VEX_W_0F38B4, + VEX_W_0F38B5, VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1, @@ -6316,8 +6318,8 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F38B4) }, + { VEX_W_TABLE (VEX_W_0F38B5) }, { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, /* b8 */ @@ -7631,6 +7633,16 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3879 */ { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA }, }, + { + /* VEX_W_0F38B4 */ + { Bad_Opcode }, + { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA }, + }, + { + /* VEX_W_0F38B5 */ + { Bad_Opcode }, + { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA }, + }, { /* VEX_W_0F38CF */ { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA }, diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index c6837dbb4c..dd759fbc7c 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -247,6 +247,8 @@ static initializer cpu_flag_init[] = "CPU_AVX512BW_FLAGS|CpuAVX512_FP16" }, { "CPU_PREFETCHI_FLAGS", "CpuPREFETCHI"}, + { "CPU_AVX_IFMA_FLAGS", + "CPU_AVX2_FLAGS|CpuAVX_IFMA" }, { "CPU_IAMCU_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, { "CPU_ADX_FLAGS", @@ -374,7 +376,7 @@ static initializer cpu_flag_init[] = { "CPU_ANY_AVX_FLAGS", "CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" }, { "CPU_ANY_AVX2_FLAGS", - "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI" }, + "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA" }, { "CPU_ANY_AVX512F_FLAGS", "CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CPU_ANY_AVX512BW_FLAGS|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_BF16|CpuAVX512_VP2INTERSECT" }, { "CPU_ANY_AVX512CD_FLAGS", @@ -445,6 +447,8 @@ static initializer cpu_flag_init[] = "CpuAVX512_FP16" }, { "CPU_ANY_PREFETCHI_FLAGS", "CpuPREFETCHI" }, + { "CPU_ANY_AVX_IFMA_FLAGS", + "CpuAVX_IFMA" }, }; static initializer operand_type_init[] = @@ -647,6 +651,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuAVX_VNNI), BITFIELD (CpuAVX512_FP16), BITFIELD (CpuPREFETCHI), + BITFIELD (CpuAVX_IFMA), BITFIELD (CpuMWAITX), BITFIELD (CpuCLZERO), BITFIELD (CpuOSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 0875f787cc..7cd601e924 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -211,6 +211,8 @@ enum CpuAVX512_FP16, /* PREFETCHI instruction required */ CpuPREFETCHI, + /* Intel AVX IFMA Instructions support required. */ + CpuAVX_IFMA, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -393,6 +395,7 @@ typedef union i386_cpu_flags unsigned int cpuavx_vnni:1; unsigned int cpuavx512_fp16:1; unsigned int cpuprefetchi:1; + unsigned int cpuavx_ifma:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 00bbf57ccf..489a5335e2 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -2811,6 +2811,13 @@ vpmadd52luq, 0x66B4, None, CpuAVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV=1|Ve // AVX512IFMA instructions end +// AVX-IFMA instructions. + +vpmadd52huq, 0x66B5, None, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpmadd52luq, 0x66B4, None, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } + +// AVX-IFMA instructions end. + // AVX512VBMI instructions vpmultishiftqb, 0x6683, None, CpuAVX512VBMI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -- 2.18.1