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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id l9-20020a1709060cc900b0078ddb518a90sm3097952ejh.223.2022.11.13.07.59.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 07:59:25 -0800 (PST) From: Christoph Muellner To: binutils@sourceware.org, Nelson Chu , Andrew Waterman , Palmer Dabbelt , Jim Wilson , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 1/2] RISC-V: Add T-Head Fmv vendor extension Date: Sun, 13 Nov 2022 16:59:20 +0100 Message-Id: <20221113155921.1445808-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_MANYTO,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph Müllner This patch adds the XTheadFmv extension, which allows to access the upper 32 bits of a double-precision floating-point register in RV32. The XTheadFmv extension is documented in the RISC-V toolchain contentions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Co-developed-by: Lifang Xia Signed-off-by: Christoph Müllner --- bfd/elfxx-riscv.c | 5 +++++ gas/NEWS | 6 +++--- gas/doc/c-riscv.texi | 5 +++++ gas/testsuite/gas/riscv/x-thead-fmv.d | 11 +++++++++++ gas/testsuite/gas/riscv/x-thead-fmv.s | 3 +++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 4 ++++ 8 files changed, 40 insertions(+), 3 deletions(-) create mode 100644 gas/testsuite/gas/riscv/x-thead-fmv.d create mode 100644 gas/testsuite/gas/riscv/x-thead-fmv.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 300ccf49534..a1e42064ee0 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1239,6 +1239,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadcondmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadfmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadfmv", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmempair", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2419,6 +2420,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadcondmov"); case INSN_CLASS_XTHEADFMEMIDX: return riscv_subset_supports (rps, "xtheadfmemidx"); + case INSN_CLASS_XTHEADFMV: + return riscv_subset_supports (rps, "xtheadfmv"); case INSN_CLASS_XTHEADMAC: return riscv_subset_supports (rps, "xtheadmac"); case INSN_CLASS_XTHEADMEMIDX: @@ -2573,6 +2576,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadcondmov"; case INSN_CLASS_XTHEADFMEMIDX: return "xtheadfmemidx"; + case INSN_CLASS_XTHEADFMV: + return "xtheadfmv"; case INSN_CLASS_XTHEADMAC: return "xtheadmac"; case INSN_CLASS_XTHEADMEMIDX: diff --git a/gas/NEWS b/gas/NEWS index 86731348e3e..1c2da4ed97b 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -26,9 +26,9 @@ for --enable-compressed-debug-sections. * Add support for various T-Head extensions (XTheadBa, XTheadBb, XTheadBs, - XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadMemIdx, XTheadMemPair, - XTheadMac, and XTheadSync) from version 2.0 of the T-Head ISA manual, which - are implemented in the Allwinner D1. + XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadFmv, XTheadMemIdx, + XTheadMemPair, XTheadMac, and XTheadSync) from version 2.0 of the T-Head + ISA manual, which are implemented in the Allwinner D1. * Add support for the RISC-V Zawrs extension, version 1.0-rc4. diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index cc63760cb80..f2a69d8b950 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -734,6 +734,11 @@ The XTheadFMemIdx extension provides floating-point memory operations. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XTheadFmv +The XTheadFmv extension provides access to the upper 32 bits of a doulbe-precision floating point register. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf}. + @item XTheadMac The XTheadMac extension provides multiply-accumulate instructions. diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d b/gas/testsuite/gas/riscv/x-thead-fmv.d new file mode 100644 index 00000000000..f2bbe010beb --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d @@ -0,0 +1,11 @@ +#as: -march=rv32i_xtheadfmv +#source: x-thead-fmv.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+6005950b[ ]+th.fmv.hw.x[ ]+a0,fa1 +[ ]+[0-9a-f]+:[ ]+5005158b[ ]+th.fmv.x.hw[ ]+a1,fa0 diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.s b/gas/testsuite/gas/riscv/x-thead-fmv.s new file mode 100644 index 00000000000..250ba8358ae --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmv.s @@ -0,0 +1,3 @@ +target: + th.fmv.hw.x a0, fa1 + th.fmv.x.hw a1, fa0 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index e40592159cd..d7d9dbc83f6 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2208,6 +2208,11 @@ #define MASK_TH_FSURD 0xf800707f #define MATCH_TH_FSURW 0x5000700b #define MASK_TH_FSURW 0xf800707f +/* Vendor-specific (T-Head) XTheadFmv instructions. */ +#define MATCH_TH_FMV_HW_X 0x6000100b +#define MASK_TH_FMV_HW_X 0xfff0707f +#define MATCH_TH_FMV_X_HW 0x5000100b +#define MASK_TH_FMV_X_HW 0xfff0707f /* Vendor-specific (T-Head) XTheadMac instructions. */ #define MATCH_TH_MULA 0x2000100b #define MASK_TH_MULA 0xfe00707f @@ -3122,6 +3127,9 @@ DECLARE_INSN(th_fsrd, MATCH_TH_FSRD, MASK_TH_FSRD) DECLARE_INSN(th_fsrw, MATCH_TH_FSRW, MASK_TH_FSRW) DECLARE_INSN(th_fsurd, MATCH_TH_FSURD, MASK_TH_FSURD) DECLARE_INSN(th_fsurw, MATCH_TH_FSURW, MASK_TH_FSURW) +/* Vendor-specific (T-Head) XTheadFmv instructions. */ +DECLARE_INSN(th_fmv_hw_x, MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X) +DECLARE_INSN(th_fmv_x_hw, MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW) /* Vendor-specific (T-Head) XTheadMac instructions. */ DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA) DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index dddabfdd415..f90cf97ceb2 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -416,6 +416,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADCMO, INSN_CLASS_XTHEADCONDMOV, INSN_CLASS_XTHEADFMEMIDX, + INSN_CLASS_XTHEADFMV, INSN_CLASS_XTHEADMAC, INSN_CLASS_XTHEADMEMIDX, INSN_CLASS_XTHEADMEMPAIR, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 599486fdf03..dfd508b0e71 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1931,6 +1931,10 @@ const struct riscv_opcode riscv_opcodes[] = {"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0}, {"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadFmv instructions. */ +{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0}, +{"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadMemIdx instructions. */ {"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, 0}, {"th.ldib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIB, MASK_TH_LDIB, match_th_load_inc, 0}, -- 2.38.1