From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from zg8tmja5ljk3lje4ms43mwaa.icoremail.net (zg8tmja5ljk3lje4ms43mwaa.icoremail.net [209.97.181.73]) by sourceware.org (Postfix) with SMTP id B3FB13844690 for ; Tue, 13 Dec 2022 04:34:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B3FB13844690 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from host014-ubuntu-1804.lxd (unknown [10.12.130.31]) by app2 (Coremail) with SMTP id EggMCgCHZS_WAJhjFtgYAA--.18777S4; Tue, 13 Dec 2022 12:34:30 +0800 (CST) From: Li Xu To: binutils@sourceware.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Li Xu Subject: [PATCH] RISC-V: Add string length check for operands in AS Date: Tue, 13 Dec 2022 12:34:28 +0800 Message-Id: <20221213043428.33155-1-xuli1@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID:EggMCgCHZS_WAJhjFtgYAA--.18777S4 X-Coremail-Antispam: 1UD129KBjvJXoWxXw4kuw4kAF47XFWrAr15twb_yoW5AFy3pa y8J3WjkrZ5XF93t3s8KrW5Ca17Aa109rZ09r1fAw12krW8CFy2yws7tr17XFsIvFWY93yr Za1DZrW8Zr4UJaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUva14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j 6r4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY1x0262kKe7AKxVWU AVWUtwCY02Avz4vE-syl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2 IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v2 6r126r1DMIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2 IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv 67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyT uYvjfUYNVyDUUUU X-CM-SenderInfo: 50xoxi46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The current AS accepts invaild operands due to miss of operands length check. For example, "e6" is an invalid operand in (vsetvli a0, a1, e6, mf8, tu, ma), but it's still accepted by assembler. In detail, the condition check "strncmp (array[i], *s, len) == 0" in arg_lookup function passes with "strncmp ("e64", "e6", 2)" in the case above. So the generated encoding is same as that of (vsetvli a0, a1, e64, mf8, tu, ma). This patch fixes issue above by prompting an error in such case and also adds a new testcase. gas/ChangeLog: * config/tc-riscv.c (arg_lookup): Add string length check for operands. * testsuite/gas/riscv/vector-insns-fail-vsew.d: New testcase for an illegal vsew. * testsuite/gas/riscv/vector-insns-fail-vsew.l: Likewise. * testsuite/gas/riscv/vector-insns-fail-vsew.s: Likewise. --- gas/config/tc-riscv.c | 2 +- gas/testsuite/gas/riscv/vector-insns-fail-vsew.d | 3 +++ gas/testsuite/gas/riscv/vector-insns-fail-vsew.l | 3 +++ gas/testsuite/gas/riscv/vector-insns-fail-vsew.s | 1 + 4 files changed, 8 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-vsew.d create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-vsew.l create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-vsew.s diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 0682eb35524..b0989e4b124 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1206,7 +1206,7 @@ arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) return false; for (i = 0; i < size; i++) - if (array[i] != NULL && strncmp (array[i], *s, len) == 0) + if (array[i] != NULL && (strlen(array[i]) == len) && strncmp (array[i], *s, len) == 0) { *regnop = i; *s += len; diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-vsew.d b/gas/testsuite/gas/riscv/vector-insns-fail-vsew.d new file mode 100644 index 00000000000..c0c81579741 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-fail-vsew.d @@ -0,0 +1,3 @@ +#as: -march=rv32ifv +#source: vector-insns-fail-vsew.s +#error_output: vector-insns-fail-vsew.l diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-vsew.l b/gas/testsuite/gas/riscv/vector-insns-fail-vsew.l new file mode 100644 index 00000000000..87a2c22a805 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-fail-vsew.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: instruction vsetvli requires absolute expression +.*: Error: illegal operands `vsetvli a0,a1,e6,mf8,tu,ma' diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-vsew.s b/gas/testsuite/gas/riscv/vector-insns-fail-vsew.s new file mode 100644 index 00000000000..b8f3242406f --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-fail-vsew.s @@ -0,0 +1 @@ + vsetvli a0, a1, e6, mf8, tu, ma # unrecognized vsew -- 2.17.1