From: WANG Xuerui <i.swmail@xen0n.name>
To: binutils@sourceware.org
Cc: Chenghua Xu <xuchenghua@loongson.cn>,
Zhensong Liu <liuzhensong@loongson.cn>,
Qinggang Meng <mengqinggang@loongson.cn>,
Xi Ruoyao <xry111@xry111.site>, WANG Xuerui <git@xen0n.name>
Subject: [PATCH v3 1/6] LoongArch: support disassembling certain pseudo-instructions
Date: Wed, 14 Dec 2022 13:51:59 +0800 [thread overview]
Message-ID: <20221214055204.2890795-2-i.swmail@xen0n.name> (raw)
In-Reply-To: <20221214055204.2890795-1-i.swmail@xen0n.name>
From: WANG Xuerui <git@xen0n.name>
Add a flag in the pinfo field for being able to mark certain specialized
matchers as disassembler-only, so some degree of isolation between
assembler-side and disassembler-side can be achieved.
This isolation is necessary, firstly because some pseudo-instructions
cannot be fully described in the opcode table, like `li.[wd]`, so the
corresponding opcode entry cannot have meaningful match/mask values.
Secondly, some of these pseudo-instructions can be realized in more than
one plausible ways; e.g. `li.w rd, <something between 0 and 0x7ff>` can
be realized on LA64 with any of `addi.w`, `addi.d` or `ori`. If we tie
disassembly of such aliases with the corresponding GAS support, only one
canonical form among the above would be recognized as `li.w`, and it
would mildly impact the readability of disassembly output.
People wanting the exact disassembly can always set `-M no-aliases` to
get the original behavior back.
In addition, in certain cases, information is irreversibly lost after
assembling, so perfect round-trip would not be possible in such cases.
For example, `li.w` and `li.d` of immediates within int32_t range
produce the same code; in this patch, `addi.d rd, $zero, imm` is treated
as `li.d`, while `addi.w` and `ori` immediate loads are shown as `li.w`,
due to the expressible value range well within 32 bits.
---
gas/config/tc-loongarch.c | 3 ++-
gas/testsuite/gas/loongarch/imm_ins.d | 4 ++--
gas/testsuite/gas/loongarch/imm_ins_32.d | 2 +-
gas/testsuite/gas/loongarch/jmp_op.d | 12 +++++-----
gas/testsuite/gas/loongarch/li.d | 8 +++----
gas/testsuite/gas/loongarch/macro_op.d | 4 ++--
.../gas/loongarch/macro_op_large_abs.d | 14 +++++------
.../gas/loongarch/macro_op_large_pc.d | 14 +++++------
gas/testsuite/gas/loongarch/nop.d | 2 +-
gas/testsuite/gas/loongarch/reloc.d | 2 +-
include/opcode/loongarch.h | 2 ++
opcodes/loongarch-dis.c | 24 ++++++++++++-------
opcodes/loongarch-opc.c | 23 ++++++++++++++++--
13 files changed, 72 insertions(+), 42 deletions(-)
diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
index 60149a6d8db..de7f9e26ae3 100644
--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
@@ -743,7 +743,8 @@ get_loongarch_opcode (struct loongarch_cl_insn *insn)
for (it = ase->opcodes; it->name; it++)
{
if ((!it->include || (it->include && *it->include))
- && (!it->exclude || (it->exclude && !(*it->exclude))))
+ && (!it->exclude || (it->exclude && !(*it->exclude)))
+ && !(it->pinfo & INSN_DIS_ALIAS))
str_hash_insert (ase->name_hash_entry, it->name,
(void *) it, 0);
}
diff --git a/gas/testsuite/gas/loongarch/imm_ins.d b/gas/testsuite/gas/loongarch/imm_ins.d
index 0ceaead3edf..c588b5e0e25 100644
--- a/gas/testsuite/gas/loongarch/imm_ins.d
+++ b/gas/testsuite/gas/loongarch/imm_ins.d
@@ -8,10 +8,10 @@
Disassembly of section .text:
00000000.* <.text>:
-[ ]+0:[ ]+03848c0c[ ]+ori[ ]+\$t0,[ ]+\$zero,[ ]+0x123
+[ ]+0:[ ]+03848c0c[ ]+li.w[ ]+\$t0,[ ]+0x123
[ ]+4:[ ]+15ffe00d[ ]+lu12i.w[ ]+\$t1,[ ]+-256\(0xfff00\)
[ ]+8:[ ]+16001fed[ ]+lu32i.d[ ]+\$t1,[ ]+255\(0xff\)
-[ ]+c:[ ]+02bffc0e[ ]+addi.w[ ]+\$t2,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc0e[ ]+li.w[ ]+\$t2,[ ]+-1\(0xfff\)
[ ]+10:[ ]+1601ffee[ ]+lu32i.d[ ]+\$t2,[ ]+4095\(0xfff\)
[ ]+14:[ ]+0004b58b[ ]+alsl.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+18:[ ]+0006b58b[ ]+alsl.wu[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
diff --git a/gas/testsuite/gas/loongarch/imm_ins_32.d b/gas/testsuite/gas/loongarch/imm_ins_32.d
index 0a826bfba5b..5fd5835a342 100644
--- a/gas/testsuite/gas/loongarch/imm_ins_32.d
+++ b/gas/testsuite/gas/loongarch/imm_ins_32.d
@@ -8,7 +8,7 @@
Disassembly of section .text:
00000000.* <.text>:
-[ ]+0:[ ]+03848c0c[ ]+ori[ ]+\$t0,[ ]+\$zero,[ ]+0x123
+[ ]+0:[ ]+03848c0c[ ]+li.w[ ]+\$t0,[ ]+0x123
[ ]+4:[ ]+0004b58b[ ]+alsl.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+8:[ ]+0006b58b[ ]+alsl.wu[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+c:[ ]+0009358b[ ]+bytepick.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
diff --git a/gas/testsuite/gas/loongarch/jmp_op.d b/gas/testsuite/gas/loongarch/jmp_op.d
index 218c13f9398..e34660c2fd4 100644
--- a/gas/testsuite/gas/loongarch/jmp_op.d
+++ b/gas/testsuite/gas/loongarch/jmp_op.d
@@ -7,15 +7,15 @@
Disassembly of section .text:
00000000.* <.text>:
-[ ]+0:[ ]+03400000[ ]+[ ]+andi[ ]+\$zero, \$zero, 0x0
-[ ]+4:[ ]+63fffc04[ ]+[ ]+blt[ ]+\$zero, \$a0, -4\(0x3fffc\)[ ]+# 0x0
-[ ]+8:[ ]+67fff880[ ]+[ ]+bge[ ]+\$a0, \$zero, -8\(0x3fff8\)[ ]+# 0x0
-[ ]+c:[ ]+67fff404[ ]+[ ]+bge[ ]+\$zero, \$a0, -12\(0x3fff4\)[ ]+# 0x0
+[ ]+0:[ ]+03400000[ ]+[ ]+nop[ ]+
+[ ]+4:[ ]+63fffc04[ ]+[ ]+bgtz[ ]+\$a0, -4\(0x3fffc\)[ ]+# 0x0
+[ ]+8:[ ]+67fff880[ ]+[ ]+bgez[ ]+\$a0, -8\(0x3fff8\)[ ]+# 0x0
+[ ]+c:[ ]+67fff404[ ]+[ ]+blez[ ]+\$a0, -12\(0x3fff4\)[ ]+# 0x0
[ ]+10:[ ]+43fff09f[ ]+[ ]+beqz[ ]+\$a0, -16\(0x7ffff0\)[ ]+# 0x0
[ ]+14:[ ]+47ffec9f[ ]+[ ]+bnez[ ]+\$a0, -20\(0x7fffec\)[ ]+# 0x0
[ ]+18:[ ]+4bffe81f[ ]+[ ]+bceqz[ ]+\$fcc0, -24\(0x7fffe8\)[ ]+# 0x0
[ ]+1c:[ ]+4bffe51f[ ]+[ ]+bcnez[ ]+\$fcc0, -28\(0x7fffe4\)[ ]+# 0x0
-[ ]+20:[ ]+4c000080[ ]+[ ]+jirl[ ]+\$zero, \$a0, 0
+[ ]+20:[ ]+4c000080[ ]+[ ]+jr[ ]+\$a0
[ ]+24:[ ]+53ffdfff[ ]+[ ]+b[ ]+-36\(0xfffffdc\)[ ]+# 0x0
[ ]+28:[ ]+57ffdbff[ ]+[ ]+bl[ ]+-40\(0xfffffd8\)[ ]+# 0x0
[ ]+2c:[ ]+5bffd485[ ]+[ ]+beq[ ]+\$a0, \$a1, -44\(0x3ffd4\)[ ]+# 0x0
@@ -28,4 +28,4 @@ Disassembly of section .text:
[ ]+48:[ ]+6bffb8a4[ ]+[ ]+bltu[ ]+\$a1, \$a0, -72\(0x3ffb8\)[ ]+# 0x0
[ ]+4c:[ ]+6fffb485[ ]+[ ]+bgeu[ ]+\$a0, \$a1, -76\(0x3ffb4\)[ ]+# 0x0
[ ]+50:[ ]+6fffb0a4[ ]+[ ]+bgeu[ ]+\$a1, \$a0, -80\(0x3ffb0\)[ ]+# 0x0
-[ ]+54:[ ]+4c000020[ ]+[ ]+jirl[ ]+\$zero, \$ra, 0
+[ ]+54:[ ]+4c000020[ ]+[ ]+ret[ ]+
diff --git a/gas/testsuite/gas/loongarch/li.d b/gas/testsuite/gas/loongarch/li.d
index 850a3f48e30..bb53fb1496e 100644
--- a/gas/testsuite/gas/loongarch/li.d
+++ b/gas/testsuite/gas/loongarch/li.d
@@ -8,14 +8,14 @@
Disassembly of section .text:
00000000.* <_start>:
-[ ]+0:[ ]+03803c06[ ]+ori[ ]+\$a2,[ ]+\$zero,[ ]+0xf
+[ ]+0:[ ]+03803c06[ ]+li.w[ ]+\$a2,[ ]+0xf
[ ]+4:[ ]+1a000005[ ]+pcalau12i[ ]+\$a1,[ ]+0
[ ]+4:[ ]+R_LARCH_PCALA_HI20[ ]+.rodata
[ ]+8:[ ]+02c000a5[ ]+addi.d[ ]+\$a1,[ ]+\$a1,[ ]+0
[ ]+8:[ ]+R_LARCH_PCALA_LO12[ ]+.rodata
-[ ]+c:[ ]+03800404[ ]+ori[ ]+\$a0,[ ]+\$zero,[ ]+0x1
-[ ]+10:[ ]+0381000b[ ]+ori[ ]+\$a7,[ ]+\$zero,[ ]+0x40
+[ ]+c:[ ]+03800404[ ]+li.w[ ]+\$a0,[ ]+0x1
+[ ]+10:[ ]+0381000b[ ]+li.w[ ]+\$a7,[ ]+0x40
[ ]+14:[ ]+002b0000[ ]+syscall[ ]+0x0
[ ]+18:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+1c:[ ]+0381740b[ ]+ori[ ]+\$a7,[ ]+\$zero,[ ]+0x5d
+[ ]+1c:[ ]+0381740b[ ]+li.w[ ]+\$a7,[ ]+0x5d
[ ]+20:[ ]+002b0000[ ]+syscall[ ]+0x0
diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loongarch/macro_op.d
index d264c4f25c5..7ffb3e7b9c6 100644
--- a/gas/testsuite/gas/loongarch/macro_op.d
+++ b/gas/testsuite/gas/loongarch/macro_op.d
@@ -9,9 +9,9 @@ Disassembly of section .text:
00000000.* <.text>:
[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+4:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+4:[ ]+02bffc04[ ]+li.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+c:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc04[ ]+li.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+14:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0
diff --git a/gas/testsuite/gas/loongarch/macro_op_large_abs.d b/gas/testsuite/gas/loongarch/macro_op_large_abs.d
index c3214a859e6..3c35ef81223 100644
--- a/gas/testsuite/gas/loongarch/macro_op_large_abs.d
+++ b/gas/testsuite/gas/loongarch/macro_op_large_abs.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
00000000.* <.text>:
[ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+.text
-[ ]+4:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+4:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0
[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+.text
[ ]+8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+8:[ ]+R_LARCH_PCALA64_LO20[ ]+.text
@@ -19,7 +19,7 @@ Disassembly of section .text:
[ ]+10:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+14:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+14:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text
-[ ]+18:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+18:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0
[ ]+18:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text
[ ]+1c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+1c:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.text
@@ -28,7 +28,7 @@ Disassembly of section .text:
[ ]+24:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+28:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+28:[ ]+R_LARCH_PCALA_HI20[ ]+.text
-[ ]+2c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+2c:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0
[ ]+2c:[ ]+R_LARCH_PCALA_LO12[ ]+.text
[ ]+30:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+30:[ ]+R_LARCH_PCALA64_LO20[ ]+.text
@@ -37,7 +37,7 @@ Disassembly of section .text:
[ ]+38:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+3c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+3c:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text
-[ ]+40:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+40:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0
[ ]+40:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text
[ ]+44:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+44:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.text
@@ -50,7 +50,7 @@ Disassembly of section .text:
[ ]+54:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1
[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+58:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
-[ ]+5c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+5c:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0
[ ]+5c:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1
[ ]+60:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+60:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1
@@ -59,7 +59,7 @@ Disassembly of section .text:
[ ]+68:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+6c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+6c:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1
-[ ]+70:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+70:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0
[ ]+70:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+74:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+74:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1
@@ -68,7 +68,7 @@ Disassembly of section .text:
[ ]+7c:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+80:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+80:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1
-[ ]+84:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+84:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0
[ ]+84:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+88:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+88:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1
diff --git a/gas/testsuite/gas/loongarch/macro_op_large_pc.d b/gas/testsuite/gas/loongarch/macro_op_large_pc.d
index c3214a859e6..3c35ef81223 100644
--- a/gas/testsuite/gas/loongarch/macro_op_large_pc.d
+++ b/gas/testsuite/gas/loongarch/macro_op_large_pc.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
00000000.* <.text>:
[ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+.text
-[ ]+4:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+4:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0
[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+.text
[ ]+8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+8:[ ]+R_LARCH_PCALA64_LO20[ ]+.text
@@ -19,7 +19,7 @@ Disassembly of section .text:
[ ]+10:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+14:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+14:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text
-[ ]+18:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+18:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0
[ ]+18:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text
[ ]+1c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+1c:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.text
@@ -28,7 +28,7 @@ Disassembly of section .text:
[ ]+24:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+28:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+28:[ ]+R_LARCH_PCALA_HI20[ ]+.text
-[ ]+2c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+2c:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0
[ ]+2c:[ ]+R_LARCH_PCALA_LO12[ ]+.text
[ ]+30:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+30:[ ]+R_LARCH_PCALA64_LO20[ ]+.text
@@ -37,7 +37,7 @@ Disassembly of section .text:
[ ]+38:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+3c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+3c:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text
-[ ]+40:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+40:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0
[ ]+40:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text
[ ]+44:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+44:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.text
@@ -50,7 +50,7 @@ Disassembly of section .text:
[ ]+54:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1
[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+58:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
-[ ]+5c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+5c:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0
[ ]+5c:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1
[ ]+60:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+60:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1
@@ -59,7 +59,7 @@ Disassembly of section .text:
[ ]+68:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+6c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+6c:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1
-[ ]+70:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+70:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0
[ ]+70:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+74:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+74:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1
@@ -68,7 +68,7 @@ Disassembly of section .text:
[ ]+7c:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+80:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+80:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1
-[ ]+84:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+84:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0
[ ]+84:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+88:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+88:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1
diff --git a/gas/testsuite/gas/loongarch/nop.d b/gas/testsuite/gas/loongarch/nop.d
index 4cdcc5ce0d2..222456e8b8c 100644
--- a/gas/testsuite/gas/loongarch/nop.d
+++ b/gas/testsuite/gas/loongarch/nop.d
@@ -7,4 +7,4 @@
Disassembly of section .text:
0+000 <target>:
-[ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero, \$zero, 0x0
+[ ]+0:[ ]+03400000[ ]+nop[ ]+
diff --git a/gas/testsuite/gas/loongarch/reloc.d b/gas/testsuite/gas/loongarch/reloc.d
index 6f5f110b1af..c3820c55f98 100644
--- a/gas/testsuite/gas/loongarch/reloc.d
+++ b/gas/testsuite/gas/loongarch/reloc.d
@@ -8,7 +8,7 @@
Disassembly of section .text:
00000000.* <.text>:
-[ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0
+[ ]+0:[ ]+03400000[ ]+nop[ ]+
[ ]+4:[ ]+58000085[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0x4
[ ]+4:[ ]+R_LARCH_B16[ ]+.L1
[ ]+8:[ ]+5c000085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0x8
diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h
index c3922348a56..251621a239f 100644
--- a/include/opcode/loongarch.h
+++ b/include/opcode/loongarch.h
@@ -118,6 +118,8 @@ dec2 : [1-9][0-9]?
const unsigned long pinfo;
#define USELESS 0x0l
+/* Instruction is a simple alias only for disassembler use. */
+#define INSN_DIS_ALIAS 0x00000001l
};
struct hash_control;
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 9dcf989d0df..036eb8f2b0f 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -25,6 +25,14 @@
#include "libiberty.h"
#include <stdlib.h>
+static bool loongarch_dis_show_aliases = true;
+static const char *const *loongarch_r_disname = NULL;
+static const char *const *loongarch_f_disname = NULL;
+static const char *const *loongarch_c_disname = NULL;
+static const char *const *loongarch_cr_disname = NULL;
+static const char *const *loongarch_v_disname = NULL;
+static const char *const *loongarch_x_disname = NULL;
+
static const struct loongarch_opcode *
get_loongarch_opcode_by_binfmt (insn_t insn)
{
@@ -41,7 +49,9 @@ get_loongarch_opcode_by_binfmt (insn_t insn)
{
for (it = ase->opcodes; it->mask; it++)
if (!ase->opc_htab[LARCH_INSN_OPC (it->match)]
- && it->macro == NULL)
+ && it->macro == NULL
+ && (!(it->pinfo & INSN_DIS_ALIAS)
+ || loongarch_dis_show_aliases))
ase->opc_htab[LARCH_INSN_OPC (it->match)] = it;
for (i = 0; i < 16; i++)
if (!ase->opc_htab[i])
@@ -59,13 +69,6 @@ get_loongarch_opcode_by_binfmt (insn_t insn)
return NULL;
}
-static const char *const *loongarch_r_disname = NULL;
-static const char *const *loongarch_f_disname = NULL;
-static const char *const *loongarch_c_disname = NULL;
-static const char *const *loongarch_cr_disname = NULL;
-static const char *const *loongarch_v_disname = NULL;
-static const char *const *loongarch_x_disname = NULL;
-
static void
set_default_loongarch_dis_options (void)
{
@@ -87,6 +90,9 @@ set_default_loongarch_dis_options (void)
static int
parse_loongarch_dis_option (const char *option)
{
+ if (strcmp (option, "no-aliases") == 0)
+ loongarch_dis_show_aliases = false;
+
if (strcmp (option, "numeric") == 0)
{
loongarch_r_disname = loongarch_r_normal_name;
@@ -301,6 +307,8 @@ print_loongarch_disassembler_options (FILE *stream)
The following LoongArch disassembler options are supported for use\n\
with the -M switch (multiple options should be separated by commas):\n"));
+ fprintf (stream, _("\n\
+ no-aliases Use canonical instruction forms.\n"));
fprintf (stream, _("\n\
numeric Print numeric register names, rather than ABI names.\n"));
fprintf (stream, _("\n"));
diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
index 1b510048c29..2ea9effdbf9 100644
--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
@@ -331,9 +331,29 @@ static struct loongarch_opcode loongarch_macro_opcodes[] =
{ 0 } /* Terminate the list. */
};
+static struct loongarch_opcode loongarch_alias_opcodes[] =
+{
+ /* match, mask, name, format, macro, include, exclude, pinfo. */
+ { 0x00150000, 0xfffffc00, "move", "r0:5,r5:5", 0, 0, 0, INSN_DIS_ALIAS }, /* or rd, rj, zero */
+ { 0x02800000, 0xffc003e0, "li.w", "r0:5,s10:12", 0, 0, 0, INSN_DIS_ALIAS }, /* addi.w rd, zero, simm */
+ { 0x02c00000, 0xffc003e0, "li.d", "r0:5,s10:12", 0, 0, 0, INSN_DIS_ALIAS }, /* addi.d rd, zero, simm */
+ { 0x03400000, 0xffffffff, "nop", "", 0, 0, 0, INSN_DIS_ALIAS }, /* andi zero, zero, 0 */
+ { 0x03800000, 0xffc003e0, "li.w", "r0:5,u10:12", 0, 0, 0, INSN_DIS_ALIAS }, /* ori rd, zero, uimm */
+ /* ret must come before jr because it is more specific. */
+ { 0x4c000020, 0xffffffff, "ret", "", 0, 0, 0, INSN_DIS_ALIAS }, /* jirl zero, ra, 0 */
+ { 0x4c000000, 0xfffffc1f, "jr", "r5:5", 0, 0, 0, INSN_DIS_ALIAS }, /* jirl zero, rj, 0 */
+ { 0x60000000, 0xfc00001f, "bltz", "r5:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* blt rj, zero, offset */
+ { 0x60000000, 0xfc0003e0, "bgtz", "r0:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* blt zero, rd, offset */
+ { 0x64000000, 0xfc00001f, "bgez", "r5:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* bge rj, zero, offset */
+ { 0x64000000, 0xfc0003e0, "blez", "r0:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* bge zero, rd, offset */
+ { 0 } /* Terminate the list. */
+};
+
+
static struct loongarch_opcode loongarch_fix_opcodes[] =
{
/* match, mask, name, format, macro, include, exclude, pinfo. */
+ { 0x0, 0x0, "move", "r,r", "or %1,%2,$r0", 0, 0, 0 },
{ 0x00001000, 0xfffffc00, "clo.w", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00001400, 0xfffffc00, "clz.w", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00001800, 0xfffffc00, "cto.w", "r0:5,r5:5", 0, 0, 0, 0 },
@@ -354,8 +374,6 @@ static struct loongarch_opcode loongarch_fix_opcodes[] =
{ 0x00005400, 0xfffffc00, "bitrev.d", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00005800, 0xfffffc00, "ext.w.h", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00005c00, 0xfffffc00, "ext.w.b", "r0:5,r5:5", 0, 0, 0, 0 },
- /* or %1,%2,$r0 */
- { 0x00150000, 0xfffffc00, "move", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00006000, 0xfffffc00, "rdtimel.w", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00006400, 0xfffffc00, "rdtimeh.w", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00006800, 0xfffffc00, "rdtime.d", "r0:5,r5:5", 0, 0, 0, 0 },
@@ -848,6 +866,7 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] =
struct loongarch_ase loongarch_ASEs[] =
{
{ &LARCH_opts.ase_ilp32, loongarch_macro_opcodes, 0, 0, { 0 }, 0, 0 },
+ { &LARCH_opts.ase_ilp32, loongarch_alias_opcodes, 0, 0, { 0 }, 0, 0 },
{ &LARCH_opts.ase_ilp32, loongarch_imm_opcodes, 0, 0, { 0 }, 0, 0 },
{ &LARCH_opts.ase_ilp32, loongarch_privilege_opcodes, 0, 0, { 0 }, 0, 0 },
{ &LARCH_opts.ase_ilp32, loongarch_load_store_opcodes, 0, 0, { 0 }, 0, 0 },
--
2.38.1
next prev parent reply other threads:[~2022-12-14 5:52 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-14 5:51 [PATCH v3 RESEND 0/6] LoongArch: colored disassembly and readability tweaks WANG Xuerui
2022-12-14 5:51 ` WANG Xuerui [this message]
2022-12-14 5:52 ` [PATCH v3 2/6] opcodes/loongarch: remove unused code WANG Xuerui
2022-12-14 5:52 ` [PATCH v3 3/6] opcodes/loongarch: implement style support in the disassembler WANG Xuerui
2023-01-17 10:37 ` Andrew Burgess
2022-12-14 5:52 ` [PATCH v3 4/6] opcodes/loongarch: style disassembled address offsets as such WANG Xuerui
2022-12-14 5:52 ` [PATCH v3 5/6] opcodes/loongarch: do not print hex notation for signed immediates WANG Xuerui
2022-12-14 5:52 ` [PATCH v3 6/6] opcodes/loongarch: print unrecognized insn words with the .word directive WANG Xuerui
2023-01-03 4:05 ` [PATCH v3 RESEND 0/6] LoongArch: colored disassembly and readability tweaks WANG Xuerui
2023-01-03 11:10 ` mengqinggang
2023-01-03 11:16 ` WANG Xuerui
-- strict thread matches above, loose matches on Subject: below --
2022-12-14 5:46 [PATCH v3 " WANG Xuerui
2022-12-14 5:46 ` [PATCH v3 1/6] LoongArch: support disassembling certain pseudo-instructions WANG Xuerui
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