From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mailbox.box.xen0n.name (mail.xen0n.name [115.28.160.31]) by sourceware.org (Postfix) with ESMTPS id 68A983836D3E for ; Wed, 14 Dec 2022 05:52:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 68A983836D3E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xen0n.name DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xen0n.name; s=mail; t=1670997129; bh=Zn6JnxHqFsPi3wIgXCMAFrjWcURC7ZLaKvYschbVejI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ij+XOczI/CfSCcpmRqCFW+EBeuafRGJIxM6doQsYHqAbmW/M8ZjZ5+KBO4u2C+9fY zppHTw2l/nMJbFgzzOSctVLXW8crclvvbJ2GIRfhCUdf7pLB9DcDs9oCdKuDzhwJ7z v1UR/aPSCB0IvZmrjhKOFcNhikyy2PxkOPk8uyds= Received: from ld50.lan (unknown [101.88.134.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 4D072601A1; Wed, 14 Dec 2022 13:52:09 +0800 (CST) From: WANG Xuerui To: binutils@sourceware.org Cc: Chenghua Xu , Zhensong Liu , Qinggang Meng , Xi Ruoyao , WANG Xuerui Subject: [PATCH v3 4/6] opcodes/loongarch: style disassembled address offsets as such Date: Wed, 14 Dec 2022 13:52:02 +0800 Message-Id: <20221214055204.2890795-5-i.swmail@xen0n.name> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221214055204.2890795-1-i.swmail@xen0n.name> References: <20221214055204.2890795-1-i.swmail@xen0n.name> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_BARRACUDACENTRAL,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: WANG Xuerui Add a modifier char 'o' telling the disassembler to print the immediate using the address offset style, and mark the memory access instructions' offset operands as such. --- opcodes/loongarch-dis.c | 19 +++++++++++++--- opcodes/loongarch-opc.c | 50 ++++++++++++++++++++--------------------- 2 files changed, 41 insertions(+), 28 deletions(-) diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c index 44f035b2181..86858f2b693 100644 --- a/opcodes/loongarch-dis.c +++ b/opcodes/loongarch-dis.c @@ -132,6 +132,7 @@ dis_one_arg (char esc1, char esc2, const char *bit_field, struct disassemble_info *info = context; insn_t insn = *(insn_t *) info->private_data; int32_t imm, u_imm; + enum disassembler_style style; if (esc1) { @@ -167,14 +168,26 @@ dis_one_arg (char esc1, char esc2, const char *bit_field, info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_x_disname[u_imm]); break; case 'u': - info->fprintf_styled_func (info->stream, dis_style_immediate, "0x%x", u_imm); + style = esc2 == 'o' ? dis_style_address_offset : dis_style_immediate; + info->fprintf_styled_func (info->stream, style, "0x%x", u_imm); break; case 's': + switch (esc2) + { + case 'b': + case 'o': + /* Both represent address offsets. */ + style = dis_style_address_offset; + break; + default: + style = dis_style_immediate; + break; + } if (imm == 0) - info->fprintf_styled_func (info->stream, dis_style_immediate, "%d", imm); + info->fprintf_styled_func (info->stream, style, "%d", imm); else { - info->fprintf_styled_func (info->stream, dis_style_immediate, "%d", imm); + info->fprintf_styled_func (info->stream, style, "%d", imm); info->fprintf_styled_func (info->stream, dis_style_text, "(0x%x)", u_imm); } switch (esc2) diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c index 2ea9effdbf9..0d80562e992 100644 --- a/opcodes/loongarch-opc.c +++ b/opcodes/loongarch-opc.c @@ -663,26 +663,26 @@ static struct loongarch_opcode loongarch_4opt_double_float_opcodes[] = static struct loongarch_opcode loongarch_load_store_opcodes[] = { /* match, mask, name, format, macro, include, exclude, pinfo. */ - { 0x20000000, 0xff000000, "ll.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x21000000, 0xff000000, "sc.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x22000000, 0xff000000, "ll.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x23000000, 0xff000000, "sc.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x24000000, 0xff000000, "ldptr.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x25000000, 0xff000000, "stptr.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x26000000, 0xff000000, "ldptr.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x27000000, 0xff000000, "stptr.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x28000000, 0xffc00000, "ld.b", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x28400000, 0xffc00000, "ld.h", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x28800000, 0xffc00000, "ld.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x28c00000, 0xffc00000, "ld.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x29000000, 0xffc00000, "st.b", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x29400000, 0xffc00000, "st.h", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x29800000, 0xffc00000, "st.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x29c00000, 0xffc00000, "st.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x2a000000, 0xffc00000, "ld.bu", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x2a400000, 0xffc00000, "ld.hu", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x2a800000, 0xffc00000, "ld.wu", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x2ac00000, 0xffc00000, "preld", "u0:5,r5:5,s10:12", 0, 0, 0, 0 }, + { 0x20000000, 0xff000000, "ll.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x21000000, 0xff000000, "sc.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x22000000, 0xff000000, "ll.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x23000000, 0xff000000, "sc.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x24000000, 0xff000000, "ldptr.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x25000000, 0xff000000, "stptr.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x26000000, 0xff000000, "ldptr.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x27000000, 0xff000000, "stptr.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x28000000, 0xffc00000, "ld.b", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x28400000, 0xffc00000, "ld.h", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x28800000, 0xffc00000, "ld.w", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x28c00000, 0xffc00000, "ld.d", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x29000000, 0xffc00000, "st.b", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x29400000, 0xffc00000, "st.h", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x29800000, 0xffc00000, "st.w", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x29c00000, 0xffc00000, "st.d", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x2a000000, 0xffc00000, "ld.bu", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x2a400000, 0xffc00000, "ld.hu", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x2a800000, 0xffc00000, "ld.wu", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x2ac00000, 0xffc00000, "preld", "u0:5,r5:5,so10:12", 0, 0, 0, 0 }, { 0x38000000, 0xffff8000, "ldx.b", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, { 0x38040000, 0xffff8000, "ldx.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, { 0x38080000, 0xffff8000, "ldx.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, @@ -791,8 +791,8 @@ static struct loongarch_opcode loongarch_load_store_opcodes[] = static struct loongarch_opcode loongarch_single_float_load_store_opcodes[] = { /* match, mask, name, format, macro, include, exclude, pinfo. */ - { 0x2b000000, 0xffc00000, "fld.s", "f0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x2b400000, 0xffc00000, "fst.s", "f0:5,r5:5,s10:12", 0, 0, 0, 0 }, + { 0x2b000000, 0xffc00000, "fld.s", "f0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x2b400000, 0xffc00000, "fst.s", "f0:5,r5:5,so10:12", 0, 0, 0, 0 }, { 0x38300000, 0xffff8000, "fldx.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, { 0x38380000, 0xffff8000, "fstx.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, { 0x38740000, 0xffff8000, "fldgt.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, @@ -805,8 +805,8 @@ static struct loongarch_opcode loongarch_single_float_load_store_opcodes[] = static struct loongarch_opcode loongarch_double_float_load_store_opcodes[] = { /* match, mask, name, format, macro, include, exclude, pinfo. */ - { 0x2b800000, 0xffc00000, "fld.d", "f0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x2bc00000, 0xffc00000, "fst.d", "f0:5,r5:5,s10:12", 0, 0, 0, 0 }, + { 0x2b800000, 0xffc00000, "fld.d", "f0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x2bc00000, 0xffc00000, "fst.d", "f0:5,r5:5,so10:12", 0, 0, 0, 0 }, { 0x38340000, 0xffff8000, "fldx.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, { 0x383c0000, 0xffff8000, "fstx.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, { 0x38748000, 0xffff8000, "fldgt.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, @@ -832,7 +832,7 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] = { 0x40000000, 0xfc000000, "beqz", "r5:5,sb0:5|10:16<<2", 0, 0, 0, 0 }, { 0x0, 0x0, "bnez", "r,la", "bnez %1,%%b21(%2)", 0, 0, 0 }, { 0x44000000, 0xfc000000, "bnez", "r5:5,sb0:5|10:16<<2", 0, 0, 0, 0 }, - { 0x4c000000, 0xfc000000, "jirl", "r0:5,r5:5,s10:16<<2", 0, 0, 0, 0 }, + { 0x4c000000, 0xfc000000, "jirl", "r0:5,r5:5,so10:16<<2", 0, 0, 0, 0 }, { 0x0, 0x0, "b", "la", "b %%b26(%1)", 0, 0, 0 }, { 0x50000000, 0xfc000000, "b", "sb0:10|10:16<<2", 0, 0, 0, 0 }, { 0x0, 0x0, "bl", "la", "bl %%b26(%1)", 0, 0, 0 }, -- 2.38.1