From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from zg8tndyumtaxlji0oc4xnzya.icoremail.net (zg8tndyumtaxlji0oc4xnzya.icoremail.net [46.101.248.176]) by sourceware.org (Postfix) with SMTP id DCF133835892 for ; Wed, 14 Dec 2022 07:32:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org DCF133835892 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from host014-ubuntu-1804.lxd (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id EwgMCgAX3YUbfJljVFYZAA--.34973S4; Wed, 14 Dec 2022 15:32:43 +0800 (CST) From: Li Xu To: binutils@sourceware.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Li Xu Subject: [PATCH v2] RISC-V: Add string length check for operands in AS Date: Wed, 14 Dec 2022 07:32:40 +0000 Message-Id: <20221214073240.24973-1-xuli1@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID:EwgMCgAX3YUbfJljVFYZAA--.34973S4 X-Coremail-Antispam: 1UD129KBjvJXoWxXw4kuw4kAF47XFWrAr15twb_yoW5Zr4Dpa y8Gw1jkrZ5XF97t3s8KrW5Ca17Aa109rs09r1fAw12krW8GFy2yanrtr17XFsIvFWY93yr Aa1DZrWrZr1UJaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUvS14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc7CjxVAaw2AFwI0_ JF0_Jw1lc2xSY4AK6svPMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI 8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AK xVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI 8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280 aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43 ZEXa7VUbhvttUUUUU== X-CM-SenderInfo: 50xoxi46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The patch I previously submitted: | Date: Tue Dec 13 04:34:28 GMT 2022 | Subject: [PATCH] RISC-V: Add string length check for operands in AS | Message-ID: The current AS accepts invalid operands due to miss of operands length check. For example, "e6" is an invalid operand in (vsetvli a0, a1, e6, mf8, tu, ma), but it's still accepted by assembler. In detail, the condition check "strncmp (array[i], *s, len) == 0" in arg_lookup function passes with "strncmp ("e64", "e6", 2)" in the case above. So the generated encoding is same as that of (vsetvli a0, a1, e64, mf8, tu, ma). This patch fixes issue above by prompting an error in such case and also adds a new testcase. gas/ChangeLog: * config/tc-riscv.c (arg_lookup): Add string length check for operands. * testsuite/gas/riscv/vector-insns-fail-vsew.d: New testcase for an illegal vsew. * testsuite/gas/riscv/vector-insns-fail-vsew.l: Likewise. * testsuite/gas/riscv/vector-insns-fail-vsew.s: Likewise. --- gas/config/tc-riscv.c | 3 ++- gas/testsuite/gas/riscv/vector-insns-fail-vsew.d | 3 +++ gas/testsuite/gas/riscv/vector-insns-fail-vsew.l | 3 +++ gas/testsuite/gas/riscv/vector-insns-fail-vsew.s | 1 + 4 files changed, 9 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-vsew.d create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-vsew.l create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-vsew.s diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 0682eb35524..42c041155c5 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1206,7 +1206,8 @@ arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) return false; for (i = 0; i < size; i++) - if (array[i] != NULL && strncmp (array[i], *s, len) == 0) + if (array[i] != NULL && strncmp (array[i], *s, len) == 0 + && array[i][len] == '\0') { *regnop = i; *s += len; diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-vsew.d b/gas/testsuite/gas/riscv/vector-insns-fail-vsew.d new file mode 100644 index 00000000000..c0c81579741 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-fail-vsew.d @@ -0,0 +1,3 @@ +#as: -march=rv32ifv +#source: vector-insns-fail-vsew.s +#error_output: vector-insns-fail-vsew.l diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-vsew.l b/gas/testsuite/gas/riscv/vector-insns-fail-vsew.l new file mode 100644 index 00000000000..87a2c22a805 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-fail-vsew.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: instruction vsetvli requires absolute expression +.*: Error: illegal operands `vsetvli a0,a1,e6,mf8,tu,ma' diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-vsew.s b/gas/testsuite/gas/riscv/vector-insns-fail-vsew.s new file mode 100644 index 00000000000..b8f3242406f --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-fail-vsew.s @@ -0,0 +1 @@ + vsetvli a0, a1, e6, mf8, tu, ma # unrecognized vsew -- 2.17.1