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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t18-20020a17090605d200b007c16430e5c8sm7344770ejt.92.2022.12.21.09.07.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 09:07:14 -0800 (PST) From: Christoph Muellner To: binutils@sourceware.org, Nelson Chu , Andrew Waterman , Palmer Dabbelt , Jim Wilson , Philipp Tomsich , Aaron Durbin , Andrew de los Reyes , Eric Gouriou , Barna Ibrahim Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [RFC PATCH 4/6] RISC-V: Add Zvkn ISA extension support Date: Wed, 21 Dec 2022 18:07:04 +0100 Message-Id: <20221221170706.2877188-5-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221170706.2877188-1-christoph.muellner@vrull.eu> References: <20221221170706.2877188-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_MANYTO,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph Müllner This commit adds the Zvkn ISA extension instructions, which are part of the vector crypto extensions. Signed-off-by: Christoph Müllner --- bfd/elfxx-riscv.c | 5 +++++ gas/testsuite/gas/riscv/zvkn.d | 21 ++++++++++++++++++++ gas/testsuite/gas/riscv/zvkn.s | 13 +++++++++++++ include/opcode/riscv-opc.h | 35 ++++++++++++++++++++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 13 +++++++++++++ 6 files changed, 88 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zvkn.d create mode 100644 gas/testsuite/gas/riscv/zvkn.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index fad49e4176a..b672e610a54 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1209,6 +1209,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2430,6 +2431,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, case INSN_CLASS_ZVKHA_OR_ZVKHB: return (riscv_subset_supports (rps, "zvkha") || riscv_subset_supports (rps, "zvkhb")); + case INSN_CLASS_ZVKN: + return riscv_subset_supports (rps, "zvkn"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2596,6 +2599,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zvkha"); case INSN_CLASS_ZVKHB: return _("zvkhb"); + case INSN_CLASS_ZVKN: + return _("zvkn"); case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/testsuite/gas/riscv/zvkn.d b/gas/testsuite/gas/riscv/zvkn.d new file mode 100644 index 00000000000..5d477721442 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkn.d @@ -0,0 +1,21 @@ +#as: -march=rv64gc_zvkn +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+a280a277[ ]+vaesdf.vv[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a680a277[ ]+vaesdf.vs[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a2802277[ ]+vaesdm.vv[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a6802277[ ]+vaesdm.vs[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a281a277[ ]+vaesef.vv[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a681a277[ ]+vaesef.vs[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a2812277[ ]+vaesem.vv[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a6812277[ ]+vaesem.vs[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+8a812277[ ]+vaeskf1.vi[ ]+v4,v8,2 +[ ]+[0-9a-f]+:[ ]+8a872277[ ]+vaeskf1.vi[ ]+v4,v8,14 +[ ]+[0-9a-f]+:[ ]+aa812277[ ]+vaeskf2.vi[ ]+v4,v8,2 +[ ]+[0-9a-f]+:[ ]+aa872277[ ]+vaeskf2.vi[ ]+v4,v8,14 +[ ]+[0-9a-f]+:[ ]+a683a277[ ]+vaesz.vs[ ]+v4,v8 diff --git a/gas/testsuite/gas/riscv/zvkn.s b/gas/testsuite/gas/riscv/zvkn.s new file mode 100644 index 00000000000..f0f3811eaec --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkn.s @@ -0,0 +1,13 @@ + vaesdf.vv v4, v8 + vaesdf.vs v4, v8 + vaesdm.vv v4, v8 + vaesdm.vs v4, v8 + vaesef.vv v4, v8 + vaesef.vs v4, v8 + vaesem.vv v4, v8 + vaesem.vs v4, v8 + vaeskf1.vi v4, v8, 2 + vaeskf1.vi v4, v8, 14 + vaeskf2.vi v4, v8, 2 + vaeskf2.vi v4, v8, 14 + vaesz.vs v4, v8 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 2d22f88acb7..86b04ce16a0 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2094,6 +2094,29 @@ #define MASK_VSHA2CLVV 0xfe00707f #define MATCH_VSHA2MSVV 0xb6002077 #define MASK_VSHA2MSVV 0xfe00707f +/* Zvkn instructions. */ +#define MATCH_VAESDFVV 0xa200a077 +#define MASK_VAESDFVV 0xfe0ff07f +#define MATCH_VAESDFVS 0xa600a077 +#define MASK_VAESDFVS 0xfe0ff07f +#define MATCH_VAESDMVV 0xa2002077 +#define MASK_VAESDMVV 0xfe0ff07f +#define MATCH_VAESDMVS 0xa6002077 +#define MASK_VAESDMVS 0xfe0ff07f +#define MATCH_VAESEFVV 0xa201a077 +#define MASK_VAESEFVV 0xfe0ff07f +#define MATCH_VAESEFVS 0xa601a077 +#define MASK_VAESEFVS 0xfe0ff07f +#define MATCH_VAESEMVV 0xa2012077 +#define MASK_VAESEMVV 0xfe0ff07f +#define MATCH_VAESEMVS 0xa6012077 +#define MASK_VAESEMVS 0xfe0ff07f +#define MATCH_VAESKF1VI 0x8a002077 +#define MASK_VAESKF1VI 0xfe00707f +#define MATCH_VAESKF2VI 0xaa002077 +#define MASK_VAESKF2VI 0xfe00707f +#define MATCH_VAESZVS 0xa603a077 +#define MASK_VAESZVS 0xfe0ff07f /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3178,6 +3201,18 @@ DECLARE_INSN(vghmacvv, MATCH_VGHMACVV, MASK_VGHMACVV) DECLARE_INSN(vsha2chvv, MATCH_VSHA2CHVV, MASK_VSHA2CHVV) DECLARE_INSN(vsha2clvv, MATCH_VSHA2CLVV, MASK_VSHA2CLVV) DECLARE_INSN(vsha2msvv, MATCH_VSHA2MSVV, MASK_VSHA2MSVV) +/* Zvkn instructions. */ +DECLARE_INSN(vaesdfvv, MATCH_VAESDFVV, MASK_VAESDFVV) +DECLARE_INSN(vaesdfvs, MATCH_VAESDFVS, MASK_VAESDFVS) +DECLARE_INSN(vaesdmvv, MATCH_VAESDMVV, MASK_VAESDMVV) +DECLARE_INSN(vaesdmvs, MATCH_VAESDMVS, MASK_VAESDMVS) +DECLARE_INSN(vaesefvv, MATCH_VAESEFVV, MASK_VAESEFVV) +DECLARE_INSN(vaesefvs, MATCH_VAESEFVS, MASK_VAESEFVS) +DECLARE_INSN(vaesemvv, MATCH_VAESEMVV, MASK_VAESEMVV) +DECLARE_INSN(vaesemvs, MATCH_VAESEMVS, MASK_VAESEMVS) +DECLARE_INSN(vaeskf1vi, MATCH_VAESKF1VI, MASK_VAESKF1VI) +DECLARE_INSN(vaeskf2vi, MATCH_VAESKF2VI, MASK_VAESKF2VI) +DECLARE_INSN(vaeszvs, MATCH_VAESZVS, MASK_VAESZVS) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index be5650297a7..f36fc1be2ed 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -414,6 +414,7 @@ enum riscv_insn_class INSN_CLASS_ZVKHA, INSN_CLASS_ZVKHB, INSN_CLASS_ZVKHA_OR_ZVKHB, + INSN_CLASS_ZVKN, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 35d3e653147..79c123927b7 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1839,6 +1839,19 @@ const struct riscv_opcode riscv_opcodes[] = {"vsha2cl.vv", 0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2CLVV, MASK_VSHA2CLVV, match_opcode, 0}, {"vsha2ms.vv", 0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2MSVV, MASK_VSHA2MSVV, match_opcode, 0}, +/* Zvkn instructions. */ +{"vaesdf.vv", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESDFVV, MASK_VAESDFVV, match_opcode, 0}, +{"vaesdf.vs", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESDFVS, MASK_VAESDFVV, match_opcode, 0}, +{"vaesdm.vv", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESDMVV, MASK_VAESDMVV, match_opcode, 0}, +{"vaesdm.vs", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESDMVS, MASK_VAESDMVV, match_opcode, 0}, +{"vaesef.vv", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESEFVV, MASK_VAESEFVV, match_opcode, 0}, +{"vaesef.vs", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESEFVS, MASK_VAESEFVV, match_opcode, 0}, +{"vaesem.vv", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESEMVV, MASK_VAESEMVV, match_opcode, 0}, +{"vaesem.vs", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESEMVS, MASK_VAESEMVV, match_opcode, 0}, +{"vaeskf1.vi", 0, INSN_CLASS_ZVKN, "Vd,Vt,Vj", MATCH_VAESKF1VI, MASK_VAESKF1VI, match_opcode, 0}, +{"vaeskf2.vi", 0, INSN_CLASS_ZVKN, "Vd,Vt,Vj", MATCH_VAESKF2VI, MASK_VAESKF2VI, match_opcode, 0}, +{"vaesz.vs", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESZVS, MASK_VAESZVS, match_opcode, 0}, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS }, -- 2.38.1